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NOTE: CHEATING IN ANY FORM WILL NULLIFY YOUR EXAM AND WILL BE A GROUND FOR AN
AUTOMATIC GRADE OF 5.00.
MULTIPLE CHOICE: Select the most appropriate answer from the given choices.
2. A datapath, when combined with the control unit, forms a component referred to as ______.
a. central processing unit c. output unit
b. input unit d. memory unit
3. The equivalent of the decimal number 7562.45 in the octal numbering system is _________
a. 11612.646 c. 11612.346
b. 16612.346 d. 6612.436
5. Using the 2’s complement method, the result of subtracting 11011101 from 10100110 is _______
a. – 0 0 0 1 0 1 1 1 c. – 0 0 1 1 0 1 1 1
b. 0 0 1 1 0 1 1 1 d. – 0 0 1 0 0 1 0 1
6. Each of the following 4 numbers has a different base. Which of the four numbers have the same
value in decimal ?
a. b & d c. a & c
b. c & d d. none of these
7. Given two decimal numbers 694 and 835. Their sum in BCD is ________
a. 00111111001001 c. 0001010100101001
b. 01011111001001 d. none of these
12. This is the basic mathematics needed for the study of the logic design of digital systems.
a. Combinational Design c. Boolean Algebra
b. Sequential Design d. Quine-McCluskey Technique
13. This has one or more inputs and one or more outputs which take on discrete values.
a. digital system c. finite state machine
b. switching circuit d. algorithmic state machine
14. This part of the design of digital system involves determining how to interconnect basic logic
building blocks to perform a specific function
a. structural diagram c. iterative design
b. behavioral design d. logic design
15. The simplest form of the Boolean expression (a + b’ + c’)(a’ + c’) in product-of-sums form is _____
a. (a + c’)(c’ + b) c. (a’ + c’)(c’ + b)
b. (a’ + c’)(c’ + b’) d. none of these
16. The reduced form of the Boolean expression (A’ + C)(A’ + C’)(A + B + C’D) is _______
a. A’B + A’C’D c. AB’ + A’CD’
b. A’B’ + AC’D’ d. none of these
17. The minterm expansion of the Boolean expression A’B’C’D’ + AC’D’ + B’CD’ + A’BCD + BC’D is
a. ∑m(1, 2, 3, 6, 9, 10, 12, 14) c. ∑m(0, 2, 5, 7, 8, 10, 12, 13)
b. ∑m(0, 1, 5, 7, 9, 10, 12, 13) d. none of these
18. What logical reason/s can you give why NAND and NOR gates are considered universal gates?
a. they can appear anywhere in the circuit c. they can imitate function of other gates
b. they can produce universal operation d. they cannot be partial
20. This is the time needed by a gate in processing its input signals before the output signal can be
generated
a. setup time c. hold time
b. threshold time d. none of these
23. What will happen if the function v(w+x+y)z would be implemented using NOR gates?
a. Not possible using NOR gates c. Six NOR gates will be used
b. given function must be implemented d. none of these
using OR and NAND gates
24. The simplest form of the Boolean expression X’Z + W’XY’ + W(X’Y + XY’) in SOP form is
a. XZ’ + X’Y + W’XY c. X’Z + XY’ + WX’Y
b. X’Z + XY’ + WXY’ d. none of these
25. The binary signal at the inputs and outputs of any gate has one of two values, except during ____
a. threshold c. transition
b. saturation d. steady-state
26. This is a diagram made up of squares, with each square representing one minterm of the function
that is to be minimized
a. K-Map c. Truth Table
b. Prime-Implicant Chart d. Flowchart
28. Two adjacent 1’s form a prime implicant, provided that they are not within a group of ______
a. two adjacent squares c. four adjacent squares
b. three adjacent squares d. none of these
29. The simplest expression (in sum-of-products form) for the function F(A,B,C,D,E) =
∑m (1,3,5,7,8,12,15,18,19,22,23,24,27,28,31) is
a. F = Z c. F = W’Z
b. F = Z’ d. none of these
a. w’x’y’ c. wx’z
b. w’xz d. wxz’
a. XY’ c. X’Z
b. WY d. none of these
For questions 34 to 40, refer to the behavior of the synchronous sequential circuit below. Assume that the
states are identified as the combination ABC.
X
Y
D Q T Q J Q
A B C
Q Q K Q
CP
34. What is the next state for an input of 0 if the current state is 000?
a. 010 c. 111
b. 011 d. none of these
35. What is the next state for an input of 1 if the current state is 001?
a. 100 c. 010
b. 101 d. none of these
36. What is the next state for an input of 0 if the current state is 010?
a. 000 c. 100
b. 001 d. none of these
37. What is the next state for an input of 1 if the current state is 011?
a. 100 c. 110
b. 101 d. none of these
38. What is the next state for an input of 0 if the current state is 100?
a. 100 c. 111
b. 101 d. none of these
39. What is the next state for an input of 1 if the current state is 101?
a. 000 c. 110
b. 001 d. none of these
For questions 41 to 44, refer to the given J-K flip-flop excitation table below.
45. This element of the ASM chart is connected by directed edges indicating the sequential precedence
and evolution of the states as the machine operates.
46. This element of the ASM chart describes the effect of an input on the control subsystem.
a. decision box c. conditional box
b. state box d. none of these
47. This is a device in which the output depends in some systematic way on variables
other than the immediate inputs to the device.
a. combinational circuit c. state machine
b. programmable logic device d. programmable logic array
49. The master-slave is a pulse-triggered flip-flop and is indicated as such with a right angle symbol
called a ______________
a. dynamic input indicator c. postponed output indicator
b. static pulse indicator d. none of these
50. The control sequence and datapath tasks of a digital system are specified by means of a ___.
a. software algorithm c. program control unit
b. hardware algorithm d. arithmetic & logic unit