STA

Why is timing analysis important when designing a chip?

STA Introduction

Timing is important because just designing the chip is not enough; we need to know how fast the chip is
going to run, how fast the chip is going to interact with the other chips, how fast the input reaches the
output etc…Timing Analysis is a method of verifying the timing performance of a design by checking for
all possible timing violations in all possible paths.

 Static timing analysis is a method of validating the timing performance of a

design by checking all possible paths for timing violations.
 Static Timing Analysis (STA) is a method of computing the expected timing of a
digital circuit without requiring simulation
 STA is an exhaustive method of analyzing, debugging and validating the timing
performance of a design.

Majorly Tool used

Prime Time (From Synopsys)

Input Required for STA

1. Netlist
2. .lib for standard cells
3. .lib for hard macros
4. SPEF/SDF files
5. Constraints files (.sdc)
6. Routing delay form the layout
Advanced Timing Analysis

Analysis Modes
Data to Data Checks
Case Analysis
Multiple Clocks per Register
Minimum Pulse Width Checks
Derived Clocks
Clock Gating Checks
Netlist Editing
Report_clock_timing
Clock Reconvergence Pessimism
Worst-Arrival Slew Propagation
Debugging Delay Calculation

PrimeTime Timing Models Support

PrimeTime offers the following timing models to address STA needs for IP, large hierarchical designs,
and custom design:

1. Quick Timing Model (QTM)

 2. Extracted Timing Model (ETM)
3. Interface Logic Model (ILM)
4. Stamp Model

Input To STA Tools

Majorly Tool used

Prime Time (From Synopsys)

Input Required for STA

1. Netlist

2. .lib for standard cells

3. .lib for hard macros

4. SPEF/SDF files

5. Constraints files (.sdc)

Setup Time
 Setup time is the minimum amount of time the data signal should be held steady
before the clock event so that the data are reliably sampled by the clock. This applies to
synchronous circuits such as the flip-flop.
 In short I can say that the amount of time the Synchronous input (D) must be
stable before the active edge of the Clock.
 The Time when input data is available and stable before the clock pulse is applied is
called Setup time.

How To fix Setup time Violation

What is Setup time?

The setup time is the interval before the clock where the data must be held stable.
Setup Violation can be fixed by
1. reduce the amount of delay in data path, this can be done by reducing the necessary buffers
2.VT swapping, means you swap HVT cell with SVT or LVT cells
3. upsizing the cells can also prevent the setup violation
4. Use of two inverters in place of buffer
5. readjusting the position of cells

Hold Time
Hold time:
 Hold time is the minimum amount of time the data signal should be held steady after the clock
event so that the data are reliably sampled. This applies to synchronous circuits such as the flip-flop.
 Or in short I can say that the amount of time the synchronous input (D) must be stable after the
active edge of clock.
 The Time after clock pulse where data input is held stable is called hold time.

How To Fix Hold Time Violations

What is Hold time?

The hold time is the interval after the clock where the data must be held stable. Hold time can be
negative, which means the data can change slightly before the clock edge and still be properly captured.
Most of the current day flip-flops has zero or negative hold time.

Way of fixing the hold time violation is just opposite of setup time violation.Below are few methods to fix
hold time violation.

1. introducing the delay in data path, you can do this by adding the buffers in data path
2. Downsizing the cells
3. VT swapping, you can swap the the LVT buffers to SVT or HVT buffers