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JEDEC TO-220AB JEDEC TO-263A
SOURCE
DRAIN
GATE DRAIN
(FLANGE)
GATE
DRAIN (FLANGE) SOURCE
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to TJ = 125oC.
Thermal Resistance Junction to Ambient RθJA Typical Socket Mount - - 62.5 oC/W
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = -12A, VGS = 0V, - - -1.5 V
(Figure 13)
Reverse Recovery Time trr TJ = 150oC, ISD = -12A, dISD/dt = 100A/µs - 300 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = -12A, dISD/dt = 100A/µs - 1.8 - µC
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, starting TJ = 25oC, L = 5.2mH, RG = 25Ω, peak IAS = 12A. See Figures 15, 16.
1.2 -12.0
POWER DISSIPATION MULTIPLIER
1.0
-9.6
ID, DRAIN CURRENT (A)
0.8
-7.2
0.6
-4.8
0.4
-2.4
0.2
0 0
0 25 50 75 100 125 150 25 50 75 100 125 150
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE
1
THERMAL IMPEDANCE
ZθJC, NORMALIZED
0.5
0.2
0.1 PDM
0.1
0.05
0.02
0.01 t1
SINGLE PULSE t2 t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + RθJA +TC
0.01
10-5 10-4 10-3 10-2 10-1 1 10
t 1, RECTANGULAR PULSE DURATION (s)
-100 -20
VGS = -9V
VGS = -10V
10µs -16
-10 -20
VDS ≥ I D(ON) x rDS(ON)
VGS = -9V
VGS = -6V
VGS = -10V
-55oC
-6 -12
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-4 -8 125oC
VGS = -5V
-2 -4
VGS = -4V
0 0
0 -2 -4 -6 -8 -10 0 -2 -4 -6 -8 -10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)
1.0
2µs PULSE TEST 2.2
VGS = -10V, ID = -6.5A
PULSE DURATION = 80µs
rDS(ON) DRAIN TO SOURCE
ON RESISTANCE
0.6
1.4
0.4
VGS = - 20V 1.0
0.2
0.6
0
0 -10 -20 -30 -40 -50 0.2
-40 0 40 80 120
ID, DRAIN CURRENT (A)
TJ , JUNCTION TEMPERATURE (oC)
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE
1.25 1000
ID = 250µA VGS = 0V, f = 1MHz
CISS = CGS + CGD
NORMALIZED DRAIN TO SOURCE
C, CAPACITANCE (pF)
1.05 600
CISS
0.75 0
-40 0 40 80 120 160 0 -10 -20 -30 -40 -50
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE
5 -100
TJ = -55oC PULSE DURATION = 80µs
TJ = 25oC DUTY CYCLE = 0.5% MAX
gfs, TRANSCONDUCTANCE (S)
4 TJ = 125oC
ISD, DRAIN CURRENT (A)
TJ = 150oC
-10
3
2
TJ = 25oC
-1.0
1
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0 -0.1
0 -4 -8 -12 -16 -20 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8
ID , DRAIN CURRENT (A) VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
0
I D = -12A
VGS, GATE TO SOURCE (V)
-5
- 10
VDS = -20V
VDS = -50V VDS = -80V
- 15
0 8 16 24 42 40
Qg(TOT) , TOTAL GATE CHARGE (nC)
VDS
tAV
L 0
VARY tP TO OBTAIN
REQUIRED PEAK IAS RG
-
VDD
+
0V DUT VDD
tP IAS
VGS
VDS
IAS tP
0.01Ω
BVDSS
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON tOFF
td(ON) td(OFF)
tr tf
0
RL 10% 10%
DUT - VDS
VDD 90% 90%
RG
VGS + VGS
0
10%
50% 50%
PULSE WIDTH
90%
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
-VDS
CURRENT (ISOLATED
REGULATOR SUPPLY) 0
VDS
DUT
12V
0.2µF 50kΩ
BATTERY
0.3µF
Qgs VGS
Qgd
D
Qg(TOT)
G DUT
VDD
0
IG(REF) S 0
+VDS
IG CURRENT ID CURRENT
SAMPLING SAMPLING IG(REF)
RESISTOR RESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. H4
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