On Signal-Gating Schemes for Low-Power Adders
Zhijun Huang and Milo5 D. Ercegovac
Computer Science Department
University of California Los Angeles
Los Angeles, CA 90095
{ zj huang, milos}@cs.ucla.edu
Abstract
Signal gating schemes for low-power adder design
are studied in this paper. Signal gating dynamically de-
activates portions of an adder according to the actual
precision of two operands. Based on program analy-
sis, signal gating is developed for two different adders:
symmetric adders and asymmetric adders. The effect
of signal gating is investigated by incorporating several
gating schemes into a RISC pipeline. Experimental re-
sults indicate more power saving compared to previous
work.
1 Introduction
Adders are fundamental arithmetic units in digi-
tal systems. As power consumption is becoming an
important concern, low-power adders have been stud-
ied extensively on the circuit and logic levels. In [1]-
[4], power estimation and comparison of various adder
structures are presented. In [5]-[8], power optimiza-
tion techniques are proposed to reduce switching ac-
tivity. In these studies, adders have been treated as
isolated units with little consideration of application
data characteristics. Because power dissipation is di-
rectly related to data switching patterns, the isolated
adder optimization would lead to limited power sav-
ing. Program analysis has revealed that there are a
large number of short-precision additions in most ap-
plications [9]-[12]. To take advantage of short-precision
data, signal ating can be applied to deactivate por-
tions of an a%der to match run-time data precision.
Signal gating is a popular power reduction technique
that has been used widely at all levels of abstraction.
On the architecture level, an idle functional unit and
its input/output registers can be powered down by dis-
\
abling their clock signals 13][14]. For a busy func-
tional unit, some portion(s can still be gated accord-
ing to operand precisions as first proposed in [lo]. The
notion of operand gating is further generalized to all
stages of the microprocessor pipeline in [12]. In the
adaptive power-aware system proposed in [15], an en-
semble of functional units with different fixed widths
are provided and only one of them is adaptively en-
abled according to input data precision. A major limi-
tation of these architecture-level signal gating schemes
0-7803-7147-x/01/$10.0002001IEEE 867
is the lack of arithmetic details and reliable power es-
timation, which would affect the optimal points and
area/power/delay tradeoffs. For example, the power
distribution in adders with short-precision data is gen-
erally not uniform. [16] attempted to consider adder
details with signal gating logic and concluded that lit-
tle power saving could be achieved because of the over-
head. This conclusion is true if the adder design is
considered separately. However, the overhead can be
reduced or amortized if the related units are also mod-
ified t o accept short-precision data.
In this paper, we develop signal gating schemes with
arithmetic details for different precision patterns of ad-
dition and appl the techniques into DLX microproces-
sor pipeline [l'i'f The rest of this paper is organized as
follows. Section 2 gives basic definitions. Section 3
presents program analysis results as the motivation of
this work. Section 4 discusses signal gating schemes
for adders with symmetric-precision operands. Section
5 studies signal gating schemes for special adders with
asymmetric-precision operands. Section 6 discusses ex-
perimental results including the power optimization of
the DLX pipeline. The last section concludes this work.
2 Definitions
A n-bit two's-complement number can be parti-
tioned into two parts: sign extension bits (leading ze-
ros or ones), and significand bits including the sign bit.
The sign extension part is denoted as E and the sig-
nificand part as D.
1"' and ID1 denote the lengths of
+
E and D , respective y. Therefore, n = IEl 101and
1 5 ]Dl 5 n . 1 1 is the actual precision of the num-
0
ber. For two's-complement addition with operands X
and Y , the operation precision is defined as IDopl =
m u z ( ~ ~I+l).x ~ , q{JDopJ= i}] is the probability of
operations with precision IDopl = i. We also define the
following probability variables for each operand:
Pi D : the probability of bit i being in part D;
Pi[E]:the probability of bit i being in part E ;
SPi: the static probability of bit i being logic '1';
TRi: the rate of bit i toggling per cycle.
Pi(D) and Pi(E) reflect data spatial correlation. If two
neighbor bits have the similar P ( E ) , they are highly
correlated. S P and T R reflect the temporal correla-
tion. The lower the values, the higher the data are
temporally correlated.
3 Program Analysis
With the execution tracing tool Shade [18], we have
analyzed run-time features of operations and operands
in 32-bit Mediabench programs [19]. We have the fol-
lowing observations. First, about 70% of the total ex-
ecuted instructions involve addition steps. This is be-
cause additions/subtractions, load/store memory ad-
dress calculation and branches all require addition op-
erations. Moreover, most instruction executions have
a PC incrementing step. In program djpeg, for ex-
ample, the distribution of instruction types is: addi-
tions/subtractions are 36.08%, multldiv 3.26%, shift
and logic 21.02%' load/store 30.49%, branches 7.44%.
Second, most arithmetic operations have precisions
much smaller than the datapath hardware width. In
djpeg, 86% of additionlsubtraction has precision of 20
bits or less, 57% has precision of 13 bits or less, as
shown in Fig. 1. Third, the precision difference be-
tween two operands is significant. In djpeg, the average
precision difference between additionlsubtraction's two
operands is 7 bits while the difference between the two
operands in data memory address calculation is 13 bits.
Fourth, the SP of each bit is less than 0.5 in most cases,
and the T R is often not equal to 2 x S P x (1 - S P )
because of the correlation. These observations have
motivated this work.
Precision Distribution of AdditionlSubtractionin djpeg
100 8 ;.a.
/flfl
4 8 12 16 20 24
Precision
Figure 1: Precision distribution of AddISub.
4 Signal Gating for Symmetric Adders
We define symmetric adders as n-bit adders with
both operands have the similar data range, which is
the general case. In our design, input data of an adder
are stored in two registers. Upon each clock rising edge,
new data are loaded into the registers and the addition
works on the loaded data. Signal gating is applied to
both input registers and combinational addition logic.
In many cases, signal gating with one gating boundary
cannot fully utilize dynamic data precisions. Adders
with multiple gating boundaries may be designed for
more energy saving. Here we only discuss signal gating
with one boundary.
4.1 Signal Gating with One Boundary
Suppose the upper G-bit portion of the adder is
identified as the candidate to be gated. The general
structure of a signal-gated adder is illustrated in Fig. 2.
IDL is identity detection logic and GCTL is gating con-
trol logic as shown in 3. The behavior of si nal gating
is as follows. The first step is to detect ]Ex7and IEyl,
the sign-extension widths of X and Y . Two leading
bits from the lower ( N - G) part are involved in test-
ing. This is necessary because we need the result of
lower-part computation to be in a correct form with-
out overflow. The OR signal of upper (G 2) bits in +
each operand indicate if upper G bits can be viewed as
extension bits of '0'. The NAND signal of upper ( G + 2 )
bits indicate if upper G bits can be viewed as exten-
sion bits of '1'. To protect the clock signal from glitches
and ensure correct timing, g is latched to be g l before
controlling the clock and is registered to be gll before
controlling the combinational circuit. If lExl > G and
lEyl > G, the G-bit portion is gated by disabling the
clock of input registers and blocking the carry signal.
The adder works as a short-precision adder and the re-
sult is then restored to the full width. Otherwise, the
adder works as a normal full-width adder.
X G bits Y: G bits X (N-G) bits Y: (N-G)
bits
-
SUM:G bits S U M (N-G)
bits
Figure 2 : Symmetric adder with signal gating.
28 32
.:i.-
w biu
a bich
gclk
c
a, Lars lkg
811
(a) IDL (b) GCTL
Figure 3: Identical Detection and Gating Control Logic.
4.2 Overhead Analysis
To justify the signal gating technique, the energy
overhead should not exceed the power reductions.
868
Moreover, the area and delay overhead need to be con-
sidered. We assume tree structures of 2-input gates are
used t o implement IDL. To implement w-input NAND,
a tree structure will have log2 w levels and (20-1) gates.
For the structure in Fig. 2, we estimate the area over-
head as
Aoh = (4G + 8) 1 Anand2 4- Q A ~ a t c h4-G . Amur21
The energy overhead, Job, depends on Aoh and the G-
bit data switching activities. The delay increase of the
IDL stage is
Tloh = (log,(G + 2) -k 2)tnand2 + tlatch
and the delay increase of the addition stage is
T20h = tlatch tmuz.21
To find the optimal gating positions, power distribu-
tion in the baseline registers and adders is needed. This
can be achieved by various power estimation tools. For
a baseline adderlsubtractor with test data from djpeg,
the power distribution is given in Fig. 4. Denote the
energy consumption of the i-th cell as Ji. The Rower
consumption of the addition unit is Jadd = Ji.
When the upper g bits are gated (ng = n - g ) , the
power consumption is reduced to
ng
Jgadd = Ji + (1 - P{ lDopl < n g } )
i=l i=ng+l
and the power saving in the addition unit is
n In this case, the G portion must be active in order to
A J a J d = P{ lDopl< ng} Ji
i=ng+l
in which P{ IDopJ < ng} is the probability of operation
precisions being less than ng, which can be obtained
from Fig. 1. Similarly, we can deduce A J r e g x and
A Jregy. The overall power saving will be
AJtotal = A J r e g x + A J r e g y + A J a d d - Joh
5 Signal Gating for Asymmetric
Adders
We define asymmetric adders as n-bit adders with
two operands having quite different data ranges. The
range difference can exist explicitly or implicitly. Two
types of explicit asymmetric additions are considered
here: PC incrementing and addition with one operand
being short-width immediates. In implicit asymmet-
ric addition, both operands have full hardware widths
while the precisions are quite different at run time.
In processor pipelines, PC incrementing is an ex-
plicit asymmetric addition. Assuming the PC has word
resolution, one operand of the addition is always +1
while the other operand is in full 30-bit precision. The
Power Distribution in 32-bit AddedSubtractor
5 -
4
4 8 12 16
Bit
20 24 28 32
Figure 4: Power distribution in adderlsubtractor.
incrementing is complicated as the branch target ad-
dress would be loaded into PC when a branch is taken.
In [12], the PC incrementing is performed byte-serially
to reduce the activity. In the worst case, the PC incre-
menting has to be done in four cycles. Here we look at
how to apply signal gating in low power PC increment-
ing design with little performance loss. A diagram of
the design is given in Fig. 5. The upper G portion is
still the gating candidate. When branch is 1 indicating
the branch is taken, gating logic is inactive and branch
fl target address BPC is loaded into PC in the next cy-
Ji cle. When branch is 0 and the lower N G bits of are
not all l’s, the upper G portion are gated in the next
cycle. If branch is 0 and the N G bits are all l’s, the
NG part in the next cycle will compute 11 . . . 11 + 1,
which would generate a carry into the upper G portion.
accept the carry.
Figure 5: PC incrementor with signal gating.
Addition with one immediate operand is fre-
quently used in addition/subtraction instructions and
load/store memory address calculations. One operand
has the full precision range of n . The other operand
has small range of w (w < n ) . To apply signal gating,
the addition can be partitioned into two portions: the
lower w bits and the upper ( n - w) bits. the upper por-
tion is then simplified as an incrementor/decrementor,
as shown in Fig. 6. if half adder is used to imple-
ment incrementor/decrementor, the boolean expres-
sion is si = ci@xi and ci+l = ci(xi$dir). The direction
control dir is S’Cd and dir = 1 indicates decrementing.
The carry-in of the upper portion is modified to be
s cd.
869
 X: s d d d d d d d d did d d d d d
y: s s s s s s s s s s j d d d d d d
s Cdl
y
Y: Sign Portion
cd
0 0 1 0 0 0 0 0 0 0
( 1 1 1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
Figure 6: Simplification in addition with immediates.
Because the logic of the upper portion is reduced,
power consumption goes down accordingly even if there
is no signal gating. If we want to gate the upper por-
tion when s @ cd = 0, output multiplexers are neces-
sary. More importantly, there is a timing problem to
be solved. If the upper portion with input registers
is gated when waiting for the carry signal cd, the new
X input may be lost when the upper portion starts
computing. gating-controlled Latches can be inserted
to hold new X at the register’s outputs. As the over-
head is a latch and a multiplexer each bit, the power
saving is minimal, if any. An alternative approach is
to put the lower portion and the upper portion into
two pipeline stages if possible. The carry signal of the
lower-portion stage is used to gate the upper-portion
stage.
In implicit asymmetric addition, a partition similar
to Fig. 6 can still be made. However, the upper por-
tion of Y is not always the sign portion. It is possible
that some or all bits in the upper portion is significant
bits. We estimate that the signal gating design for im-
plicit asymmetric addition would be complicated and
the power saving is not much.
6 Experiments
6.1 Adder with Signal Gating
We first studied the power saving effect of the
general symmetric adders with signal gating. These
schemes have been designed in gate-level VHDL. The
Synopsys design environment is used as a common plat-
form to compare different schemes. Test data are gath-
ered by tracing the execution of addition/subtraction
in djpeg. The breakdown of power consumption in
different schemes is shown in Table 1. The baseline
scheme is a 32-bit two’s-complement carry propagate
adder/subtractor. G11 is the scheme with signal gat-
ing on upper 11 bits. G18 is the scheme with gating
on upper 18 bits. 2G is the scheme with dual gating
on upper 11 and 18 bits. The power consumption is
divided into two parts: the useful power consumption,
Pus,and the overhead power, Po,,.Pus, includes Perk,
Pdin,Preg,and Padd. Pclk and Pdin are the power con-
sumptions of clock and data input ports. Preg and Padd
are the power consumptions of input registers and the
adder/subtractor core.
Table 1: Power comparison ( n W / M H z )
II p
Schemes I baseline I G11 I
din
I-.. ,I
i195.7 i140.7
30.6 I 46.2 I
i
G18 I 2G 1
99.2 i 109.2
58.9 I 57.6
I
0 0 0 I F PI)” 120.8 I 90.51 I 81.1 I 76.0 1
0 0 01
0 -1
0 I
As we have expected, the power is reduced in the
following circuit blocks: the clock port, input register ,
and the addition core. Considering only the Pus,, the
power reduction is encouraging: G11 reduces 19%, G18
27% and 2G 29%. For the overall power consumption,
however, only G11 reduces the power by 6.2% while
the other two schemes consumes even more power. To
justify the use of signal gating in adders, the power
overhead must be reduced or amortized. If we consider
adders in a whole design, it is possible to reduce the
overhead by amortizing the precision detection cost or
keeping the short-precision data for subsequent com-
putations. For example, if signal gating is applied in a
multiplier, there is no need to provide precision detec-
tion logic for the final CPA. In the following, we study
how to keep short-precision data in the DLX processor
pipeline.
6.2 DLX Pipeline with Signal Gating
The DLX pipeline considered here is an improved
version of the basic pipeline with reduced stalls from
branch hazards [17]. There are five stages: instruction
fetch (IF), instruction decode (ID), execute (EX), data
memory access (MEM) and write back (WB). IF, ID
and EX have addition operations. The adder in stage
IF is the P C incrementor. The adder in stage ID cal-
culates the branch target address (BTA), which is the
addition of PC and an immediate. The ALU imple-
ments arithmetic and logic operations, as well as data
memory address calculation.
Previous work in [14] studied clock gating on the
whole units and the related pipeline registers, which
we call whole-unit ating. For example, the EX stage
will be idle at 9.176 of the total execution time and
MEM will be idle at 69.5% of the total time when run-
ning djpeg, which are good candidates for whole-unit
gating. In addition t o whole-unit gating, we extend
the signal gating schemes described in this paper to
the whole pipeline, which is called portion-unit gating.
Instead of detecting precision at two inputs of ALU,
the precision is detected at the outputs of ALU and
data memory. The precision information is kept in the
pipeline using some tag bits. In our experiment, we
use dual signal gating on upper 11 and 18 bits of EX,
MEM, WB units as well as their input registers. PC+1
and BTA are asymmetric adders described in Section 5.
There is no gating on IF and ID units because they are
always busy and instructions are not data to be com-
puted. Instruction compression techniques can be used
870
to reduce the number of bits to be processed, which is
out of our scope here. Based on the simulation data
in Table 1, each unit with dual signal gating is as-
sumed to consume 33% less power on average when
gated. Table 2 lists the the power reduction percent-
age in pipeline blocks of two gating schemes compared
to the baseline DLX pipeline with no gating.
Schemes PC+1 BTA EX MEM WB I REG
W 0 0 9.17 69.5 9.17 I 26.33
W+P 44.53 25.00 39.42 79.65 39.42 1 37.77
Only those units with power changing are listed in
the table. W is the whole-unit gating scheme. W+P
is the combining of whole-unit gating and portion-unit
gating. It can be seen that W+P achieve another 10-
45% reduction compared t o W. With respect to the
gating overhead, there is little cost in the W scheme
because there is no precision detection and the gating
control signals are also pipeline control signals. The
W+P scheme has precision detection in both ALU and
MEM outputs. The total overhead may offset the ben-
efit in EX stage, judged from Table 1. Considering
that ALU and MEM are gated when idle, the overhead
would be much less.
7 Conclusions
Signal gating schemes for low-power adder design
have been studied in this paper. The program anal-
ysis indicates that there is a large number of short-
precision additions and the precision difference between
two operands is large. Based on the precision features,
signal gating is developed for two types of adders: sym-
metric adders and asymmetric adders. The effect of sig-
nal gating is studied by treating a signal-gated adder
as a separate unit as well as incorporating signal gat-
ing into a RISC pipeline. Experimental results indicate
10-45% power saving in the pipeline units compared to
previous work.
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