8

Describing Combinational
and Sequential Logic using
Verilog HDL

8.1 THE DATA-FLOW STYLE OF DESCRIPTION:

REVIEW OF THE CONTINUOUS ASSIGNMENT

We have already come across numerous examples in the previous chapters of Verilog designs
written in the so-called data-?ow style. This style of description makes use of the parallel
statement known as a continuous assignment. Predominantly used to describe combinational
logic, the ?ow of execution of continuous assignment statements is dictated by events on signals
(usually wires) appearing within the expressions on the left- and right-hand sides of the
continuous assignments. Such statements are identi?ed by the keyword assign. The keyword
is followed by one or more assignments terminated by a semicolon.
All of the following examples describe combinational logic, this being the most common use
of the continuous assignment statement:

//some continuous assignment statements

assign A ¬ q [0], B ¬ q [1], C ¬ q [2];

assign out ¬ ($s1 & $s0 & i0) j

($s1 & s0 & i1) j
(s1 & $s0 & i2) j
(s1 & s0 & i3);

assign #15 {c_out, sum} ¬ a _ b _ c_in;

The continuous assignment statement forms a static binding between the wire being assigned
on the left-hand side of the ¬ operator and the expression on the right-hand side of the assignment
operator. This means that the assignment is continuously active and ready to respond to any

FSM-based Digital Design using Verilog HDL Peter Minns and Ian Elliott
# 2008 John Wiley & Sons, Ltd. ISBN: 978-0-470-06070-4
198Describi
ng
2 assign q = en ? data : q;
Combination
al and 3 endmodule
Sequential
Logic using
Verilog
HDL
1
1 data
q
modul MUX
e
0
latch
(outp
ut q,
input
data,
en); en
Describing a level-sensitive latch using a continuous assignment.Figure 8.1

changes to variables appearing in the right-hand side expression (the inputs). Such changes result
in the evaluation of the expression and updating of the target wire (output). In this manner, a
continuous assignment is almost exclusively used to describe combinatorial logic.
As mentioned previously, a Verilog module may contain any number of continuous assign-
ment statements; they can be inserted anywhere between the module header and internal wire/
reg declarations and the endmodule keyword.
The expression appearing on the right-hand side of the assignment operator may contain
both reg- and wire-type variables and make use of any of the Verilog operators mentioned in
Chapter 7.
The so-called target of the assignment (left-hand side) must be a wire, since it is continuously
driven. Both single-bit and multi-bit wires may be the targets of continuous assignment statements.
It is possible, although not common practice, to use the continuous assignment statement to
describe sequential logic, in the form of a level-sensitive latch.
The conditional operator (? is used on the right-hand side of the assignment on line 2 of the:)
listing shown in Figure 8.1. When en is true (logic 1) the output q is assigned the value of the
input data continuously. When en goes to logic 0, the output q is assigned itself, i.e. feedback
maintains the value of q, as shown in the logic diagram below the Verilog listing.
It should be noted that the use of a continuous assignment to create a level-sensitive latch, as
shown in Figure 8.1, is relatively uncommon. Most logic synthesis software tools will issue a
warning message on encountering such a construct.

8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION:

THE SEQUENTIAL BLOCK

The Verilog HDL sequential block de?nes a region within the hardware description conta-
ining sequential statements; these statements execute in the order they are written, in just the