Flexray - Physical Layer Conformance Test Specification V1.0

FlexRay Physical Layer Conformance Test Specification
FlexRay Physical Layer

Conformance Test Specification
Version 1.0
Registered copy for mazkarateaskasua@ikerlan.es
Version 1.0 December-2005 Page 1 of 816

Disclaimer
Disclaimer
This specification as released by the FlexRay Consortium is intended for the purpose
of information only.
The use of material contained in this specification requires membership within the
FlexRay Consortium or an agreement with the FlexRay Consortium.
Following the completion of the development of the FlexRay Communications
System Specifications commercial exploitation licenses will be made available to
End Users by way of an End User’s License Agreement. Such licenses shall be
contingent upon End Users granting reciprocal licenses to all Core Partners and non-
assertions in favor of all Premium Associate Members, Associate Members and
Development Members.

All details and mechanisms concerning the bus guardian concept are defined in the
FlexRay Bus Guardian Specification.
The FlexRay Communications System is currently specified for a baud rate of
10Mbit/s. It may be extended to additional baud rates.
No part of this publication may be reproduced or utilized in any form or by any
means, electronic or mechanical, including photocopying and microfilm, without
permission in writing from the publisher.
All rights reserved. The word FlexRay and the FlexRay logo are registered
trademarks.
Copyright © 2004 - 2005 FlexRay Consortium. All rights reserved.
The Core Partners of the FlexRay Consortium are BMW AG, DaimlerChrysler AG,
General Motors Corporation, Freescale GmbH, Philips GmbH, Robert Bosch GmbH,
and Volkswagen AG.

Table of Contents
Table of Contents
1 Introduction .......................................................................................................... 12
1.1 Scope........................................................................................................... 12
1.2 References................................................................................................... 12
1.3 Terms and Definitions.................................................................................. 12
1.4 Acronyms and Abbreviations....................................................................... 12
1.5 Notational Conventions................................................................................ 14
2 Test Environment................................................................................................. 15

2.1 Test Case Architecture ................................................................................ 15
2.2 Test Method ................................................................................................. 15
2.2.1 Upper Tester......................................................................................... 16
2.2.2 Lower Tester......................................................................................... 17
2.2.3 Supervisor ............................................................................................ 18
2.3 Test Environment......................................................................................... 18
2.4 Test Topology .............................................................................................. 18
2.4.1 Cable overview of the test topology ..................................................... 23
2.4.2 Shield.................................................................................................... 26
2.4.3 ESD Protection ..................................................................................... 26
2.4.4 Termination........................................................................................... 27
2.4.5 Common Mode Chokes........................................................................ 29
2.4.6 Active Star ............................................................................................ 30
2.4.7 Passive Star ......................................................................................... 30
2.4.8 Passive Bus .......................................................................................... 32
2.4.9 Cables................................................................................................... 33
2.4.10 Connectors ........................................................................................... 35
2.5 Test Equipment............................................................................................ 35
2.5.1 General ................................................................................................. 35
2.5.2 Power Supply VBAT ............................................................................... 36
2.5.3 Power Supply VCC................................................................................. 36
2.5.4 Power Supply VIO ................................................................................. 37

Table of Contents
2.5.5 Ground Shift Generator ........................................................................ 38

2.5.6 Low Battery Generator ......................................................................... 38
2.5.7 Signal Generator .................................................................................. 39
2.5.8 Analog Signal Measurement ................................................................ 40
2.5.9 Digital Signal Measurement ................................................................. 40
2.5.10 Data Acquisition Unit ............................................................................ 41
2.5.11 Broadband Amplifier ............................................................................. 41
2.5.12 Arbitrary Function Generator................................................................ 42
3 Stress Conditions................................................................................................. 43

3.1 Ground Shift................................................................................................. 43
3.2 Low Battery Voltage inside operational Range ........................................... 44
3.3 Undervoltage................................................................................................ 45
3.4 Dynamic Low Battery Voltage ..................................................................... 45
3.5 Failures ........................................................................................................ 47
3.6 Babbling Idiot ............................................................................................... 51
3.7 Dynamic Ground Shift.................................................................................. 51
3.8 EMC ............................................................................................................. 52
3.9 ESD.............................................................................................................. 52
3.10 Temperature Tests ...................................................................................... 52
4 Parameter List...................................................................................................... 53
4.1 Static Test Cases......................................................................................... 54
4.2 Communication............................................................................................ 54
4.2.1 Delay..................................................................................................... 54
4.2.2 Signal Shape ........................................................................................ 55
4.2.3 Threshold.............................................................................................. 56
4.2.4 Timing ................................................................................................... 57
4.2.5 Truncation............................................................................................. 58
4.3 Mode ............................................................................................................ 59
4.3.1 Active Star ............................................................................................ 61
4.3.2 Bus Driver ............................................................................................. 61

Table of Contents
4.4 Power Supply............................................................................................... 62

4.5 Environment................................................................................................. 63
4.6 Dynamic Low Battery Voltage ..................................................................... 63
4.7 Ground Shift................................................................................................. 63
4.8 Failure .......................................................................................................... 63
4.8.1 Babbling Idiot........................................................................................ 64
4.8.2 Loss ...................................................................................................... 64
4.8.3 Short Circuit.......................................................................................... 65
4.8.4 Termination........................................................................................... 65

4.9 Functional Class .......................................................................................... 66
5 Test Cases for Bus Drivers within a homogeneous Topology ............................ 67
5.1 Configuration................................................................................................ 67
5.1.1 Topology ............................................................................................... 67
5.1.2 Test Planes........................................................................................... 67
5.1.3 Test Patterns ........................................................................................ 71
5.1.4 Observation Windows........................................................................... 75
5.1.5 Power Modes of the Bus Driver............................................................ 78
5.1.6 Power Supplies..................................................................................... 79
5.1.7 Stress.................................................................................................... 79
5.1.8 Failures ................................................................................................. 79
5.1.9 Optional Features ................................................................................. 79
5.1.10 Definition of Communication and Control............................................. 80
5.1.11 Standard Preamble............................................................................... 88
5.1.12 Standby Preamble ................................................................................ 88
5.1.13 Sleep Preamble .................................................................................... 89
5.1.14 ReceiveOnly Preamble......................................................................... 90
5.1.15 Standard Postamble ............................................................................. 90
5.1.16 Receiver Masks .................................................................................... 90
5.1.17 Services ................................................................................................ 91
5.2 Static Test Cases......................................................................................... 97

Table of Contents
5.3 Test Cases.................................................................................................102

5.3.1 Communication.Delay.dBDTx01 ........................................................102
5.3.2 Communication.Delay.dBDTx10 ........................................................114
5.3.3 Communication.Delay.dTxAsym ........................................................126
5.3.4 Communication.Delay.dBDRx01........................................................132
5.3.5 Communication.Delay.dBDRx10........................................................144
5.3.6 Communication.Delay.dRxAsym........................................................156
5.3.7 Mode.Bus Driver.Low Power.Standby ...............................................162
5.3.8 Mode.Bus Driver.Normal ....................................................................261

5.3.9 Mode.Bus Driver.Low Power.Sleep ...................................................279
5.3.10 Mode.Bus Driver.ReceiveOnly ...........................................................333
5.3.11 Failure.Loss ........................................................................................345
5.3.12 Failure.Short Circuits ..........................................................................366
5.3.13 Power Supply.Undervoltage VBAT .......................................................368
5.3.14 Power Supply.Undervoltage VCC ........................................................376
5.3.15 Power Supply.Undervoltage VIO .........................................................384
5.3.16 Dynamic Low Battery Voltage ............................................................386
5.3.17 Communication.Timing.Masks ...........................................................402
5.3.18 Communication.Truncation ................................................................408
5.3.19 Failure.Short Circuit Bus Wires ..........................................................414
5.3.20 Communication.Shortened Bit Times.................................................422
5.3.21 Dynamic Ground Shift ........................................................................426
5.3.22 Eye Diagram.......................................................................................430
5.4 Test Procedures ........................................................................................432
5.4.1 Signal Shape, Timing, Delay ..............................................................432
5.4.2 Truncation, Masks ..............................................................................433
5.4.3 Mode...................................................................................................434
5.4.4 Failure.................................................................................................435
5.4.5 Undervoltage ......................................................................................436
5.4.6 Dynamic Low Battery..........................................................................437

Table of Contents
6 Test Cases for Active Stars within a homogeneous Topology..........................438

6.1 Configuration..............................................................................................438
6.1.1 Topology .............................................................................................438
6.1.2 Test Planes.........................................................................................438
6.1.3 Test Patterns ......................................................................................440
6.1.4 Observation Windows.........................................................................442
6.1.5 Power Modes of the AS......................................................................445
6.1.6 Power Supplies...................................................................................446
6.1.7 Stress..................................................................................................446

6.1.8 Failures ...............................................................................................446
6.1.9 Optional Features ...............................................................................446
6.1.10 Definition of Communication ..............................................................447
6.1.11 Standard Preamble.............................................................................449
6.1.12 Sleep Preamble ..................................................................................450
6.1.13 Standard Postamble ...........................................................................450
6.1.14 Services ..............................................................................................450
6.2 Static Test Cases.......................................................................................451
6.3 Test Cases.................................................................................................453
6.3.1 Communication.Delay.dStarDelay .....................................................453
6.3.2 Communication.Delay.dStarDelay0 ....................................................461
6.3.3 Communication.Delay.dStarAsym .....................................................469
6.3.4 Communication.Delay.dStarSetUpDelay ...........................................473
6.3.5 Communication.Truncation.dTruncationM,N ........................................481
6.3.6 Communication.Truncation.dStarTruncation......................................489
6.3.7 Mode.Active Star.Normal ...................................................................497
6.3.8 Mode.Active Star.Normal.GoToSleep ................................................509
6.3.9 Mode.Active Star.Normal.GoToSleep_Fail ........................................515
6.3.10 Mode.Active Star.Low Power.Sleep...................................................521
6.3.11 Mode.Active Star.Low Power.Sleep.Wake-up ...................................535
6.3.12 Mode.Active Star.Branch.Active.........................................................553

Table of Contents
6.3.13 Mode.Active Star.Branch.Idle.............................................................559

6.3.14 Mode.Active Star.Branch.FailSilent....................................................571
6.3.15 Failure.Loss ........................................................................................577
6.3.17 Failure.Short Circuit Bus Wires ..........................................................599
6.3.19 Eye Diagram.......................................................................................612
6.4 Test Procedures ........................................................................................614
6.4.1 Delay...................................................................................................614

6.4.2 Truncation...........................................................................................615
6.4.3 Mode...................................................................................................616
6.4.4 Failure.................................................................................................617
7 Test Cases for AS with CC Interface within a homogeneous Topology ...........619
7.1 Configuration..............................................................................................619
7.1.1 Topology .............................................................................................619
7.1.2 Test Planes.........................................................................................619
7.1.3 Test Patterns ......................................................................................621
7.1.4 Observation Windows.........................................................................621
7.1.6 Power Supplies...................................................................................621
7.1.7 Stress..................................................................................................621
7.1.8 Failures ...............................................................................................621
7.1.12 Sleep Preamble ..................................................................................626
7.1.13 Services ..............................................................................................626
7.3 Test Cases.................................................................................................629

Table of Contents
7.3.1 Communication.Delay.dStarTx01.......................................................629
7.3.2 Communication.Delay.dStarTx10.......................................................640
7.3.3 Communication.Delay.dTxAsym ........................................................651
7.3.4 Communication.Delay.dStarRx01 ......................................................657
7.3.5 Communication.Delay.dStarRx10 ......................................................669
7.3.6 Communication.Delay.dRxAsym........................................................681
7.3.7 Mode.Active Star.Normal ...................................................................687
7.3.8 Mode.Active Star.Normal.GoToSleep ................................................699
7.3.9 Mode.Active Star.Normal.GoToSleep_Fail ........................................705

7.3.10 Mode.Active Star.Low Power.Sleep...................................................711
7.3.11 Mode.Active Star.Low Power.Sleep.Wake-up ...................................725
7.3.12 Mode.Active Star.Branch.Idle.............................................................731
7.3.13 Mode.Active Star.Branch.Active.........................................................743
7.3.14 Mode.Active Star.Branch.FailSilent....................................................749
7.3.15 Failure.Loss ........................................................................................755
7.3.16 Failure.Short Circuits ..........................................................................765
7.3.18 Communication.Truncation ................................................................771
7.3.20 Communication.Shortened Bit Times.................................................785
7.4 Test Procedures ........................................................................................789
7.4.1 Signal Shape, Timing, Delay ..............................................................789
7.4.2 Failure.................................................................................................790
7.4.4 Mode...................................................................................................792
7.4.5 Truncation...........................................................................................793
8 Test Cases for Bus Drivers within a heterogeneous Topology .........................794
8.1 Configuration..............................................................................................794
8.1.1 Topology .............................................................................................794
8.1.2 Test Planes.........................................................................................795

Table of Contents
8.1.3 Test Patterns ......................................................................................796

8.1.4 Power Modes of the Bus Driver..........................................................796
8.1.5 Power Supplies...................................................................................796
8.1.6 Stress..................................................................................................796
8.1.7 Failures ...............................................................................................796
8.1.9 Definition of Communication and Control...........................................796
8.1.11 Standby Preamble ..............................................................................796

8.1.12 Sleep Preamble ..................................................................................796
8.1.13 ReceiveOnly Preamble.......................................................................796
8.1.15 Receiver Masks ..................................................................................796
8.1.16 Services ..............................................................................................797
8.3 Test Cases.................................................................................................798
8.4 Test Procedures ........................................................................................798
9 Test Cases for Active Stars within a heterogeneous Topology.........................799
9.1 Configuration..............................................................................................799
9.1.1 Topology .............................................................................................799
9.1.2 Test Planes.........................................................................................800
9.1.3 Test Patterns ......................................................................................801
9.1.5 Power Supplies...................................................................................801
9.1.6 Stress..................................................................................................801
9.1.7 Failures ...............................................................................................801
9.1.11 Sleep Preamble ..................................................................................801

Table of Contents

9.1.13 Services ..............................................................................................801
9.3 Test Cases.................................................................................................802
9.4 Test Procedures ........................................................................................802
10 Test Cases for AS with CC Interface within a heterogeneous Topology ..........803
10.1 Configuration..............................................................................................803
10.1.1 Topology .............................................................................................803
10.1.2 Test Planes.........................................................................................803

10.1.3 Test Patterns ......................................................................................803
10.1.4 Power Supplies...................................................................................803
10.1.5 Stress..................................................................................................803
10.3 Test Cases.................................................................................................803
10.4 Test Procedures ........................................................................................803
11 Appendix ............................................................................................................804
11.1 FlexRay Parameters ..................................................................................804
11.2 References to the EPL Specification .........................................................808
11.3 Index ..........................................................................................................809
11.4 List of Tables..............................................................................................810
11.5 List of Figures ............................................................................................811

Error! Style not defined.
1 Introduction
1.1 Scope
This specification describes the conformance test for the electrical physical layer for
FlexRay communication systems.
It is part of this document to define a test that considers the ISO9646 standard and
the FlexRay Communications System Electrical Physical Layer Specification V2.1
Rev A.
The purpose of this document is to provide a standardized way to verify whether
FlexRay bus driver and active star products are compliant to the FlexRay electrical

physical layer specification. The primary motivation is to ensure a level of
interoperability of FlexRay bus drivers and active stars from different sources in a
system environment.
This document shall provide all necessary technical information to ensure that test
results will be identical even on different test systems, provided that the particular
test suite and the test system are compliant to the content of this document.
1.2 References
[01-PL Spec] FlexRay Communications System Electrical Physical Layer
Specification V2.1 Rev A, December 2005
[02-BG Spec] FlexRay Communications System Bus Guardian Specification
V2.0, 30-June-2004
[03-ISO1] ISO 9646 Part 1, General Concepts
[04-ISO2] ISO 9646 Part 2, Abstract Test Suite Specification
[05-ISO4] ISO 9646 Part 4, Test Realization
[06-DIN1] ISO 7637 (comparable to DIN 40839)
[07-EMC Spec] FlexRay Physical Layer EMC Measurment Specification V2.1,
December 1005
[08-Prot Spec] FlexRay Communications System Protocol Specification V2.1
Rev A, December 2005
1.3 Terms and Definitions

See [08-Prot Spec].
1.4 Acronyms and Abbreviations

AS.................... Active Star

ASP ................. Abstract Service Primitive

BD.................... Bus Driver
BG ................... Bus Guardian
BGE ................. Bus Guardian Enable
BGT ................. Bus Guardian Tick
BM ................... Bus Minus
BP.................... Bus Plus
CC ................... Communication Controller
CE.................... Communication Element

CHI .................. Controller Host Interface
CMC ................ Common Mode Choke
CTRLx ............. Optional/product specific Mode Control Signals of the Bus Driver
DUT ................. Device Under Test
ECU ................. Electronic Control Unit
EMC................. Electromagnetic Compatibility
I/R .................... Interruption
INH1 ................ Inhibit 1 output signal of the bus driver / active star
INTN ................ Interrupt Not
IUT................... Implementation Under Test
LT .................... Lower Tester
PCO................. Point of Control and Observation
PDU ................. Protocol Data Unit
PL .................... Physical Layer
RxD.................. Receive data signal from the bus driver
RxEN ............... Receive data enable Not signal from the bus driver
S/C................... Short circuit
SCSN............... SPI chip select Not input
SOVS............... System Operation Variable Space, see chapter 4
SPI................... Serial Peripheral Interface
STBN ............... Standby Not signal
SUT ................. System under Test

SV.................... Supervisor
TCP ................. Test Coordination Procedure
TP .................... Test Plane
TSS.................. Transmission Start Sequence
TxD .................. Transmit data signal to the bus driver
TxEN................ Transmit data enable Not signal to the bus driver
UGS................... Ground Shift Voltage
UT.................... Upper Tester
VBAT.................. A supply voltage of the bus driver (Battery)

VCC ................... A supply voltage of the bus driver (+5V)
VECU ................. The supply (battery) voltage of the ECU
VIO .................... Supply voltage for the bus drivers digital I/O ports
WAKE .............. Local wake-up input signal of the bus driver
WU................... Wake-up
1.5 Notational Conventions

Notational conventions are listed in [01-PL Spec].

2 Test Environment
2.1 Test Case Architecture
Each test case is specified with the following parts, that must all described
unambiguous:
•Test Case Name
a name for this test case.
• Test Purpose
a description of the motivation for this test case.
• Configuration
the state of the test environment for this test case.

• Preamble (setup state)
the steps to do before the specified test case could be executed.
• Test execution
the description of the execution of this test case.
• Postamble
the steps to do after the specified test case in order to have a defined
state.
• Pass- / Fail Criteria
the criteria to judge the test result.
Every test case is independent from the other test cases.
Each test case is stressed by some specified stress conditions in order to check the
robustness of the IUT. These stress conditions are specified in detail in chapter 3 on
page 43 et seqq.
The test parameters are FlexRay variables or constants that are defined in [01-PL
Spec]. These test parameters are specified in detail in chapter 4 on page 53 et seqq.
Every test case starts at the beginning of the preamble and ends after the
postamble. There is no delay between the preamble and the test execution and
between the test execution and the postamble.
The pass/fail criteria is related only on the test execution.
Product specific items are not part of this conformance test specification.
2.2 Test Method

The FlexRay BD has several interfaces, that are supplied by specified power
supplies and stimuli and observed by external components (signal measurements).
The requirements for those generators and signal measurements are specified in
chapter 2.5 on page 35 et seqq.
The interfaces of the BD are separated in two parts:

•Analog interface
bus (service provider) and supply pins.
• Digital interface
the pins for connecting the BD with the FlexRay protocol components.
Each test case describes the used pins for supplying, stimulation and observation.
The used test method for the FlexRay PL regarding the [03-ISO1] is the local test
method, see also Figure 2-1.
The local test method contains a lower tester (LT) for the analog interface (bus) and
an upper tester (UT) for the digital interface. Both are part of the test system. The
coordination of the test cases is done by the test coordination procedure (TCP).
The whole test is controlled by the supervisor (SV) that is also part of the test

system. The SV controls the UP and LT with the TCP.
Test System
PCO
Upper Tester
ASPs
TCP SV
S Lower Tester
PDUs
U IUT
T PCO ASPs
Service Provider
Figure 2-1: Local Test Method
2.2.1 Upper Tester

The UT has to provide test data, control and observe the IUT at its upper interface.
The implementation has to keep in mind the possibility of two different host
interfaces of the IUT as specified in [01-PL Spec]. Figure 2-2 shows the mandatory
signals of the IUT that the conformance test considers:
Upper Tester Upper Tester

TxD TxEN RxD RxEN BGE INH1 ERRN STBN TxD TxEN RxD RxEN BGE INH1 INTN SPI

IUT (option A) IUT (option B)
Figure 2-2: Upper Tester

The tasks of the UT are:
• Provide test data streams
• Change the mode of the IUT
• Observe and acquire the error line
• Observe and acquire the received data stream
• Provide IUT functions to the supervisor
• Provide test system functionality to the IUT
2.2.2 Lower Tester

The LT has to provide data and observe the IUT at its lower interface – the supply
and bus interface of the IUT. Figure 2-3 shows an overview of this tester.
IUT
Supply GND BP BM
Lower Tester
Figure 2-3: Lower Tester

The tasks of the LT are:

• Generate and control bus failures

• Generate ground shift
• Control the supply voltages
• Provide IUT functions to the supervisor
• Provide test system functionality to the IUT
2.2.3 Supervisor
The SV has to control and observe the whole test system and communicates with
the IUT via the LT and UT.
The tasks of the SV are:
• Control the LT and UT

• Observe and acquire the LT and UT
• Control and observe optional measurement devices
• Execute and coordinate test procedures
• Create the test report
2.3 Test Environment

The following parameters are constants within the conformance test and used in the
standard environment:
• Temperature: ambient
• Moisture: ambient
• Test topology: as described in chapter 2.4 on page 18
• Termination: as described in the test topology; differences are specified in
the used test case
• Amount of nodes: as described in the test topology
• Amount of Stars: as described in the test topology
• Baud rate: 10 Mbit/s (gdBit = 100ns) as part of the harmonized baud rates
in the FlexRay consortium
• Common mode choke as specified in chapter 2.4.5.
2.4 Test Topology

The purpose is to test the expected worst case of a possible topology with the
maximum number of cascaded active stars, one passive star and one passive bus.
It is sufficient to test only with one physical channel, because the behaviour of the
physical layer is independent from the number of used channels in a communication
network.
The used test topology is described in the following sections and shown in Figure
2-4.

Item Description
Ground
Local ground of node 24
3m Splice for power supply wires
1.5m Bus wire
Bus termination

Cable shield connection
VBat 2m Length of the power supply wire

GND 0.5m
and
VCC 4m the ground connection
GND 0.5m
Node
1
11 Active star
2 AS 4
PS
Passive star
1.5m 0.15m 10m Passive bus with stubs

0.
0.2m
0.2m
0.2m
2m
3 Bus splice as part of the passive bus
VBAT power supply

VBAT
VCC power supply

VCC

Item Description
VIO power supply

VIO
Chassis of
test system
Table 2-1: Test Topology Description

Version 1.0
VIO splice for Node 24
VBAT splice for AS VIO
Battery
VBAT 3m
3m
0.1m 0.1m GNDNode24
VCC splice for AS VCC splice for Node 24

VCC VCC
3m 3m
VBat 2m
0.1m GND 0.5m 0.1m GNDNode24
VBAT splice for Nodes, except Node 24 1 VBAT splice for Node 24
Battery
VBAT VBAT
3m 3m
termination active star
0.1m
1m
0.1m GNDNode24
passive star channel number
11 passive bus
cable shield 3 2
length of 11m 2 4
1
PS AS 1.5m 0.15m 10m
December-2005
communication lines VBAT 4m 3
0.
m 0.2 VCC 4m 2m
0.2
5 5m
0.2m
0.2m
0.2m
GND 0.5m
1m
0. 2
5m
3.5m
VGS 2m
24 23 22 21 2 14 13 12 11
Figure 2-4: Conformance Test Topology

VBat 4m VBat 5m VBat 3m VBat 4m VBat 6m VBat 10m VBat 9m VBat 8m VBat 6m
VCC 4m GND 0.5m GND 0.5m GND 0.5m GND 5m GND 0.5m GND 0.5m GND 0.5m GND 0.5m
VIO 4m VGS 2m
GND 0.5m length of supply lines: from nodes and star
VGS 2m 4 GND splices
to VBat splice, to VCC splice and to VIO splice
to GND splice, VGS see text below
Page 21 of 816

Description of the test topology:

• A detailed description of the AS hardware may be given in chapter 2.4.5.
• A detailed description of the passive star hardware is given in chapter
2.4.7.
• A detailed description of the passive bus hardware is given in chapter
2.4.8.
• Nodes without ground shift stress must be connected with their negative
terminal to one of the ground splices that are mounted on the stainless
steel chassis.
• The four ground splices shall be mounted near the nodes and the AS to
consider the length of the GND cables of the nodes and the AS. The
following nodes are connected to one of the GND splices:

GND splice 1: Nodes 11, 12, 13 and 14
GND splice 2: Nodes 21, 22, 23 and 24
GND splice 3: Nodes 1, 2 and the AS
GND splice 4: negative terminal of all supplies
• Nodes, that are stressed with ground shift, are connected to a switch1, that
guarantees, that these nodes could be connected directly to ground or are
stressed by ground shift. This switch shall be controllable by the SV. The
attenuation of the used switches shall be as small as possible.
• The ground shift terminal of the nodes and the AS are connected to the
positive terminal of the ground shift generator. The length of this cable is
1m.
• The negative terminal of the ground shift generator is connected to the
GND splice of the test system (chassis). The length of this cable is 1m.
• All nodes must be connected to the battery splice (+) that is mounted on
the chassis.
• The AS must be connected to the VBAT splice (+) for the AS that is
mounted on the chassis.
• The AS must be connected to the VCC splice (+) for the AS that is mounted
on the chassis.
• Node 24 must be connected to the VBAT splice (+) for the node that is
• Node 24 must be connected to the VCC splice (+) for the node that is
• Node 24 must be connected to the VIO splice (+) for the node that is
• The chassis must be a steel plate for the ground connections of the IUTs
and the power supply.
1
The switch shall be on the nodes and the AS. The connections from the switch to the terminals shall
be as short as possible.

•The chassis is connected to the negative terminal of the power supply

(clamp 31).
• The battery splice is connected to the positive terminal of the power supply
(clamp 30).
• The VBAT splice for the nodes is connected to the positive terminal of the
nodes VBAT power supply.
• The VBAT splice for the AS is connected to the positive terminal of the AS
VBAT power supply.
• The VCC splice for the AS is connected to the positive terminal of the first
+5V power supply.
• The VBAT splice for the node 24 is connected to the positive terminal of the
VBAT power supply for node 24.

• The VCC splice for the node 24 is connected to the positive terminal of the
second +5V power supply.
• The VIO splice for the node 24 is connected to the positive terminal of the
VIO power supply.
• All communication channels must be terminated regarding the [01-PL
Spec].
• The shield of every link must be terminated regarding the [01-PL Spec].
• The bus cables must meet the requirements of the [01-PL Spec]; see also
chapter 2.4.9.1 on page 33. All bus cables are shielded. The shield is only
connected at the AS (see also chapter 2.4.2).
• The supply cables must meet the requirements specified in chapter 2.4.9.2
on page 34.
The following topics are part of the implementation of the conformance test, but have
to meet the [01-PL Spec]:
• the type of mounting of the IUTs on the chassis
• the type and manufacturer of the cables
• the type and manufacturer of the connectors
• the type of the battery splice
• the wiring of the IUTs
2.4.1 Cable overview of the test topology

No. Type From To Length Termination Remarks
[m]
1. Bus wire Node 1 Active star 1 Both ends
2. Ground wire Node 1 GND splice 3 0.5 -
3. Supply wire Node 1 Battery splice 2 -
4. Bus wire Node 2 Active star 3.5 Both ends
5. Ground wire Node 2 GND splice 3 5 -


[m]
7. Bus wire Node 11 Bus splice 1 0.2 No termination Part of the passive bus
10. Bus wire Node 12 Bus splice 1 0.2 Only at node 12 Part of the passive bus

19. Bus wire Node 21 Passive star 0.25 No termination Connected to the passive
star
star
25. Bus wire Node 23 Passive star 1 Only at node 23 Connected to the passive
star
2
28. Ground shift wire VGS supply Node 23 1 - Connected to positive
terminal
29. Ground shift wire3 VGS supply GND splice 4 1 - Connected to negative
terminal
star
2
Positive terminal of the Ground Shift Generator
3
Negative terminal of the Ground Shift Generator


[m]
33. Ground shift wire2 VGS supply Node 24 1 - Connected to positive

terminal
3
34. Ground shift wire VGS supply GND splice 4 1 - Connected to negative
terminal
35. Ground wire Active star GND splice 2 0.5 -
36. Supply wire Active star VBAT splice 4 -
37. Supply wire Active star VCC splice 4 -

38. Bus wire Active star Passive star 11 Only at active star
39. Bus Wire Active star Bus splice 3 1.5 Only at active star
40. Ground shift wire2 VGS supply Active star 1 - Connected to positive
terminal
3
41. Ground shift wire VGS supply GND splice 4 1 - Connected to negative
terminal
42. Bus wire Bus splice 1 Bus splice 2 10 No termination Part of the passive bus
43. Bus wire Bus splice 2 Bus splice 3 0.15 No termination Part of the passive bus
44. Supply wire Battery Battery splice 3 - VBAT supply for nodes
45. Ground wire Battery GND splice 4 0.1 - VBAT supply for nodes
46. Supply wire Battery Battery splice 3 - VBAT supply for AS
47. Ground wire Battery GND splice 4 0.1 - VBAT supply for AS
48. Supply wire VCC Supply VCC splice 3 - VCC supply for AS
49. Ground wire VCC Supply GND splice 4 0.1 - VCC supply for AS
50. Supply wire Battery Battery splice 3 - VBAT supply for node 24
51. Ground wire Battery GND splice 4 0.1 - VBAT supply for node 24
52. Supply wire VCC Supply VCC splice 3 - VCC supply for node 24
53. Ground wire VCC Supply GND splice 4 0.1 - VCC supply for node 24
54. Supply wire VIO Supply VIOsplice 3 - VIO supply for node 24
55. Ground wire VIO Supply GND splice 4 0.1 - VIO supply for node 24
56. Ground wire Passive star GND splice 2 0.1 Ground connection of PS
Table 2-2: Cable Overview of Test Topology

2.4.2 Shield
Each communication link must have one cable shield connection. The conformance
test uses one active star, that is the central point of shield connection in the topology.
Table 2-3 and Figure 2-5 show the specified shield connection with bus cable,
connectors, active star and node:
Name Description Typ Unit
Rs Damping resistance 1000 Ω
Tolerance 1 %
Cs Capacitance 470 nF

Tolerance 10 %
L2, R2, R3 and C1 Components of the passive star, see chapter 2.4.7.
Table 2-3: Shield Connection Components
Node Active Star Passive Star Node
Bus Cable Bus Cable Bus Cable

Cs Cs L2 L2
Rs Rs
R2 R2
Cable Shield Cable Shield C1 Cable Shield
R3
Figure 2-5: Cable Shield Connection

The cable shield of each branch at the AS is connected via Rs and Cs to the local
ground of the AS.
The cable shield of each branch at the PS is connected via L2 and R2 to C1 and R3 to
the local ground of the PS, see chapter 2.4.7.
The shield must not be interrupted between the housings of the active star, nodes
and the passive star.
2.4.3 ESD Protection

To emulate the load of ESD protection circuits every BD has a specified load at the
bus terminals:

ECU
CBP
BP
RT1
FlexRay Bus
BD R1 CDiff
C1
RT2

BM
CBM
Figure 2-6: ESD Load Circuit
CBP Capacitance of BP to GND 47 pF
Tolerance; NP0 dielectricum 5 %
CBM Capacitance of BM to GND 47 pF
CDiff ECU’s differential input capacitance 39 pF
Table 2-4: ESD Load Circuit

As described in Figure 2-6 the ESD load circuit is placed on the board between the
termination and the bus terminals. If no termination exist the ESD load circuit is
placed between the CMC and the bus terminals.
2.4.4 Termination
Each terminated node and star as described in the test topology must have the
following split termination:

BP
3.5m
C1 R RT1
1
IUT
RT2
2
BM
Figure 2-7: Terminated Node

The RDCLoad is specified in [01-PL Spec] in chapter 4.6 on page 21. See also figure 4-
5 in [01-PL Spec].
For the nominal (default) RDCLoad the termination resistor (as specified in figure 4-1
on page 19 and 4-5 on page 21 in [01-PL Spec]) is defined as e.g. RT= RT1+RT2.
Values of discrete components:
RT1 Resistor of split termination Z0 4 Ω

2
Tolerance 1 %
RT2 Resistor of split termination Z0 4 Ω

2
Tolerance 1 %
R1 Resistor 5 Ω
Tolerance 1 %
C1 Ceramic capacitor 4.7 nF
Tolerance 10 %
Table 2-5: Split Termination Components

The value of Z0 depends on the used bus cable. This cable is defined in chapter
2.4.9.1.
4
Z0: impedance characteristic of the used cable. See also chapter 2.4.9.1

Some nodes in the test topology have no termination. Figure 2-8 shows the bus
connection of an unterminated node.
BP
0.2m
IUT
BM 14

Figure 2-8: Unterminated Node
2.4.5 Common Mode Chokes

Common mode chokes shall be used within the conformance testing of bus drivers
as follows:
ECU
BP
RT1
CMC FlexRay Bus
BD R1
C1
RT2
BM
Figure 2-9: Common Mode Choke Implementation

As described in Figure 2-9 the CMC is placed on the board between the IUT and the
termination. If no termination exist the CMC is placed between the IUT and the ESD
protection circuit.

The manufacturer of the CMC is: Epcos

The type of the CMC is: B82789C0104N002 (bifilar winding)
2.4.6 Active Star

The conformance test specification does not prescribe a certain implementation of
the AS. This depends on the device specification of the IUT.
2.4.7 Passive Star

The passive star shall be implemented as follows:

Shield
BM
BP
Bus
Plug 1
L1
BP
R1
L1
BM
R1
L2

C1 R3
Shield
R2
GND Splice
Bus
Plug n
L1
BP
R1
L1
BM
R1
L2
Shield
R2
Figure 2-10: Passive Star Implementation
R1 Series resistance on signal wire 22 Ω
Tolerance 1 %
L1 Series inductance on signal wire 220 nH

Tolerance 10 %
R2 Series resistance on signal wire 100 Ω
Tolerance 1 %
L2 Series inductance on signal wire 220 nH
Tolerance 10 %
R3 Inductance of shield to system ground 1 MΩ

Tolerance 1 %
C1 Capacitance to system ground 100 nF
Tolerance 10 %
Table 2-6: Passive Star Implementation

The ground of the passive star is connected to GND splice 2 with a ground wire of
0.1m length.
2.4.8 Passive Bus

The passive bus shall be implemented as follows:

Splice
BP
Cable Cable
Bus
Bus
BM
Shield
Zoom Node x

BP
BM
Shield
Node x
Bus
Bus
Figure 2-11: Passive Bus Implementation

The plugs shall be realized with 9 pin Sub-D connectors mounted on a small board.
The wires between the connectors shall be as short as possible.
2.4.9 Cables
2.4.9.1 Bus Cables

The used bus cables in the conformance test must have a shield and require the
following conditions:

Name Description Typ Tolerance Unit
Z0 Differential mode 90 ± 2% Ω
impedance @ 10 MHz5
Table 2-7: Bus Cable Impedance
Name Description Min Max Unit
T’0 Specific line delay 10 ns/m
α5MHz Cable attenuation @ 5 MHz 82 dB/km

lBus Maximum electrical distance 24 m
between two nodes6 or
active stars, see also [01-PL
Spec]
lStubDistanceM,N Distance between two 150 mm

network splices
Table 2-8: Bus Cable Characteristics

See further recommendations about bus cables in the application notes of [01-PL
Spec].
An example for a bus cable is:
Cable manufacturer: Gebauer & Griller
Cable type: xF8FF_2_B56_FlM02YHBY
2.4.9.2 Power supply cables

The used cables in the conformance test must require the following conditions:
ACross section Cross section of GND and 1.5 mm2

power supply wires
Table 2-9: Supply Cable Characteristics

An example for a supply cable is:
5
According to DIN VDE0472 Part 516
6
Including passive stars and splices

Supply cable manufacturer: Coroplast

Supply cable type: FLRY-A 2.5
2.4.10 Connectors
The used connectors in the conformance test must require the following conditions:
RDCContact Contact resistance 50 mΩ

(including crimps)
ZConnector Impedance of connector 70 200 Ω

lCoupling Length coupling connection7 150 mm
dContactInterruption Contact interruption; 100 ns

RDCContact > 1 Ω8
Table 2-10: Connectors Characteristics

See further recommendations about connectors in the application notes of [01-PL
Spec].
An example for a connector is:
Connector manufacturer: Erni
Connector type: Sub-D 9 pin
2.5 Test Equipment
2.5.1 General
Hint: In every test case the accuracy/resolution of each generator and measurement
device must be taken into account.
Hint: INH1 is floating while the IUT is in sleep mode and at VBAT level while the IUT
is not in a sleep mode. A pull down resistor shall be used to force a floating INH1
output to ground.
The logical level of the optional signal INH1 must be interpreted as:
uVBAT
• Logical High: uINH1 > 2
7
To be measured from end to end of untwisted area in the connected cables
8
the time limit reflects the state of the art measurements techniques and potentially needs to be lower

uVBAT
• Logical Low: uINH1 < 2
2.5.2 Power Supply VBAT

The power supply must be connected with the negative terminal to the chassis of the
test system (that is connected to the ground pin) and with the positive terminal to the
VBAT splice of the communication network. This supply simulates a battery in an
automotive environment.
The default voltage of VBAT is the maximal battery operational range defined in the
data sheet of the IUT up to +42V.
Alternatively, for some test cases, the IUT is powered by a low battery generator as

defined in 2.5.6 instead.
Output Description Min Max Unit
VBAT Supply voltage DC +50 V
Ripple (rms) AC 10 mV
Imin 5 A
Precision/Accuracy 1 %
Table 2-11: VBAT Power Supply Characteristics

An example for this supply is:
Supply manufacturer: Toellner
Supply type: 8825-64
Used voltages of VBAT: +14V…+42V, +7.0, +5.5V, +2.0V.
Hint: Node 24 must support to be supplied independently by extra VBAT, VCC and VIO
power supplies.
Hint: The active star must support to be supplied independently by extra VBAT and
VCC power supplies.
2.5.3 Power Supply VCC

VCC splice of the communication network. This supply simulates the voltage regulator
inside an active star or a node in an automotive environment.
The default voltage of VCC is +5.0V.

VCC Supply voltage DC +5.05 V
Imin 0.7 A
Table 2-12: VCC Power Supply Characteristics


Hint: The VCC on the nodes shall be generated by local voltage regulators and are
not independent from VECU.
Used voltages of VCC: +5.0 (normal), +2.0 (undervoltage).
Node 24 must be supplied independently by an extra VCC power supply.
2.5.4 Power Supply VIO

VIO splice of the communication network. This supply simulates the voltage regulator
inside a node in an automotive environment.
The default voltage of VIO depends on the I/O voltage of the devices counterpart, i.e.
the host.
VIO Supply voltage DC +5.05 V
Imin 0.7 A
Table 2-13: VIO Power Supply Characteristics

Supply type: TOE 8840

Hint: The VIO on the nodes shall be generated by local voltage regulators and are not
independent from VECU.
Standard voltage of VIO: depends on implementation.
Undervoltage of VIO: +0.75.
Node 24 must be supplied independently by an extra VIO power supply.
The logical high level of the digital signal is specified in chapter 11 in [01-PL Spec]
on page 81.
2.5.5 Ground Shift Generator

This generator is used to simulate ground shift between selected nodes and stars of

a communication network. It is connected between the predefined ground pin of the
node or star and the chassis of the test system (ground connection of the power
supply).
UGS Ground shift voltage DC 0 +5 V
Imin 0.8 A
Table 2-14: Ground Shift Generator Characteristics

Supply manufacturer: Kepco
Supply type: BOP 20-10M
2.5.6 Low Battery Generator

This generator is used to simulate a low battery voltage that appears when turning
on the starter circuit. The power supply must be connected with the negative terminal
to the chassis (that is connected to the ground pin) and with the positive terminal to
the VBAT splice of the communication network. This supply may be the same as
specified in chapter 2.5.2 and depends on the test case.
The IUTs are supplied by either this low battery generator or a battery power supply
as defined in 2.5.2.
The test signal is defined in [06-DIN1].

VECU Low battery voltage DC +14 V
Imin 5 A
Table 2-15: Low Battery Generator Characteristics


2.5.7 Signal Generator

The signal generator is connected to TxD, TxEN and BGE9 of the bus driver and its
ground pin. The generator is used to provide various test patterns, that are described
in the test cases chapters below.
UTxD Bit time in test pattern 100 400 ns
Voltage level of test pattern for 0 5 V

digital input
Imin 10 mA
Fall time of signal @ digital input of 3 ns

IUT
Rise time of signal @ digital input 3 ns

of IUT
Table 2-16: Signal Generator Characteristics

An example for this generator is:
Generator manufacturer: Agilent
Generator type: 16720A
9
only if this signal is available

2.5.8 Analog Signal Measurement

The characteristics of the measurement device are described in this chapter. This
may be an oscilloscope or equivalent device.
Input Description Min Max Unit
Ux Voltage level of analog test 0 14 V

signals
Cx Input capacitance of probe 10 pF
Rx Inpuit resistance 1 MΩ

Sample Rate 800 MSa/s
Bandwidth 200 MHz
Table 2-17: Analog Measurement Device Characteristics

An example for this oscilloscope is:
Oscilloscope manufacturer: LeCroy
Oscilloscope type: Waverunner 6050
2.5.9 Digital Signal Measurement

shall be a logic analyzer or equivalent device.
Ux Voltage level of digital test signals -5 5 V
Bandwidth 2 GHz
Cx Capacitance load 10 pF
Rx Resistive load 0.1 MΩ
Number of channels 96 -
Timing sample rate 2 ns

(full channel mode)
Table 2-18: Digital Measurement Device Characteristics

An example for this logic analyzer is:
Logic analyzer manufacturer: Agilent

Logic analyzer type: 16911A
2.5.10 Data Acquisition Unit

shall be a unit for measuring voltages or currents.
Ux Absolut input voltage -5 5 V
Ix Absolut input current -1 1 A
Number of channels 2 -

Timing sample rate 600 S/s
(full channel mode)
Table 2-19: Data Acquisition Unit

An example for this data acquisition unit is:
Data acquisition unit manufacturer: Agilent
Data acquisition unit type: 34970A
2.5.11 Broadband Amplifier

The characteristics of this generator are described in this chapter. This device is
necessary for dynamic ground shift.
Ux Absolut output voltage 0 10 V
Frequency range (-3dB) 0 500 kHz
Gain 13 dB
imin 1 A
Precision/Accuracy 0.5 %
Response time 1 µs
Table 2-20: Broadband Amplifier

An example for this broadband amplifier is:
Broadband amplifier manufacturer: Toellner

Broadband amplifier type: 7608
2.5.12 Arbitrary Function Generator

The characteristics of this generator are described in this chapter. This device is
necessary for dynamic ground shift.
Ux Voltage level of digital test signals 0 2 V
Frequency range (-3dB) 0 500 kHz
Sample rate 50 MS/s

Table 2-21: Arbitrary Function Generator

An example for this arbitrary function generator is:
Arbitrary function generator manufacturer: Agilent
Arbitrary function generator type: 33250A

3 Stress Conditions
3.1 Ground Shift
The ground shift is located between the chassis and the predefined ground
connection of the used IUTs. Every test case describes the usage of the ground shift
and that IUT is/are affected.
Node IUT IUT

(not stressed) (Nodes 1-23) (Node 24)
VIO BD VCC BD
VIO VCC VIO VCC VCC VIO

+ - + - + internal
- external
+
UGS
UBAT - UGS
+ -
UBAT
Figure 3-1: Usage of Ground Shift
Signal Description Min Max Unit
UGS Static ground shift voltage +5 V
Table 3-1: Ground Shift

Location of ground shift in the test topology:
1m
Ground Shift Injection
11
PS 11m 2 AS 4 1.5m 0.15m 10m

3
0.
0.2m
0.2m
0.2m
m 0.1 2m
0.2
3.5m
0.2 m
1m
24 23 22 21 2 14 13 12 11

Ground Shift Injection
Figure 3-2: Location of Ground Shift
3.2 Low Battery Voltage inside operational Range

The test condition in case of a heavily discharged battery inside the operational
range (with respect to the supply voltage boundaries specified in [01-PL Spec]) is
called low battery voltage inside operational range. The behaviour of the IUT during
this stress condition is very important regarding the low power modes and the wake-
up mechanism.
Since the kind of diode (Schottky, etc.) inside the ECU varies from application to
application VBAT is the stress voltage instead of VECU. The difference between VECU
(supply voltage at the ECU) and VBAT (the voltage at the bus driver pin), is described
in Figure 3-3.
Requirements:
• All nodes including the IUTs and hosts of the topology (in bus driver test
cases) / the active star (in active star test cases) shall be supplied by this
low battery voltage.

ECU/Star
VBAT VECU
Diode
BD
+ -
Battery
GND GND
Figure 3-3: Description of VBAT and VECU

Signal Description Min Max Unit
VBATlow Low battery voltage for evaluation +5.5 V

of wake-up detection if VCC is not
implemented and non wake-up
test cases are applied.
VBATlow Low battery voltage for evaluation +7.0 V

of wake-up detection if VCC is
implemented.
Table 3-2: Stress Condition Static Low Battery Voltage inside operational
Range
3.3 Undervoltage
The behaviour of the IUT during this stress condition is very important regarding the
low power modes and the wake-up mechanism, especially for the recovery
functionality of the IUT.
• In case of presence of a VBAT pin of the IUT: VBATUndervoltage= +2.0V.
• In case of presence of a VCC pin of the IUT: VCCUndervoltage= +2.0V.
• In case of presence of a VIO pin of the IUT: VIOUndervoltage = +0.75V.
3.4 Dynamic Low Battery Voltage

The IUT will also be affected by a test signal 4’ (according to ISO 7637 and DIN
40839). The test signal 4’ emulates a low battery voltage that appears when turning
on the starter circuit, so the generator is connected to VECU of the IUT.

Signal Description Value Unit
US Battery voltage difference after tr at the IUT 7.6 V
UA Battery voltage difference after t7 at the IUT 6.1 V
UB Nominal battery voltage at the IUT 11.6 V
tf Fall time of battery voltage 5 ms
t6 Time of US 15 ms
t7 Rise time of battery voltage 50 ms
t8 Time of UA 10000 ms

tr Rise time of battery voltage 100 ms
US/tf1 Fall time of US for tf1 (simulates a small 7.6/5 V/ms

capacitance in an ECU)
US/tf6 Fall time of US for tf6 (simulates a big 6.1/300 V/ms

capacitance in an ECU)
Table 3-3: Stress signal 4’
VBAT
US/tf1
US/tf6
US UA
UB
tf t6 t7 t8 tr t
Figure 3-4: Stress signal 4’

3.5 Failures
This stress parameter shall examine the behaviour of the IUT in case of failures
onboard. A faulty link might be a faulty connection between the power lines or the
digital signals.
Requirements:
• Only one link is stressed by one test parameter.
• The test nodes are supplied as specified in the test case.
• Check the behaviour of the IUT while stressed
• Check the recovery of the IUT after removal of stress

1
1m
11
PS 11m 2 AS 4 1.5m 0.15m 10m

3
0.
0.2m
0.2m
0.2m
m 0.1 2m
0.2
3.5m
0.2 m
1m
24 23 22 21 2 14 13 12 11
Onboard Failures
Figure 3-5: Location of the onboard Failures
Overview of all failures:
Abbreviation Condition Description
FL110 I/R VBAT Interruption of supply line VBAT of the IUT
FL2 I/R VCC Interruption of supply line VCC of the IUT
FL3 I/R VBAT and VCC Interruption of supply lines VBAT and VCC of
the IUT
FL4 S/C TxEN GND Short circuit between TxEN and ground
FL5 I/R TxEN Interruption of TxEN11
10
FL means Failure
11
Interruptions means floating

Abbreviation Condition Description
FL6 I/R TxD Interruption of TxD11
FL7 Minimum RDCLoad Minimum allowed bus load (40 Ω)12, see [01-
PL Spec]. See also Figure 2-7.
FL8 Maximum RDCLoad Maximum allowed bus load (55 Ω)12, see [01-
PL Spec]. See also Figure 2-7.
FL9 I/R STBN Interruption of STBN11
FL10 I/R BGE Interruption of BGE11

FL11 S/C BP GND Short circuit between BP and GND
FL12 S/C BM GND Short circuit between BM and GND
FL13 S/C BP +48V Short circuit between BP and +48V
FL14 S/C BM +48V Short circuit between BM and +48V
FL15 I/R GND_IUT Loss of GND of the IUT
FL16 I/R GND_Node Loss of GND of the whole node or AS
FL17 I/R VIO Interruption of supply line VIO of the IUT
FL18 I/R CTRL2 Interruption of CTRL211
Table 3-4: Faulty Lines Test Parameter
IUT IUT
VBAT VBAT
VCC VCC
FL1: VIO FL2: VIO
12
This termination is done in node 23

IUT IUT
VBAT VBAT
VCC VCC
FL3: VIO FL17: VIO
Figure 3-6: Failure/Loss of Supplies

TxD TxD TxD
TxEN TxEN TxEN
IUT BGE IUT BGE IUT BGE
STBN STBN STBN
CTRL2 CTRL2 CTRL2
FL5: FL6:
FL4: GND
TxD TxD TxD

TxEN TxEN TxEN
IUT BGE IUT BGE IUT BGE
STBN STBN STBN
CTRL2 CTRL2 CTRL2
FL10: FL9: FL18:
Figure 3-7: Failures of digital Signals TxEN, TxD, BGE and STBN
BP BP
IUT IUT
BM BM
GND GND
FL11: +48V FL12: +48V

BP BP
IUT IUT
BM BM
GND GND
FL13: +48V FL14: +48V
Figure 3-8: Failures of Bus Wires BP and BM

IUT IUT
GND FL16: GND

FL15:
Figure 3-9: Failures of GND Wire
1
1m
11
PS 11m 2 AS 4 1.5m 0.15m 10m

3
0.
0.2m
0.2m
0.2m
m 0.1 2m
0.2
3.5m
0.2 m
1m
24 23 22 21 2 14 13 12 11
Faulty Termination
Figure 3-10: Location of Termination Changes inside a Node

3.6 Babbling Idiot

The AS must recognize a babbling idiot at a branch in order to prevent the
communication of the other nodes from a faulty node. This is also described in [01-
PL Spec].
Requirements:
•The test signal supplies the TxD pin of the babbling idiot(s).
•The TxEN is active while sending data (the IUTs are enabled to transmit
data from their CCs/hosts).
• An optionally BGE signal is also active (the IUTs are enabled to transmit
data from their CCs/hosts).
• Optionally mode control signals shall be set to normal mode of the IUTs.

The test signal is specified in chapter 6.1.3.1.
3.7 Dynamic Ground Shift

The IUT shall also be affected by a dynamic ground shift. The connection and usage
are described in chapter 3.1.
4 Bits = 400ns
6V
UGS 3 Bits = 300ns 2V

0V
10 Bits = 1 µs
25µs 1ms
Figure 3-11: Dynamic Ground Shift Curve - Input

Due to internal filters and the speed of a broad band amplifier the output (uGS_dyn)
may look like the yellow curve in the following figure (the input signal is drawn in
voilet):


Figure 3-12: Dynamic Ground Shift Curve - possible Output
3.8 EMC
This conformance test specification does not support EMC stress conditions. This is
part of a separate specification, that is part of the FlexRay consortium in the
corresponding working group.
3.9 ESD
This conformance test specification does not support EMC stress conditions. This is
part of [07-EMC Spec].
3.10 Temperature Tests

This conformance test specification does not support temperature tests as a stress
condition. This is part of the semiconductor manufacturer and included in the data
sheet of the corresponding physical layer device.

4 Parameter List
The parameter list is organized by a tree and structured by the system operation
variable space (SOVS). The SOVS approach is a specific method to derive test
cases by combining basic system “variables” with each other.
The system operation conditions are given from experience from existing
communication systems. In order to have an easier way of reproducibility the test
parameters are grouped into the following variables:
Static Test Cases

Communication
Mode
Power Supply
Environment
Dynamic Low Battery

Voltage
Ground Shift
Failure
Functional Class
Figure 4-1: Overview of the SOVS Parameters
All combinations of these variables represent all theoretical possible test cases. This
would result in a huge number of test cases. But the number of combinations can be
reduced dramatically by defining variables as “constant” (e.g. environment) or by
selecting just a few representative (i.e. concerted) values for each variable. So the
relevant test cases are selected in the test case chapters beginning from page 67.

4.1 Static Test Cases

These tests must be done manually and contain the comparison of the data sheet of
the IUT with the required parameters. There is no automatic test with hard- and
software necessary.
Static Test Cases
Figure 4-2: SOVS Static Tests
4.2 Communication

This vector contains the test parameters that affect the data communication of the
test system in normal operational mode.
This item is divided in some more sub items:
Communication Delay
Signal Shape
Threshold
Timing Masks
Truncation Shortened Bit Times
Figure 4-3: SOVS Communication with Sub Items
4.2.1 Delay
The sub item delay contains all relevant tests with the focus on delay in the data
communication.

Delay dStarDelay
dStarDelay0
dStarAsym
dStarSetUpDelay
dBDTx01
dBDTx10
dTxAsym

dBDRx01
dBDRx10
dRxAsym
dASTx01
dASTx10
dASRx01
dASRx10
Figure 4-4: SOVS Delay with FlexRay Parameters
4.2.2 Signal Shape

The sub item signal shape contains all relevant tests with the focus on the signal
form.

Signal Shape dBusTxai
dBusTxia
uBDTxactive
uBDTxidle
uASTxactive

uASTxidle
Eye Diagram
Figure 4-5: SOVS Signal Shape with FlexRay Parameters
4.2.3 Threshold
Threshold test cases are static test cases and specified in the chapters 5.2, 6.2 and
7.2.

Threshold uVDIG-OUT-HIGH
uVDIG-OUT-LOW
uVDIG-IN-HIGH
uVDIG-IN-LOW
uBusActiveHigh

uBusActiveLow
uData_0
uData_1
uData
Figure 4-6: SOVS Threshold with FlexRay Parameters
4.2.4 Timing
The sub item timing contains all relevant tests with the focus on the timing of the
transmitted signal. This item is divided in some more sub items:

Timing dBDTxai
dBDTxia
dBDRx_ai
dBDRx_ia
dActivityDetection
dIdleDetection
dBranchActive

dBranchFailSilentIdle
dASTxai
dASTxia
dASRx_ai
dASRx_ia
Figure 4-7: SOVS Timing with FlexRay Parameters
4.2.4.1 Masks
This vector tests the asymmetric delay in the network.
Masks
Figure 4-8: SOVS Masks
4.2.5 Truncation
The sub item truncation contains all relevant tests with the focus on the star
truncation. This item is divided in some more sub items:

Truncation dStarTruncation
dTruncationM,N
Figure 4-9: SOVS Truncation with FlexRay Parameters
4.3 Mode
This vector contains the test parameters that contain the mode transitions and
especially the low power modes of the physical layer in node and active star
application.

Version 1.0
Mode Active Star Branch Active
Idle
FailSilent
Low Power
Normal GoToSleep
GoToSleep_Fail
December-2005
Bus Driver Low Power
Normal
Figure 4-10: SOVS Mode with Sub Items

ReceiveOnly
Page 60 of 816

4.3.1 Active Star

This sub vector contains all relevant test parameters regarding the bus driver
equipped in an active star. It is divided in several sub items:
4.3.1.1 Branch
Tests regarding the behaviour of branches.
Branch Active
Idle dBranchFailSilentIdle
FailSilent dBranchActive

Figure 4-11: SOVS Branch with Sub Items
4.3.1.2 Low Power

Tests regarding the low power mode.
Low Power dStarWakeUpReaction
dStarGoToSleep
Figure 4-12: SOVS Low Power with Sub Items
4.3.1.3 Normal
Tests regarding the normal mode and its behaviour.
Normal GoToSleep
GoToSleep_Fail
Figure 4-13: SOVS Normal with Sub Items
4.3.2 Bus Driver

This sub vector contains all relevant test parameters regarding the bus driver
equipped in a node. It is also divided in three sub items:
4.3.2.1 Low Power

Tests regarding the low power mode and its behaviour.

Low Power uBias – Low Power
Wake-up dWakePulse
dWU0Detect
dWUIdleDetect
dWUTimeout

Figure 4-14: SOVS Normal with Sub Items
4.3.2.2 Normal
Tests regarding the normal mode and its behaviour.
Normal uBias – BD_Normal
Figure 4-15: SOVS Normal with Sub Item
4.3.2.3 ReceiveOnly
Tests regarding the operation mode BD_ReceiveOnly and its behaviour.
ReceiveOnly
Figure 4-16: SOVS ReceiveOnly
4.4 Power Supply

This vector stresses the physical layer at its given pins, e.g. undervoltage.
This SOVS parameter has three more sub items.
Power Supply Undervoltage VBAT
Undervoltage VCC
Undervoltage VIO
Figure 4-17: SOVS Power Supply

4.5 Environment
The environment of the IUT is tested by this vector.
This SOVS parameter does not have sub items.
Environment
Figure 4-18: SOVS Environment
4.6 Dynamic Low Battery Voltage

This vector emulates the start of an engine with a dynamic low battery voltage. The

supply voltage is specified in chapter 3.4.
This SOVS parameter does not have sub items.
Dynamic Low Battery

Voltage
Figure 4-19: SOVS Dynamic Low Battery Voltage
4.7 Ground Shift

This vector stresses the physical layer with a specified ground shift as described in
chapter 3.1 on page 43. The ground shift generator requirements are described in
chapter 2.5.5 on page 36.
Ground Shift Dynamic Ground Shift
Figure 4-20: SOVS Ground Shift
4.8 Failure
This vector stresses the physical layer with predefined failures of the links, power
supplies and termination. The failures are described in chapter 3.5 on page 47.

Failure Babbling Idiot
Loss Power VBAT
TxD VCC
TxEN VIO
GND IUT
CTRL2 Node / AS
STBN
BGE
Short Circuit BM
BP

TxEN
Termination Minimum RDCLoad
Maximum RDCLoad
Nominal RDCLoad
Figure 4-21: SOVS Failure with Sub Items
4.8.1 Babbling Idiot

This vector contains the test parameter regarding the detection and signaling of a
babbling idiot.
This vector does not have any sub items.
Babbling Idiot
Figure 4-22: SOVS Babbling Idiot
4.8.2 Loss
This vector describes the possible loss of supply lines and digital signals at the bus
driver.

Loss Power VBAT
TxD VCC
TxEN VIO
GND IUT
CTRL2 Node / AS
STBN
BGE

Figure 4-23: SOVS Loss with several Sub Items
4.8.3 Short Circuit

This vector describes the possibility of short circuit of digital signals and the bus
wires and the behaviour of the bus driver.
Short Circuit BM iBMGNDShortMax
iBMBATShortMax
BP iBPGNDShortMax
iBPBATShortMax
TxEN
Figure 4-24: SOVS Short Circuit with Sub Items
4.8.4 Termination
This vector contains test parameters regarding different termination values.
Termination Minimum RDCLoad
Maximum RDCLoad
Nominal RDCLoad
Figure 4-25: SOVS Termination

4.9 Functional Class

Some functions of the IUT are grouped in functional classes that must be test by this
vector.
Functional Class BD voltage regulator control
Bus Driver – Bus Guardian control interface
Bus Driver internal voltage regulator
Bus Driver logic level adaption

Active Star – Bus Guardian interface
Active Star – Communication controller interface
Active Star – Voltage Regulator Control
Active Star – Internal Voltage Regulator
Figure 4-26: SOVS Functional Class

5 Test Cases for Bus Drivers within a homogeneous

Topology
5.1 Configuration
5.1.1 Topology
As specified in chapter 2.4. All IUTs are the same type and manufacturer.
5.1.2 Test Planes

5.1.2.1 Analog Signals
The test planes at the FlexRay node for analog signals (FlexRay bus) are the same
as specified in [01-PL Spec].
TP1 TP2 TP3 TP4
Transmitting Receiving
Node Node
BP
BD Network BD
BM
Figure 5-1: Test Planes @ the Nodes (analog Signals)
TP Name Signals Description
TP1 uBP/uBM Bus signals of the transmitter as close as possible to the

chip
TP2 uBP/uBM Bus signals of the transmitter at the connector near to the
network
TP3 uBP/uBM Bus signals of the receiver at the connector near to the
network
TP4 uBP/uBM Bus signals of the receiver as close as possible to the chip
Table 5-1: Test Planes @ the Nodes (analog Signals)

5.1.2.2 Digital Signals

The test planes at the FlexRay node for digital signals (observed by the logic
analyzer) are specified as:
TxEN
TxD
RxEN
RxD
BGE
CTRL2 IUT
STBN
SCSN
ERRN
INTN
WAKE
INH1

Figure 5-2: Test Planes @ the Nodes (digital Signals)
TP Name Signals Basis Description
TP_Nx_TxEN TxEN VIO/VCC Transmit Data Enable Not input signal of the
IUT
TP_Nx_TxD TxD VIO/VCC Transmit Data input signal of the IUT
TP_Nx_RxD RxD VIO/VCC Receive Data output signal of the IUT
TP_Nx_ERRN ERRN VIO/VCC Error Not output signal of the IUT (only if host
interface A is implemented)
TP_Nx_STBN STBN VIO/VCC Standby Not input signal of the IUT (only if
host interface A is implemented)
TP_Nx_INTN INTN VIO/VCC Interrupt Not output signal of the IUT (only if
host interface B is implemented)
TP_Nx_SCSN SCSN VIO/VCC The SCSN input signal of the SPI interface of
the IUT (only if host interface B is
implemented)
TP_Nx_CTRL2 CTRL2 VIO/VCC Mode control input signal of the IUT (only if
functional class "BD voltage regulator control"
is implemented)
TP_Nx_WAKE WAKE VBAT Local wake-up input signal input of the IUT
(only if functional class "BD voltage regulator
control" is implemented)

TP Name Signals Basis Description
TP_Nx_INH1 INH1 VBAT INH1 output signal of the IUT (only if

functional class "BD voltage regulator control"
is implemented)
TP_Nx_BGE BGE VIO/VCC BG Enable input signal (only if functional class

"Bus Driver - Bus Guardian control interface"
is implemented)
TP_Nx_RxEN RxEN VIO/VCC Receive Data Enable Not output signal of the
IUT (only if functional class "Bus Driver - Bus
Guardian control interface" is implemented)

Table 5-2: Test Planes @ the Nodes (digital Signals)
5.1.2.3 Naming Convention

The test planes used in this specification are divided in three parts for digital signals
and two parts for analog signals. The naming convention is defined as:
•
TPy_Nx for analog signals
y describes the location of the test plane
x represents the number of the node, see topology in chapter 2.4
• TP_Nx_YYY for digital signals
x represents the number of the node, see topology in chapter 2.4
YYY stands for the digital signal
• The analog test planes of the FlexRay bus are differential signals: uBus =
uBP - uBM.
• The digital test planes of the digital signals are single ended signals: uRxD,
uTxD and uTxEN.
Example 1:
TP_N1_RxD represents the test plane for the single ended signal RxD at node 1.
Example 2:
TP4_N23 represents the test plane for the differential analog bus signal of the
receiver at node 23.
5.1.2.4 Test Planes for the Oscilloscope

The oscilloscope observes the following test planes:
• TP_N23_RxD
• TP_N23_TxEN
• TP_N23_TxD

• TP1_N23 (if the node is a transmitter)

• TP4_N23 (if the node is a receiver)
• TP4_N2
• TP4_N12
• TP_N1_TxD
• TP_N1_TxEN
• TP_N2_TxD
• TP_N2_TxEN
• TP_N11_TxD
• TP_N12_RxD
• TP_N24_RxD

• TP_N23_TxD
1
1m
Test Planes for Oscilloscope 11
PS 11m 2 AS 4 1.5m 0.15m 10m

3
0.
0.2m
0.2m
0.2m
m 0.1 2m
0.2
3.5m
0.2 m
1m
24 23 22 21 2 14 13 12 11
BP/BM BP/BM BP/BM
TxD, TxEN & RxD
Figure 5-3: Test Planes for the Oscilloscope
5.1.2.5 Test Planes for the Logic Analyzer

The logic analyzer observes the following test planes:
• TP_Nx13_RxD
• TP_Nx_RxEN
• TP_Nx_TxD
• TP_Nx_TxEN
• TP_Nx_STBN
• TP_Nx_ERRN
• TP_Nx_INH1
• TP_Nx_WAKE
13
The number of the node depends on the test case

• TP_Nx_BGE
• TP_Nx_CTRL2
• TP_Nx_INTN
• TP_Nx_SCSN
5.1.2.6 Test Planes for the Pattern Generator

The pattern generator stimulates the following test planes:
• TP_Nx14_TxD
• TP_Nx_TxEN
• TP_Nx_BGE
5.1.2.7 Test Planes for current measurement

A shunt shall be implemented in order to measure the current of the bus wires:
• TP_Nx14_RiBP
• TP_Nx_RiBM
5.1.3 Test Patterns
5.1.3.1 Wake-up
The wake-up signal is specified in [08-Prot Spec] and shown in the following figure:
gdWakeupSymbolTxLow gdWakeupSymbolTxIdle
High
TxD Low
High
TxEN Low
Figure 5-4: Wake-up Symbol for the Test Pattern

The length of gdWakeupSymbolTxLow and gdWakeupSymbolTxIdle shall be
independent of the bus speed. The wake-up pattern shall be repeated
pWakeupPattern times.
Length of gdWakeupSymbolTxLow: 6 µs
Length of gdWakeupSymbolTxIdle: 18 µs
Number of repetitions (pWakeupPattern): 2
5.1.3.2 TSS
The TSS symbol is specified in [08-Prot Spec] and shown in the following figure:
14
The number of the node depends on the test case

gdTSSTransmitter
High
TxD
Low
High
TxEN Low
Figure 5-5: Test Pattern for the TSS Symbol

The length of gdTSSTransmitter (1100ns) depends on the bus speed (see [08-Prot
Spec]) and is specified in chapter 11.1.
The pattern of gdTSSTransmitter is sent in each test case once.
5.1.3.3 Data Signal 50/50

This test signal has a duty cycle of 50% (including the BSS):
gdBit
0 1 2 3 4 5 6 7 8 9
High
TxD Low
High
TxEN Low
Figure 5-6: Test Pattern for Data Signal 50/50

This test signal has a duty cycle of 10/90, that means that 1 bit has high and 9 bit
have low level (including the BSS):
gdBit
0 1 2 3 4 5 6 7 8 9
High
TxD Low
High
TxEN Low

This test signal has a duty cycle of 90/10, that means that 9 bit have high and 1 bit
has low level (including the BSS):

gdBit
0 1 2 3 4 5 6 7 8 9
High
TxD Low
High
TxEN Low
5.1.3.6 Data Signal 10Bit Low

The IUT shall signal Data_0 on the bus with this test signal.

gdBit
0 1 2 3 4 5 6 7 8 9
High
TxD Low
High
TxEN Low
Figure 5-9: Test Pattern 10Bit Low
5.1.3.7 Data Signal 10Bit High

This test signal is necessary to verify the BD_Standby state of the IUT. TxD shall
stay in logical HIGH state to be prepared for a possible additional feature called
“Wake on TxD”.
gdBit
0 1 2 3 4 5 6 7 8 9
High
TxD Low
High
TxEN Low
Figure 5-10: Test Pattern 10Bit High
5.1.3.8 Data Signal SymbolTxLow_Idle

This test signal shall be used to switch between Low and Idle.

gdSymbolTxLow gdSymbolTxIdle
High
TxD Low
High
TxEN Low
Figure 5-11: Test Pattern SymbolTxLow_Idle

Length of the gdSymbolTxLow: 6µs
Length of the gdSymbolTxIdle: 6µs
5.1.3.9 Current Measurement

This test pattern shall be used to measure the current flowing from the BD into the

bus wires.
Data_0 Idle Data_1 Idle

gdSymbolTxLow gdSymbolTxIdle gdSymbolTxHigh gdSymbolTxIdle
High
TxD Low
High
TxEN Low
1500µs 1500µs 1500µs 1500µs
Figure 5-12: Test Pattern for Current Measurement of Bus Wires
5.1.3.10 Non Wake-up short Idle Phase

This test pattern shall be used to check the robustness of the IUT not to wake-up in
case of a non suitable wake-up pattern due to a shorter idle phase.
Idle 6µs Data_0 0.9µs Idle 6µs Data_0 Idle

High
TxD Low
High
TxEN Low
Figure 5-13: Test Pattern for non suitable Wake-up short idle Phase
5.1.3.11 Non Wake-up short Low Phase

case of a non suitable wake-up pattern due to a shorter low phase.

Idle 6µs Data_0 6µs Idle 0.9µs Data_0 Idle

High
TxD Low
High
TxEN Low
Figure 5-14: Test Pattern for non suitable Wake-up short low Phase
5.1.3.12 Non Wake-up prolonged Pattern

case of a non suitable wake-up pattern due to a prolonged pattern.

Idle 6µs Data_0 140µs Idle 6µs Data_0 Idle
High
TxD Low
High
TxEN Low
Figure 5-15: Test Pattern for non suitable Wake-up prolonged Pattern
5.1.4 Observation Windows
5.1.4.1 Parameters dBDTx10, dBDTx01, dBDRx10 and dBDRx01
gdWakeupSymbolTxLow gdWakeupSymbolTxLow TSS

gdWakeupSymbolTxIdle gdWakeupSymbolTxIdle
60gdBit 180gdBit 60gdBit 180gdBit 11gdBit
High
TxD
Low
TxEN High
Low
High
RxD
Low
437.5 gdBit = 43.75µs 50/50 Pattern
Zoom – Observation Window 0.2µs 10gdBit
Trigger Event Zoom
0 1 2 3 4 5 6 7 8 9
High
TxD Low
High
TxEN Low
High
RxD Low
Observation Window
Figure 5-16: Observation Point for the Analysis of the Timing Characteristics
Trigger event: first positive edge of TxD or RxD signal.
Start acquisition point: 43.75µs after the trigger event.

Observation Window: 0.2µs

The [01-PL Spec] shows the measurement descriptions of the parameters
[dBDRx10, dBDRx01] in figure 8-6 and of the parameters [dBDTx10, dBDTx01] in
figure 8-8.
5.1.4.2 Verification of bus in idle state

The bus is verified to be in idle or idle_LP state at TP1/4 of node 23.
Trigger event: first negative edge of external trigger signal.
Start acquisition point: 0µs after the trigger event.
Observation Window: 5.0µs
The absolute differential voltage uBus must not exceed 30mV (uBDTxidle).

5.1.4.3 Shortened Bits with Low State
TSS 3x 10Bit Low 2x 10Bit Low
11gdBit 30gdBit 20gdBit
High
TxD Low
Zoom
High
TxEN Low
10/90 Pattern
10gdBit
Zoom – Observation Window
0 1 2 3 4 5 6 7 8 9
High
TxD Low
High
TxEN Low
Observation Window
Figure 5-17: Observation Point for the shortened Bits with Low State
Trigger event: first negative edge of uBus, trigger level -300mV.
Observation Window: 800ns

5.1.4.4 Shortened Bits with High State

TSS 3x 10Bit High 2x 10Bit High
11gdBit 30gdBit 20gdBit
High
TxD Low
Zoom
High
TxEN Low
90/10 Pattern
10gdBit
Zoom – Observation Window 300ns

0 1 2 3 4 5 6 7 8 9
High
TxD Low
High
TxEN Low
Observation Window
Figure 5-18: Observation Point for the shortened Bits with High State
Trigger event: first negative edge of uBus, trigger level -300mV.
Observation Window: 300ns
5.1.4.5 Dynamic Ground Shift

TSS
11gdBit 1x 50/50 pattern 9x 50/50 pattern
TxD
TxEN Observation Window 15µs
4 Bits = 400ns
6V
UGS 3 Bits = 300ns 2V

0V
10 Bits = 1 µs
25µs 1ms
Figure 5-19: Observation Point for Dynamic Ground Shift

Trigger event: first negative edge of TxD.
Start acquisition point: 500ns after the trigger event.
Observation Window: 15µs

5.1.4.6 Eye Diagram

TSS
11gdBit 10x 50/50 Pattern
High
TxD Low
High
TxEN Low
Figure 5-20: Observation Window for Eye Diagram

Trigger event: first negative edge of TxD.
Start acquisition point: 500ns after the trigger event.
Observation Window: 15µs

5.1.5 Power Modes of the Bus Driver
The IUT has the following power modes:
• BD_Normal: receive/transmit possible.
• BD_Standby: receive/transmit NOT possible.
• BD_Sleep: optional: receive/transmit NOT possible.
• BD_ReceiveOnly: optional: receive possible, transmit NOT possible.
The IUT reaches the power modes by:

Power Mode Hard Wired Signals SPI
BD_Normal STBN = High Product specific. Part
CTRL2 (optional15) = of the implementation.
High
BD_Standby STBN = Low Product specific. Part
15
CTRL2 (optional ) = Low of the implementation.
BD_Sleep16 STBN = Low Product specific. Part
CTRL2 (optional15) = of the implementation.
pull-up to VIO/VCC
15
Only available if functional class "BD voltage regulator control" is implemented
16
This combination of mode control signals of the hard wired signals (host interface A) is product
specific and is given as an example

Power Mode Hard Wired Signals SPI

BD_ReceiveOnly16 STBN = High Product specific. Part
15
CTRL2 (optional ) = Low of the implementation.
Table 5-3: Power Modes of the Bus Driver
5.1.6 Power Supplies

The used power supplies:
• In case of a VBAT pin the VBAT supply is connected to the IUT with different
voltages.
VBAT= +2.0, +5.5V, +7.0V, default.

• In case of a VCC pin the VCC supply is connected to the IUT with different
voltages.
VCC= +2.0, +5.0V.
All other supplies are optional and part of the implementation.
5.1.7 Stress
•The ground shift is located as shown in Figure 3-2.
•The low battery is a global stress parameter and affects all nodes of the
topology.
Note that the active star is not stressed at all in bus driver test cases! The AS is
always supplied with all implemented supply voltages and not stressed by low
battery or ground shift.
5.1.8 Failures
The failures are located as shown in Figure 3-5.
5.1.9 Optional Features

The following features are optional as specified in [01-PL Spec] and shall be tested
in the test cases if available in the IUT:
• BD mode BD_Sleep
• BD mode BD_ReceiveOnly
• Signal BGE
• Signal INH1
• Signal RxEN
• Signal WAKE
• Signal CTRL2
• Power supply input VIO
• Power supply input VCC
• Power supply input VBAT

5.1.9.1 Functional Class “Bus Driver Voltage Regulator Control”

• This functional class groups the following optional features, that must all be
implemented, if one of them is present in the IUT:
• BD mode BD_Sleep
• Signal INH1
• Signal WAKE
• Signal CTRL2
• Power supply input VBAT
5.1.9.2 Functional Class “Bus Driver – Bus Guardian Control Interface”


• Signal BGE
• Signal RxEN
5.1.9.3 Functional Class “Bus Driver Internal Voltage Regulator”

• This functional class comprises the implementation of a “VBAT” power
supply input and requires that the BD is fully operational without a VCC
supply.
5.1.9.4 Functional Class “Bus Driver Logic Level Adaptation”

• This functional class comprises the implementation of a “VIO” power supply
input and requires that the thresholds of all digital inputs can be controlled
by this voltage as well as all digital outputs are related to this voltage level.
5.1.10 Definition of Communication and Control
5.1.10.1 Communication
Matrix A (round robin test):
In some test cases it is necessary that every node within the specified topology is the
transmitter. That means that the test case starts with node 1 as transmitter and the
other nodes transmit one after another (all other nodes are receivers).
This matrix is used for observation of digital signals.

Message from Node x
Transmitters 1 2 11 12 13 14 21 22 23 24
Receivers all*) all*) all*) all*) all*) all*) all*) all*) all*) all*)
t
*) except the transmitting node
Figure 5-21: Communication Matrix A

Pause between the messages17: 20µs.
Node 11 as transmitter:

In some test instances node 11 is the transmitter and node 12 that is observed by
the oscilloscope is the receiver.
Message from Node
Transmitter 11
t
Receiver 12
Figure 5-22: Communication with Node 11 as Transmitter (Time Diagram)
17
A message is the whole test pattern (wake-up, TSS and data signal) which is sent by the transmitter
and received by the receivers. See also chapter 5.1.2.7.

11
Tr
an
PS 2 AS 4
sm
itt
3
er
24 23 22 21 2 14 13 12 11
Point of Observation

Figure 5-23: Communication with Node 11 as Transmitter (Topology)
In some test instances node 12 is the transmitter and node 23 that is observed by
the oscilloscope is the receiver.
Message from Node
Transmitter 12
t
Receiver 23

11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Point of Observation Transmitter

In some test instances node 1 is the transmitter and node 2 that is observed by the
oscilloscope is the receiver.
Message from Node
Transmitter 1
t
Receiver 2

Transmitter 1
11
PS 2 AS 4
24 23 22 21 2 14 13 12 11

In this communication node 23 is the transmitter and observed by the oscilloscope.
Message from Node
Transmitter 23
11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Transmitter Point of Observation

In this communication node 24 is the transmitter and node 23 is observed by the
oscilloscope.
Message from Node
Transmitter 24
t
Receiver 23

t
11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Node 24 and 23 as transmitter:

In this communication node 24 and 23 are the transmitters with scope observation of
the bus at node 23 and logic analyzer observation of both nodes.

Message from Node
Transmitter 23 24
t
Receiver 24 23
Figure 5-32: Communication with Node 24 as observed Transmitter (Time

Diagram)

1
11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Transmitter
Figure 5-33: Communication with Node 24 as observed Transmitter (Topology)
Node 24 and 1 as transmitter:

In this communication node 24 and node 1 are the transmitters and all IUTs are
observed by the logic analyzer.

Message from Nodes
Transmitters 24 1
Figure 5-34: Communication with Node 24 and 1 as Transmitter (Time Diagram)
Transmitter 1

11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Figure 5-35: Communication with Node 24 and 1 as Transmitter (Topology)
5.1.10.2 Control
Host Command:
Wait 1000µs after a host command to the IUT before performing the next step in the
test execution. In that case the IUT is able to switch from one mode to the other.
The commanded nodes and the observed nodes are specified in the test cases.

11
PS 2 AS 4
24 23 22 21 2 14 13 12 11

Host Command to the Nodes 1, 2, 11-14 and 21-24
Figure 5-36: Host Command to IUTs
5.1.11 Standard Preamble

1. Switch on power supplies and initialize them according to the values defined
for each test case in the configuration.
2. Set ground shift and initialize it according to the values defined for each test
case in the configuration.
3. Set failure and initialize it according to the values defined for each test case in
the configuration.
4. Wait for 500ms in order to have a stable failure condition.
5. TxEN and TxD shall be in logical HIGH (idle) state.
6. In case of a BGE signal this signal shall be in logical HIGH state.
7. In case of a VIO signal this voltage shall be supplied by the voltage used in
the implementation of the conformance test.
8. In case of a WAKE pin this signal shall be in logical HIGH state.
9. Stimulate all IUTs via host interface to enter BD_Normal.
10. Make sure that the active star is in AS_Normal mode when this preamble is
left and the test execution is entered, e.g. by switching on the power supply of
the active star just before the end of the preamble.
5.1.12 Standby Preamble


the configuration.

9. Stimulate all IUTs via host interface to enter BD_Standby.
5.1.13 Sleep Preamble

The sleep preamble will only be used if the IUT has the functional class “BD voltage
regulator control” (BD_Sleep mode) implemented. The hosts of all nodes except
node 24 will be switched off. The needed host command will be product specific.
the configuration.
9. Stimulate all IUTs via host interface to enter BD_Sleep.

5.1.14 ReceiveOnly Preamble

The ReceiveOnly preamble will only be used if the IUT has the BD_ReceiveOnly
mode implemented. The needed host command will be product specific.
the configuration.

9. Stimulate all IUTs via host interface to enter BD_ReceiveOnly.
5.1.15 Standard Postamble

1. Set ground shift to 0V.
2. Set to faultless configuration (reset failures).
3. Switch off power supplies.
5.1.16 Receiver Masks

The path asymmetry is a very important parameter for the decoding of FlexRay
signals. Each component in the physical layer may cause asymmetries, transmitters,
active stars, receivers, but also passive network segments as passive busses or
stars, connectors, ESD protection, etc. As a consequence, is is not enough to just
sum up the allowed asymmetries for transmitters, receivers and active stars. These
parameters are verified seperately. The complete physical layer including the whole
signal path may cause a path asymmetry as defined in chapter 12.3 in [01-PL Spec].
For a sequence of 10 bits logical LOW the allowed path asymmetry is:
Signal path asymmetry including jitter: -30.75 / +43.23 ns

Hint: The accuracy/resolution of the logic analyzer as described in chapter 2.5.9

must be taken into account. The sequence of 10 bit logical LOW must be enclosed
by logical HIGH sequences, i.e. the bus shall change from Data_1 to 10 bit times
Data_0 and back to Data_1.
The asymmetric channel delays are independent from the propagation delay.
5.1.17 Services
In this section, all required services are specified on measurement device or
generator. Each device (oscilloscope, logic analyzer, pattern generator, power
supply, etc.) requires own, dedicated services.

5.1.17.1 Oscilloscope Services
The oscilloscope requires services to configure the scope, to start acquisition and to
obtain specific parameters from the acquired data. The oscilloscope observes bus
and logic signals and is part of the upper tester as well as the lower tester.
Scope
IConfiguration
Configure
Acquisition
Channel
Trigger
IAcquireBusData
Initiate
GetWaveform
ObtainParameter
Figure 5-37: Oscilloscope Services
5.1.17.1.1 Services of the IConfiguration Interface

• Configure scope with standard configuration properties: Acquisition related
properties like type and sample rate, channel specific properties like probe
attenuation, input impedance, maximal input frequency and coupling as

well as trigger specific properties like trigger edge and coupling:

Configure(ConfigurationSet)
• Configure scopes acquisition behaviour:
Acquisition(MimimalNumberOfPoints, StartOffset,
AcquisitionLength)
• Configure scopes channels:
Channel(ChannelID, Range, Offset)
• Configure scopes trigger event:
Trigger(Source, Level, Slope)
5.1.17.1.2 Services of the IAcquisition Interface

• Put scope from idle into ready state. Scope will wait for trigger event
immediately after this command. Acquisition is enabled for selected

channels:
Initiate(ChannelList)
• To store acquired data of selected channels into storage structure for
obtaining parameter:
GetWaveform(ChannelList, WaveformArray)
• Obtain specific parameter from acquired data. The parameter to extract is
selectable:
ObtainParameter(ChannelList, WaveformArray, Vio,
DesiredParameter)
5.1.17.2 Pattern Generator Services

The pattern generator requires services to get configured and to prepare and upload
defined pattern sequences to the pattern generator.
PatternGenerator
IPatternGenerator
Configure
CreateComposedPattern
CreateParticularPattern
UnsetBGE
Figure 5-38: Pattern Generator Services
5.1.17.2.1 Services of the IPatternGenerator Interface

• Configure the pattern generator, including PODs, default outputs, clock
resolution, triggers, etc.:
Configure()
• Create pattern sequence by using one method:

o Create a composed pattern sequence with specific communication

matrix, patterns, selectable wake-up nodes, etc.:
CreateComposedPattern(BitDuration, Matrix, WakeupNodes,
Patterns, IdleTime, RepeatPatternSequence, WaitForTrigger)
or
o Create a composed particular pattern sequence when special
sequences like babbling idiot are required:
CreateParticularPattern(BitDuration, WakeupNodes,
SpecialPatterns, WaitForTrigger)
• Set BGE input of specific nodes to logical LOW state for a defined period.
If this method is unused, all BGE inputs have to be set to logical HIGH. If
Offset is set to zero, the selected BGE signals are logical LOW

immediately after starting the test execution:
UnsetBGE(StateDuration, SelectedNodes, Offset)
5.1.17.3 Logic Analyzer Services

The logic analyzer requires a service to get configured.
LogicAnalyzer
ILogicAnalyzer
Configure
Figure 5-39: Logic Analyzer Services
5.1.17.3.1 Services of the ILogicAnalyzer Interface

• Configure the logic analyzer to acquire selected signals with given sample
rate, thresholds and acquisition depth:
Configure(SignalDesignators, SampleRate, Thresholds,
AcquisitionDepth)
5.1.17.4 Logic Analysis System Services

The logic analyzer requires a service to execute a test.
LogicAnalysisSystem
ILogicAnalysisSystem
ExecuteLogicTest
Figure 5-40: Logic Analysis System Services
5.1.17.4.1 Services of the ILogicAnalysisSystem Interface

• Execute a test case. Preconditions to execute a logic test case are

ILogicAnalyzer.Configure, IPatternGenerator.Configure,
IPatternGenerator.CreateComposedPattern or
IPatterGenerator.CreateParticularPattern and optionally
IPatternGenerator.UnsetBGE:
ExecuteLogicTest()
5.1.17.5 Power Supply Services

Power supplies are required for providing the battery voltage, Vcc, Vio and Ground
Shift to the standard net. Additionally, the power supply for emulating the battery
must be able to simulate a battery voltage breakdown which is commonly caused by
the starter circuit.

PowerSupply
IBatterySupplyConfig
Output
DynamicLowBattery
OutputEnable
InitiateArbitraryFunction
IDCPowerSupplyConfig
Output
OutputEnable
Figure 5-41: Power Supply Services
5.1.17.5.1 Services of the IBatterySupplyConfig Interface

• Set output voltage and current limitation of battery power supply:
Output(Voltage, CurrentLimit)
• Configure emulation of battery voltage breakdown by battery power supply.
The pulse shape and the pulse offset from a following trigger event have to
be selected. The power supply will set up the voltage of the first pulse
shape point on its outputs when enabled. The pulse start requires a trigger
(software/hardware). A pulse may be repeated:
DynamicLowBattery(Pulseform, PulseOffset, Repetitions)
• Enable or disable power supply output:
OutputEnable(Enabled)

• Trigger the output of the predefined pulse immediately or enable hardware

trigger input:
InitiateArbitraryFunction(WaitForTrigger)
5.1.17.5.2 Services of the IDCPowerSupplyConfig Interface

• Set output voltage and current limitation of DC power supply. Multi-channel
power supplies are supported:
Output(Channel, Voltage, CurrentLimit)
• Enable or disable power supply output:
OutputEnable(Enabled)
5.1.17.6 Network Services

Multiple switching and control services are required for setting up power supply

connections, short circuits, interruptions and to set and get the bus driver states or
cause local wake-up events.
NetServices
ISwitch
SetShortCircuitBusWire
SetShortCircuitOnBoard
SetGroundShift
SetInterruptionBusWire
SetInterruptionOnBoard
SetTermination
SetSupplyConfiguration
ResetNet
IControl
SetOperatingMode
SendLocalWakeup
GetIUTStatus
Figure 5-42: Network Services

5.1.17.6.1 Services of the ISwitch Interface

• To set up or reset a short circuit of bus wire lines (BM, BP) with each other
or one of both bus wire lines with VBAT, VCC or GND:
SetShortCircuitBusWire(Line1, Line2, Enable)
• To set up or reset a short circuit of digital input lines (TxEN or TxD with
GND, BGE with VIO or VCC) of the IUT within selected nodes:
SetShortCircuitOnBoard(SelectedNodes, Line1, Line2,
Enable)
• To set up or reset a ground shift in selected nodes. A selected node is
always shifted by +5V:
SetGroundShift(SelectedNodes, Enable)
• To set up or reset an interruption of bus lines (BP, BM) of selected nodes:
SetInterruptionBusWire(SelectedNodes, Lines, Enable)

• To set up or reset an interruption of digital inputs or supply lines (TxD,
TxEN, STBN, BGE, WAKE, VBAT, VCC, VIO or GND) of the IUT within
selected nodes:
SetInterruptionOnBoard(SelectedNodes, Lines, Enable)
• To set up a selected termination in selected nodes:
SetTermination(SelectedNodes, TerminationType, Enable)
• To set up a specific power supply configuration of selected nodes:
SetSupplyConfiguration(SelectedNodes,
SuppliesConfiguration)
• To reset all failures (short circuits, interruptions) and abnormal conditions
(ground shift, specific power supply) in all nodes:
ResetNet()
5.1.17.6.2 Services of the IControl Interface

• To set up a specific operating mode in selected nodes:
SetOperatingMode(SelectedNodes, OperationalMode)
• To cause a local wake-up event in selected nodes:
SendLocalWakeup(SelectedNodes, WakeupEvent)
• To acquire the status of the IUT of selected nodes:
GetIUTStatus(SelectedNodes)


The motivation of static test cases is to check the availability and the boundaries in
the data sheet of the IUT (topology independent).
Every parameter must be part of the data sheet and fulfill the specified boundaries. If
at least one parameter does not pass this test, the result of the whole conformance
test is failed.
Index Parameter SOVS Brace Description Min Max Unit
1. dRxAsym Communication. Receiver delay 5 ns

Delay mismatch

2. dBDRx10 Communication. Receiver delay, 100 ns
Delay negative edge
3. dBDRx01 Communication. Receiver delay, 100 ns

Delay positive edge
4. dBDRxai Communication. Idle reaction time 50 400 ns

Timing
5. dBDRxia Communication. Activity reaction time 100 450 ns

Timing
6. dTxAsym Communication. Transmitter delay 4 ns

Delay mismatch
7. dBDTx10 Communication. Transmitter delay, 100 ns

Delay negative edge
8. dBDTx01 Communication. Transmitter delay, 100 ns

Delay positive edge
9. dBDTxai Communication. Propagation delay 100 ns

Timing active idle
10. dBDTxia Communication. Propagation delay 100 ns

Timing idle active
11. dBusTxai Communication. Transition time 30 ns

Signal Shape active idle
12. dBusTxia Communication. Transition time 30 ns

Signal Shape idle active
18
13. dBusTx01 Communication. Rise time differential 5 25 ns
Signal Shape voltage
(10% 90%)
18
Load on BP/BM: 45Ω || 100pF

14. dBusTx10 18 Communication. Fall time differential 5 25 ns

(90% 10%)
15. uBDTxactive 19 Communication. Absolute differential 600 2000 mV

Signal Shape voltage while sending
16. uBDTxidle 19 Communication. Absolute differential 0 30 mV

Signal Shape voltage while Idle
17. uVDIG-OUT-HIGH Communication. Output voltage on a 0.8xuVDIG 20 1.0xuVDIG 20 -

Threshold digital ouput, when in
logical high state

18. uVDIG-OUT-LOW Communication. Output voltage on a 0.2xuVDIG 20 -
Threshold digital ouput, when in
logical low state
19. uVDIG-IN-HIGH Communication. Threshold for 0.7xuVDIG 20 -

Threshold detecting a digital
input as on logical
high
20
20. uVDIG-IN-LOW Communication. Threshold for 0.3xuVDIG -
input as on logical low
21. uBusActiveHigh Communication. Upper receiver 150 425 mV

Threshold threshold for
detecting activity
22. uBusActiveLow Communication. Lower receiver -425 -150 mV

Threshold threshold for
detecting activity
23. uData_0 Communication. Receiver threshold for -30021 -15021 mV

Threshold detecting Data_0
21 21
24. uData_1 Communication. Receiver threshold for 150 300 mV
Threshold detecting Data_1
21
25. ∆uData Communication. Mismatch of receiver 10 %
Threshold thresholds
26. dActivity Communication. Allowed time for 100 300 ns

Detection Timing receiver to detect bus
activity
19
20
In case a reference voltage for digital IO is available via a VIO pin, then uVDIG = uVIO, otherwise
uVDIG = uVCC
21
Take into account the footnotes of the electrical physical layer specification for this parameter

27. dIdleDetection Communication. Allowed time for 50 250 ns

Timing receiver to detect bus
Idle
28. RCM1, RCM2 Environment Common mode input 10 40 kΩ

resistance
29. uCM Environment. Common mode -10 +15 V

Ground Shift voltage range
30. SPI interface Environment Characteristics of the 0.01 1 Mbit/s

optional SPI bus
driver to host
interface

31. iBMGNDShortMax Failure. Maximum output 100 mA
Short circuit.BM current when shorted
to GND
32. iBPGNDShortMax Failure. Maximum output 100 mA

Short circuit.BP current when shorted
to GND
33. iBPBAT48ShortMax Failure. Maximum output 120 mA

Short circuit.BP current when shorted
to VBAT =48V
34. iBMBAT48ShortMax Failure. Maximum output 120 mA

Short circuit.BM current when shorted
to VBAT =48V
35. uBias – Mode. Voltage @ BP & BM 1800 3200 mV

BD_Normal 22 Bus Driver. during bus state Idle
Normal
36. uBias – Mode. Voltage @ BP & BM -200 +200 mV

Low Power 22 Bus Driver. during bus state
Low Power Idle_LP
37. dWakePulse Mode. Duration of a valid 1 500 µs

Bus Driver. wake pulse @ local
Low Power. WAKE pin
Wake-up
38. dWU0Detect Mode. Time for detection of 1 4 µs

Bus Driver. a Data_0 phase in
Low Power. WU pattern
Wake-up
22

39. dWUIdleDetect Mode. Time for detection of 1 4 µs

Bus Driver. a Idle phase in WU
Low Power. pattern
Wake-up
40. dWUTimeout Mode. Acceptance timeout 48 140 µs

Bus Driver. for WU pattern
Low Power. recognition
Wake-up
41. VBAT for Power Supply Battery voltage 7 V

WU detector required for wake-up
detector operation

42. VBAT monitoring Power Supply Transition to low 2 5.5 V
power when voltage
falls below product
specific threshold
43. VCC monitoring Power Supply Transition to low 2 Product V

power when voltage specific
falls below product
specific threshold
44. dUV Power Supply Reaction time for 1000 ms

undervoltage
detection
45. iBPLeak Mode. Leakage current 25 µA

Bus Driver. when all supplies are
Off.iBPLeak switched off
46. iBMLeak Mode. Leakage current 25 µA

Bus Driver. when all supplies are
Off.iBMLeak switched off
47. Functional Functional Class Checks the complete - -

Class implementation of all
”BD voltage specified options
regulator
control”
”Bus Driver – specified options
Bus Guardian
control
interface”
”Bus Driver specified options
internal voltage
regulator”


”Bus Driver specified options
logic level
adaptation”
Table 5-4: Static Test Cases

5.3 Test Cases
5.3.1 Communication.Delay.dBDTx01
5.3.1.1 Standard environment, Ground Shift = 0, Power Supply =

Standard, Failure = 0
5.3.1.1.1 Test Purpose

This test checks the transmitter delay dBDTx01 from low to high according to figure
8-8 in [01-PL Spec] while no stress condition is present.

5.3.1.1.2 Configuration
• Topology: as specified in previous configuration section 5.1.
• In case that only VCC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that VBAT and VCC are both implemented:
o VBAT power supply of all nodes: default.
• In case that only VBAT is implemented:
• VIO power supply of all nodes (in case of an available VIO supply input):
depends on implementation.
• Ground shift: 0V.
• Failure: none.
• Communication: node 23 as transmitter.
5.3.1.1.3 Preamble (setup state)

• Standard preamble.
5.3.1.1.4 Test execution

• Observe and acquire uTxD at TP_N23_TxD of node 23 according to the
observation window described in chapter 5.1.4.1.
• Observe and acquire uBus at TP1_N23 of node 23 according to the
• Observe and acquire the error signal of the host interface (TP_N23_ERRN
or TP_N23_INTN) of node 23.
• In case of an available INH1 signal observe and acquire uINH1 at
TP_N23_INH1 of node 23.

• Stimulate IUT of node 23 at TP_N23_TxD and TP_N23_TxEN by one

wake-up pattern, followed by one TSS pattern, followed by one 50/50
pattern.
5.3.1.1.5 Postamble
• Standard postamble.
5.3.1.1.6 Pass- / Fail Criteria

Pass criteria:
• dBDTx01 ≤ 100ns.
• no error shall be signaled via the host interface.
• in case of an available INH1 signal uINH1 shall be in logical HIGH state

during test execution.

5.3.1.2 Standard environment, Ground Shift = active @ transmitter,

Power Supply = Standard, Failure = 0

8-8 in [01-PL Spec] while ground shift at the transmitter is present.

• Ground shift: +5V @ node 23 located according to the Figure 3-2.
• Failure: none.


pattern.
5.3.1.2.5 Postamble


Pass criteria:
• dBDTx01 ≤ 100ns.

5.3.1.3 Standard environment, Ground Shift = active @ receiver, Power

Supply = Standard, Failure = 0

8-8 in [01-PL Spec] while ground shift at the receiver is present.

• Failure: none.


pattern.
5.3.1.3.5 Postamble


Pass criteria:
• dBDTx01 ≤ 100ns.

5.3.1.4 Standard environment, Ground Shift = 0, Power Supply = Low

Bat, Failure = 0

8-8 in [01-PL Spec] while low battery voltage is present.
This test case is skipped if the Functional Class “Bus Driver Voltage Regulator
Control” is not implemented.

o VBAT power supply of all nodes: +5.5V.
• Failure: none.


• Observe and acquire uINH1 at TP_N23_INH1 of node 23.
pattern.
5.3.1.4.5 Postamble

Pass criteria:
• dBDTx01 ≤ 100ns.
• uINH1 shall be in logical HIGH state during test execution.


Standard, Failure = Min Bus Load

8-8 in [01-PL Spec] while minimal bus load is present.

• Failure: minimum bus load as specified in FL7.

• Switch bus load at node 23 to the minimum value as described in FL7.

pattern.
5.3.1.5.5 Postamble


Pass criteria:
• dBDTx01 ≤ 100ns.


Standard, Failure = Max Bus Load

8-8 in [01-PL Spec] while maximal bus load is present.

• Failure: maximum bus load as specified in FL8.

• Switch bus load at node 23 to the maximum value as described in FL8.

pattern.
5.3.1.6.5 Postamble


Pass criteria:
• dBDTx01 ≤ 100ns.

5.3.2 Communication.Delay.dBDTx10


This test checks the transmitter delay dBDTx10 from high to low according to figure

• Failure: none.


pattern.
5.3.2.1.5 Postamble


Pass criteria:
• dBDTx10 ≤ 100ns.



8-8 in [01-PL Spec] while ground shift at the transmitter is present.

• Failure: none.


pattern.
5.3.2.2.5 Postamble


Pass criteria:
• dBDTx10 ≤ 100ns.



8-8 in [01-PL Spec] while ground shift at the receiver is present.

• Failure: none.


pattern.
5.3.2.3.5 Postamble


Pass criteria:
• dBDTx10 ≤ 100ns.


Bat, Failure = 0


• Failure: none.


pattern.
5.3.2.4.5 Postamble

Pass criteria:
• dBDTx10 ≤ 100ns.






pattern.
5.3.2.5.5 Postamble


Pass criteria:
• dBDTx10 ≤ 100ns.






pattern.
5.3.2.6.5 Postamble


Pass criteria:
• dBDTx10 ≤ 100ns.

5.3.3 Communication.Delay.dTxAsym


This test case calculates the asymmetric transmitter delay that is measured by the
parameters dBDTx01 (chapter 5.3.1.1) and dBDTx10 (chapter 5.3.2.1) according to
figure 8-8 in [01-PL Spec] while no stress condition is present.

• No configuration needed.

• No preamble necessary.

• Calculation of |dBDTx10-dBDTx01| as measured in the test cases above.
5.3.3.1.5 Postamble
• No postamble necessary.

Pass criteria:
• |dBDTx10-dBDTx01| ≤ 4ns.



figure 8-8 in [01-PL Spec] while ground shift at the transmitter is present.


5.3.3.2.5 Postamble

Pass criteria:



figure 8-8 in [01-PL Spec] while ground shift at the receiver is present.


5.3.3.3.5 Postamble

Pass criteria:


Bat, Failure = 0

figure 8-8 in [01-PL Spec] while low battery voltage is present.



5.3.3.4.5 Postamble

Pass criteria:



figure 8-8 in [01-PL Spec] while minimal bus load is present.


5.3.3.5.5 Postamble

Pass criteria:



figure 8-8 in [01-PL Spec] while maximal bus load is present.


5.3.3.6.5 Postamble

Pass criteria:

5.3.4 Communication.Delay.dBDRx01


This test checks the receiver delay dBDRx01 from low to high according to figure 8-6
in [01-PL Spec] while no stress condition is present.

• Failure: none.


• Observe and acquire uRxD at TP_N23_RxD of node 23 according to the
pattern.
5.3.4.1.5 Postamble


Pass criteria:
• dBDRx01 ≤ 100ns.



in [01-PL Spec] while ground shift at the transmitter is present.

• Failure: none.


pattern.
5.3.4.2.5 Postamble


Pass criteria:
• dBDRx01 ≤ 100ns.



in [01-PL Spec] while ground shift at the receiver is present.

• Failure: none.


pattern.
5.3.4.3.5 Postamble


Pass criteria:
• dBDRx01 ≤ 100ns.


Bat, Failure = 0

in [01-PL Spec] while low battery voltage is present.

• Failure: none.


pattern.
5.3.4.4.5 Postamble

Pass criteria:
• dBDRx01 ≤ 100ns.



in [01-PL Spec] while minimal bus load is present.



pattern.
5.3.4.5.5 Postamble


Pass criteria:
• dBDRx01 ≤ 100ns.



in [01-PL Spec] while maximal bus load is present.



pattern.
5.3.4.6.5 Postamble


Pass criteria:
• dBDRx01 ≤ 100ns.

5.3.5 Communication.Delay.dBDRx10


in [01-PL Spec] while no stress condition is present.

• Failure: none.


pattern.
5.3.5.1.5 Postamble


Pass criteria:
• dBDRx10 ≤ 100ns.



in [01-PL Spec] while ground shift at the transmitter is present.

• Failure: none.


pattern.
5.3.5.2.5 Postamble


Pass criteria:
• dBDRx10 ≤ 100ns.



in [01-PL Spec] while ground shift at the receiver is present.

• Failure: none.


pattern.
5.3.5.3.5 Postamble


Pass criteria:
• dBDRx10 ≤ 100ns.


Bat, Failure = 0

in [01-PL Spec] while low battery voltage is present.

• Failure: none.


pattern.
5.3.5.4.5 Postamble

Pass criteria:
• dBDRx10 ≤ 100ns.



in [01-PL Spec] while minimal bus load is present.



pattern.
5.3.5.5.5 Postamble


Pass criteria:
• dBDRx10 ≤ 100ns.



in [01-PL Spec] while maximal bus load is present.



pattern.
5.3.5.6.5 Postamble


Pass criteria:
• dBDRx10 ≤ 100ns.

5.3.6 Communication.Delay.dRxAsym


parameters dBDRx01 (chapter 5.3.4.1) and dBDRx10 (chapter 5.3.5.1) according to
figure 8-6 in [01-PL Spec] while no stress condition is present.



• Calculation of |dBDRx10-dBDRx01|.
5.3.6.1.5 Postamble

Pass criteria:
• |dBDRx10-dBDRx01| ≤ 5ns.



figure 8-6 in [01-PL Spec] while ground shift at the transmitter is present.


5.3.6.2.5 Postamble

Pass criteria:



figure 8-6 in [01-PL Spec] while ground shift at the receiver is present.


5.3.6.3.5 Postamble

Pass criteria:


Bat, Failure = 0

figure 8-6 in [01-PL Spec] while low battery voltage is present.



5.3.6.4.5 Postamble

Pass criteria:



figure 8-6 in [01-PL Spec] while minimal bus load is present.


5.3.6.5.5 Postamble

Pass criteria:



figure 8-6 in [01-PL Spec] while maximal bus load is present.


5.3.6.6.5 Postamble

Pass criteria:

5.3.7 Mode.Bus Driver.Low Power.Standby

Standard, Failure = 0, from BD_Normal

This test checks the ability of the IUT to change from BD_Normal mode to
BD_Standby by host command according to figure 8-2, transition number 10 in [01-
PL Spec] while no stress condition is present.

• Failure: none.
• Communication: node 24 and 23 as transmitter.


• Observe and acquire uTxD at TP_N24_TxD of node 24.
• Observe and acquire uTxEN at TP_N24_TxEN of node 24.
• Observe and acquire uRxD at TP_N24_RxD of node 24.
• In case of an available RxEN signal observe and acquire uRxEN at
TP_N24_RxEN of node 24.

• Stimulate IUT in node 24 via host interface to enter BD_Standby.
• Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit
High pattern.
• Trigger the scope to start observation synchronously with the stimuli at
node 24.
• Wait until end of scope observation window, i.e. 5.0µs.
• Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by two
50/50 patterns.
5.3.7.1.5 Postamble


Pass criteria:
• uBus at TP4_N23 of node 23 shall stay within idle range during the
observation window, beginning with the falling edge of TxEN of node 24.
The absolute bus voltage shall not exceed 30mV (uBDTxidle).
• uRxD of node 24 shall not contain more than one falling edge (bus activity
may be detected as wake-up event), i.e. node 24 shall not receive the
patterns applied to uTxD and uTxEN of node 23.
• in case of an available RxEN signal uRxEN of node 24 shall be in logical
HIGH state before node 23 is stimulated to transmit. After stimulation,
uRxEN may change to logical LOW state (bus activity may be detected as
wake-up event).
• in case of an available INH1 signal uINH1 of node 24 shall be in logical
HIGH state (Not_Sleep) during test execution.
• no error shall be signaled via the host interface of node 24.

5.3.7.2 Standard environment, Ground Shift = active, Power Supply =


PL Spec] while ground shift is present.

• Failure: none.




High pattern.
node 24.
50/50 patterns.
5.3.7.2.5 Postamble

Pass criteria:
wake-up event).


LowBat, Failure = 0, from BD_Normal

PL Spec] while low battery voltage is present.

o VCC power supply of all nodes: +5.0.
• Failure: none.




High pattern.
node 24.
50/50 patterns.
5.3.7.3.5 Postamble
Standard postamble.

Pass criteria:
wake-up event).


Standard, Failure = 0, from BD_Sleep

This test checks the ability of the IUT to change from BD_Sleep mode to
BD_Standby by a remote wake-up according to section 8.11.1 and figure 8-2,
transition 1 in [01-PL Spec] on page 54 while no stress condition is present.

• Failure: none.

• Sleep preamble.
• Stimulate IUT in node 24 via host interface to enter BD_Normal.

• Observe and acquire uINH1 at TP_Nx_INH1 of all nodes except node 24.
• Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 24.
• Observe and acquire the error signal of the host interface (TP_Nx_ERRN
or TP_Nx_INTN) of all nodes.
TP_Nx_RxEN of all nodes except node 24.
wake-up patterns.
5.3.7.4.5 Postamble


Pass criteria:
• uINH1 of all observed nodes shall be in logical LOW state (Sleep) before
the transmission start of the wake-up pattern, i.e. the first falling edge of
uTxD or uTxEN of node 24. After the wake-up event is detected, uINH1 of
all observed nodes shall be in logical HIGH state (Not_Sleep), i.e. the IUTs
are in BD_Standby mode.
• After the wake-up event is detected, uRxD of all observed nodes shall be
in logical LOW state.
• in case of an available RxEN signal uRxEN all observed nodes shall be in

logical LOW state after the wake-up event is detected.
• no error shall be signaled via the host interface of all observed nodes after
the wake-up event is detected.



transition 1 in [01-PL Spec] on page 54 while ground shift is present.

• Failure: none.

• Sleep preamble.

wake-up patterns.
5.3.7.5.5 Postamble


Pass criteria:



LowBat, Failure = 0, from BD_Sleep

transition 1 in [01-PL Spec] on page 54 while low battery voltage is present.

depends on implementation
• Failure: none.

• Sleep preamble.

wake-up patterns.
5.3.7.6.5 Postamble


Pass criteria:




BD_Standby by a local wake-up event according to section 8.11.2 and figure 8-2,

o External VCC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available VIO supply input):
o VIO power supply of all nodes: depends on implementation.
o External VIO power supply of IUT in node 24: depends on
implementation.
• Failure: none.
• Communication: none.

• Sleep preamble.

• Observe and acquire uWAKE at TP_N24_WAKE of node 24.
• Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at
TP_N24_WAKE according to dWakePulse in [01-PL Spec].

5.3.7.7.5 Postamble

Pass criteria:
• uINH1 shall be in logical LOW state (Sleep) while the IUT of node 24 is in
BD_Sleep mode, before the falling edge of uWAKE. After the wake-up
event is detected, uINH1 shall be in logical HIGH state (BD_Standby:
Not_Sleep).
• uRxD of node 24 shall be in logical HIGH state before the falling edge of
uWAKE. After the wake-up event is detected, uRxD of node 24 shall be in
logical LOW state.

HIGH state before the falling edge of uWAKE. After the wake-up event is
detected, uRxEN of node 24 shall be in logical LOW state.




implementation.
• Failure: none.

• Sleep preamble.


5.3.7.8.5 Postamble

Pass criteria:
Not_Sleep).
logical LOW state.





implementation.
• Failure: none.

• Sleep preamble.


5.3.7.9.5 Postamble

Pass criteria:
Not_Sleep).
logical LOW state.




Control” is not implemented or an optional positive pulse by a local wake-up is not
provided by the IUT.

implementation.
• Failure: none.

• Sleep preamble.


• Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at

5.3.7.10.5 Postamble

Pass criteria:
BD_Sleep mode, before the rising edge of uWAKE. After the wake-up
Not_Sleep).

• uRxD of node 24 shall be in logical HIGH state before the rising edge of
logical LOW state.
HIGH state before the rising edge of uWAKE. After the wake-up event is




implementation.
• Failure: none.

• Sleep preamble.




Pass criteria:
Not_Sleep).

logical LOW state.




implementation.
• Failure: none.

• Sleep preamble.




Pass criteria:
Not_Sleep).

logical LOW state.


Standard, Failure = 0, from BD_ReceiveOnly

This test checks the ability of the IUT to change from BD_ReceiveOnly mode to
BD_Standby by host command according to figure 8-2, transition number 5 in [01-PL
Spec] while no stress condition is present.
This test case is skipped if the BD_ReceiveOnly mode is not implemented.

• Failure: none.

• ReceiveOnly preamble.

TP_Nx_INH1 of all nodes except node 24.
• Stimulate IUTs of all nodes except node 24 via host interface to enter
BD_Standby.

• Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one

pattern.

Pass criteria:
Hint: All observed nodes must not receive the transmission of node 24, but they
should detect the transmitted wake-up pattern and bus activity as remote wake-up
event. Thus, uRxD and uRxEN should change from logical HIGH state to logical

LOW state during test execution.
• uRxD of all observed nodes shall not contain more than one falling edge
(remote wake-up detection), i.e. the observed nodes shall not receive the
• no error shall be signaled via the host interfaces of all observed nodes.
• in case of an available INH1 signal uINH1 of all observed nodes shall be in
logical HIGH state (Not_Sleep) during test execution.
• in case of an available RxEN signal uRxEN of all observed nodes shall not
contain more than one falling edge (remote wake-up detection).



Spec] while ground shift is present.

• Failure: none.


BD_Standby.


pattern.

Pass criteria:



LowBat, Failure = 0, from BD_ReceiveOnly

Spec] while low battery voltage is present.
Control” is not implemented or the BD_ReceiveOnly mode is not implemented.

• Failure: none.


BD_Standby.


pattern.

Pass criteria:

• uINH1 of all observed nodes shall be in logical HIGH state (Not_Sleep)


Standard, Failure = 0, from BD_Standby

This test checks the ability of the IUT to change from BD_Standby mode to

• Failure: none.

• Standby preamble.

wake-up patterns.


Pass criteria:
• uRxD of all observed nodes shall be in logical HIGH state before the first
falling edge of uTxD or uTxEN of node 24. After the wake-up event is
detected, uRxD of all observed nodes shall be in logical LOW state.

logical HIGH state before the first falling edge of uTxD or uTxEN of node
24. After the wake-up event is detected, uRxEN of all observed nodes shall
be in logical LOW state.




• Failure: none.


wake-up patterns.


Pass criteria:



LowBat, Failure = 0, from BD_Standby


• Failure: none.


wake-up patterns.


Pass criteria:
• uINH1 of all observed nodes shall be in logical HIGH state (Not_Sleep)





• Failure: none.




Pass criteria:
• uINH1 of node 24 shall be in logical HIGH state (Not_Sleep) during test
execution.
logical LOW state.




• Failure: none.




Pass criteria:
execution.
logical LOW state.




• Failure: none.




Pass criteria:
execution.
logical LOW state.




• Failure: none.




Pass criteria:
execution.
logical LOW state.




• Failure: none.




Pass criteria:
execution.
logical LOW state.




• Failure: none.




Pass criteria:
execution.
logical LOW state.


Standard, Failure = 0, remain in BD_Standby

This test checks the ability of the IUT to reject spikes on the WAKE pin and to stay in
BD_Standby mode if the wake-pulse width is insufficient according to section 8.11.2
in [01-PL Spec] on page 55 while no stress condition is present.

• Failure: none.




Pass criteria:
execution.
• uRxD of node 24 shall be in logical HIGH state during test execution.
HIGH state during test execution.



in [01-PL Spec] on page 55 while ground shift is present.

• Failure: none.




Pass criteria:
execution.


LowBat, Failure = 0, remain in BD_Standby

in [01-PL Spec] on page 55 while low battery voltage is present.

• Failure: none.




Pass criteria:
execution.


Undervoltage VCC, Failure = 0, from BD_Normal

This test checks the fail silent behaviour and the ability of the IUT to change from
BD_Normal mode to BD_Standby in case of an undervoltage on VCC according to
section 8.12 and figure 8-2, transition number 3 in [01-PL Spec] on page 56 while
VBAT is implemented and no other stress condition is present.
In case of a missing VBAT supply input, see test case 5.3.14.1 and skip this test case.

Control” is not implemented or the Functional Class “Bus Driver Internal Voltage
Regulator” is implemented and a VCC supply input is not available.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External VCC power supply of IUT in node 24: +5.0V.
• Failure: none.



• Set external VCC power supply of IUT in node 24 to +2.0V.

• After the detection of the undervoltage condition by the IUT, i.e. after the
falling edge of the error signal of node 24, stimulate IUT in node 24 at
TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern.
TP_N24_TxEN of node 24.
50/50 patterns.

Pass criteria:
Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs supply input has dropped to +2.0V. Adaptation of thresholds
for digital signals may be required.
execution.
• an error shall be signaled via the host interface of node 24 not later than
1000ms after undervoltage is present.
observation window, beginning with the falling edge of uTxEN of node 24.
wake-up event).


Undervoltage VCC, Failure = 0, from BD_Normal

VBAT is implemented and ground shift is present.

• Failure: none.




50/50 patterns.

Pass criteria:
execution.
wake-up event).


Undervoltage VCC & LowBat, Failure = 0, from BD_Normal

VBAT is implemented and low battery voltage is present.

• VBAT power supply of all nodes: +5.5V.
• Failure: none.




50/50 patterns.

Pass criteria:
execution.
wake-up event).


Undervoltage VIO, Failure = 0, from BD_Normal

BD_Normal mode to BD_Standby in case of an undervoltage on VIO according to
section 8.12 and figure 8-2, transition number 3 in [01-PL Spec] on page 56 while no
other stress condition is present.
If the BD_Sleep mode is implemented, see test case 5.3.9.8 and following and skip
this test case.

Control” is implemented or the Functional Class “Bus Driver Logic Level Adaptation”
is not implemented.
• VIO power supply of all nodes: depends on implementation.
• External VIO power supply of IUT in node 24: depends on implementation.
• Failure: none.


• Set external VIO power supply of IUT in node 24 to +0.75V.

50/50 patterns.

Pass criteria:
Hint: Undervoltage detection timeout measurement requires a trigger event when VIO
voltage at the IUTs supply input has dropped to +0.75V. Adaptation of thresholds for
digital signals may be required.
wake-up event).



BD_Normal mode to BD_Standby in case of an undervoltage on VIO according to
ground shift is present.
this test case.

Control” is implemented or the Functional Class “Bus Driver Logic Level Adaptation”
is not implemented.
• Failure: none.



50/50 patterns.

Pass criteria:
wake-up event).


Undervoltage VCC, Failure = 0, from BD_ReceiveOnly

BD_ReceiveOnly mode to BD_Standby in case of an undervoltage on VCC according
to section 8.12 and figure 8-2, transition number 3 in [01-PL Spec] on page 56 while

Control” or the BD_ReceiveOnly mode is not implemented or the Functional Class
“Bus Driver Internal Voltage Regulator” is implemented and a VCC supply input is not
available.
• Failure: none.




50/50 patterns.


Pass criteria:
execution.
wake-up event).


Undervoltage VCC, Failure = 0, from BD_ReceiveOnly


available.
• Failure: none.




50/50 patterns.


Pass criteria:
execution.
wake-up event).


Undervoltage VCC & LowBat, Failure = 0, from BD_ReceiveOnly


available.
• Failure: none.




50/50 patterns.


Pass criteria:
execution.
wake-up event).


Undervoltage VIO, Failure = 0, from BD_ReceiveOnly

BD_ReceiveOnly mode to BD_Standby in case of an undervoltage on VIO according
no other stress condition is present.
this test case.

Control” is implemented or if the Functional Class “Bus Driver Logic Level
Adaptation” or the BD_ReceiveOnly mode is not implemented.
• Failure: none.



50/50 patterns.

Pass criteria:
wake-up event).



BD_ReceiveOnly mode to BD_Standby in case of an undervoltage on VIO according
this test case.

Adaptation” or the BD_ReceiveOnly mode is not implemented.
• Failure: none.



50/50 patterns.

Pass criteria:
wake-up event).


Undervoltage VCC, Failure = 0, from BD_Standby

BD_Standby mode to BD_Standby in case of an undervoltage on VCC according to

• Failure: none.




50/50 patterns.


Pass criteria:
execution.
wake-up event).


Undervoltage VCC, Failure = 0, from BD_Standby


• Failure: none.




50/50 patterns.


Pass criteria:
execution.
wake-up event).


Undervoltage VCC & LowBat, Failure = 0, from BD_Standby


• Failure: none.




50/50 patterns.


Pass criteria:
execution.
wake-up event).


Undervoltage VIO, Failure = 0, from BD_Standby

BD_Standby mode to BD_Standby in case of an undervoltage on VIO according to
this test case.

Adaptation” is not implemented.
• Failure: none.



50/50 patterns.

Pass criteria:
wake-up event).



BD_Standby mode to BD_Standby in case of an undervoltage on VIO according to
this test case.

Adaptation” is not implemented.
• Failure: none.



50/50 patterns.

Pass criteria:
wake-up event).


Standard, Failure = 0, Power_On

This test checks the behaviour and the ability of the IUT to enter BD_Standby in
case of an power on wake-up event according to section 8.11.4 in [01-PL Spec]
while no stress condition is present.

o External VBAT power supply of IUT in node 24: default.
• In case of an available VIO supply input:
implementation.
• Failure: none.

• Disable outputs of external power supplies of IUT in node 24.
• If host interface option A is implemented:
o Switch STBN signal of node 24 and all available mode control
signals (CTRLx) to unconnected. This is to make the IUTs state
independent from a host command.
• If host interface option B is implemented:
o Do not send any host command to the IUT during test execution.



• Enable outputs of external power supplies of IUT in node 24.
• After the detection of the power on wake-up event by the IUT, i.e. after the
rising edge of the error signal of node 24, stimulate IUT in node 24 at
50/50 patterns.

Pass criteria:
Hint: Power on wake-up detection timeout measurement requires a trigger event
when voltages at the IUTs supply inputs have raised to sufficient values. Adaptation
of thresholds for digital signals may be required.
• the error signal of the host interface of node 24 shall be in logical LOW
state before the power supply outputs of the IUT in node 24 are enabled.
After the detection of the power on wake-up event, the error signal shall
change to logical HIGH state. Subsequently, no error shall be signaled via
the host interface of node 24.

LOW state (zero volts) before the power supply outputs of the IUT in node
24 are enabled. After detection of the power on wake-up event, uINH1
shall change to logical HIGH state.
wake-up event).


Standard, Failure = 0, Power_On

while ground shift is present.

implementation.
• Failure: none.




50/50 patterns.

Pass criteria:

LOW state (zero volts) before the power supply outputs of the IUT in node
24 are enabled. After detection of the power on wake-up event, uINH1
shall change to logical HIGH state.
wake-up event).


LowBat, Failure = 0, Power_On

while low battery voltage is present.

o External VBAT power supply of IUT in node 24: +5.5V.
o VCC power supply of IUT in node 24: +5.0V.
o External VBAT power supply of IUT in node 24: +5.5V.
o VIO power supply of IUT in node 24: depends on implementation.
• Failure: none.




50/50 patterns.

Pass criteria:

• uINH1 of node 24 shall be in logical LOW state (zero volts) before the
power supply outputs of the IUT in node 24 are enabled. After detection of
the power on wake-up event, uINH1 shall change to logical HIGH state.
wake-up event).



This test checks the ability of the IUT to ignore non suitable remote wake-up patterns
with shorted idle phase and to remain in BD_Standby mode according to section
8.11.1 in [01-PL Spec] on page 54 while no stress condition is present.

• In case that VIO is implemented:
• Failure: none.
• Communication: Node 23 as transmitter.


• Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one non
wake-up short idle phase pattern as specified in chapter 5.1.3.10.


Pass criteria:
Hint: the observation shall be at least 100ms, because the IUT may wake-up within
this time.
execution, i.e. node 24 shall remain in BD_Standby.




with shorted low phase and to remain in BD_Standby mode according to section

• Failure: none.


wake-up short low phase pattern as specified in chapter 5.1.3.11.


Pass criteria:
this time.




This test checks the ability of the IUT to ignore non suitable prolonged remote wake-
up patterns and to remain in BD_Standby mode according to section 8.11.1 in [01-
PL Spec] on page 54 while no stress condition is present.

• Failure: none.


wake-up prolonged pattern as specified in chapter 5.1.3.12.


Pass criteria:
this time.


5.3.8 Mode.Bus Driver.Normal


BD_Normal by host command according to figure 8-2, transition number 11 in [01-PL

• Failure: none.
• Communication: matrix A (round robin test).


• Observe and acquire uTxD at TP_Nx_TxD of all nodes.
• Observe and acquire uTxEN at TP_Nx_TxEN of all nodes.
• Observe and acquire uRxD at TP_Nx_RxD of all nodes.
TP_Nx_INH1 of all nodes.
TP_Nx_RxEN of all nodes.
• Stimulate IUTs in all nodes via host interface to enter BD_Normal.

• Stimulate IUT in the first transmitting node according to the sequence

described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one wake-up
pattern.
• Stimulate IUTs of transmitting nodes according to the sequence described
on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern,
followed by one 50/50 pattern.
5.3.8.1.5 Postamble

Pass criteria:

• uRxD of all nodes shall contain all 50/50 patterns transmitted at uTxD and
uTxEN of all nodes except the patterns transmitted by the specific node
itself, i.e. all transmitted data shall be received by all receiving nodes
(loopback functionality not mandatory).
• in case of an available INH1 signal uINH1 of all nodes shall be in logical
• in case of an available RxEN signal uRxEN of all nodes shall be in logical
HIGH state before the first node according to the sequence described on
matrix A is stimulated (falling edge of uTxD and uTxEN) and shall be in
logical LOW state while uRxD of the corresponding node signals the
received patterns.
• no error shall be signaled via the host interfaces of all nodes.




• Failure: none.


pattern.


5.3.8.2.5 Postamble

Pass criteria:

received patterns.


Bat, Failure = 0, from BD_Standby


• Failure: none.


• Observe and acquire uINH1 at TP_Nx_INH1 of all nodes.
pattern.


5.3.8.3.5 Postamble

Pass criteria:

• uINH1 of all nodes shall be in logical HIGH state (Not_Sleep) during test
execution.
received patterns.



This test checks the ability of the IUT to change from BD_Sleep mode to BD_Normal
by host command according to figure 8-2, transition number 8 in [01-PL Spec] while
no stress condition is present.

implementation.
• Failure: none.
• Communication: node 24 and node 1 as transmitter.

• Stimulate IUT in node 24 via host interface to enter BD_Sleep.

• Observe and acquire uSTBN or uSCSN at TP_N24_STBN or
TP_N24_SCSN of node 24.


pattern.
• Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS
pattern, followed by one 50/50 pattern.
5.3.8.4.5 Postamble
•

Standard postamble.

Pass criteria:
• uRxD of node 24 shall be in logical HIGH state before this node is
stimulated to transmit, i.e. until the first falling edge of uTxD and uTxEN of
node 24.
uTxEN of node 24 and node 1 except the patterns transmitted by the
specific node itself, i.e. all transmitted data shall be received by all
receiving nodes (loopback functionality not mandatory).
• uINH1 of node 24 shall be in logical LOW state (Sleep) before this node is
stimulated via host interface (rising edge of uSTBN or falling edge of
uSCSN) to enter BD_Normal. After the wake-up event is detected, uINH1
of node 24 shall be in logical HIGH state (Not_Sleep).
HIGH state before this node is stimulated to transmit, i.e. until the first
falling edge of uTxD and uTxEN of node 24. Then, uRxEN of node 24 shall
be in logical LOW state while uRxD of node 24 signals the received
patterns.




implementation.
• Failure: none.




pattern.
5.3.8.5.5 Postamble
•

Standard postamble.

Pass criteria:
node 24.
patterns.



low battery voltage is present.

implementation.
• Failure: none.




pattern.
5.3.8.6.5 Postamble
•

Standard postamble.

Pass criteria:
node 24.
patterns.



•

Topology: as specified in previous configuration section 5.1.
• Failure: none.




pattern.
• Stimulate IUTs in transmitting nodes according to the sequence described
5.3.8.7.5 Postamble

Pass criteria:

received patterns.



•

• Failure: none.




pattern.
5.3.8.8.5 Postamble

Pass criteria:

received patterns.


LowBat, Failure = 0, from BD_ReceiveOnly

Control” is not implemented or the BD_ReceiveOnly mode is not implemented.

• Failure: none.


pattern.


5.3.8.9.5 Postamble

Pass criteria:

execution.
received patterns.

5.3.9 Mode.Bus Driver.Low Power.Sleep


This test checks the ability of the IUT to change from BD_Normal mode to BD_Sleep

implementation.
• Failure: none.


• Observe and acquire uSTBN or uSCSN at TP_Nx_STBN or TP_Nx_SCSN
of all nodes.


• Stimulate IUTs in all nodes via host interface to enter BD_Sleep.
5.3.9.1.5 Postamble

Pass criteria:
• uINH1 of all nodes shall be in logical HIGH state (Not_Sleep) before this
node is stimulated via host interface (falling edge at uSTBN or at uSCSN)
to enter BD_Sleep mode. After stimulation, uINH1 shall change to logical

LOW state (Sleep).




implementation.
• Failure: none.


of all nodes.

5.3.9.2.5 Postamble

Pass criteria:
LOW state (Sleep).





implementation.
• Failure: none.


of all nodes.

5.3.9.3.5 Postamble

Pass criteria:
LOW state (Sleep).



Undervoltage VBAT, Failure = 0, from BD_Normal

BD_Normal mode to BD_Sleep in case of an undervoltage on VBAT according to
VCC is implemented and no other stress condition is present.
In case of a missing VCC supply input, see test case 5.3.13.1 and skip this test case.

• VBAT and VCC supplies:
implementation.
• Failure: none.



• Set external VBAT power supply of the IUT in node 24 to +2.0V.
5.3.9.4.5 Postamble
•

Standard postamble.

Pass criteria:
VBAT voltage at the IUTs supply input has dropped to +2.0V. Adaptation of thresholds
• uINH1 of node 24 shall be in logical HIGH state (Not_Sleep) before VBAT of
the IUT in node 24 is set to undervoltage. uINH1 shall be in logical LOW
state (Sleep) not later than 1000ms after undervoltage is present.


Undervoltage VBAT, Failure = 0, from BD_Normal

BD_Normal mode to BD_Sleep in case of an undervoltage on VBAT according to
VCC is implemented and ground shift is present.

implementation.
• Failure: none.



5.3.9.5.5 Postamble
•

Standard postamble.

Pass criteria:


Undervoltage VBAT, Failure = 0, from BD_ReceiveOnly

BD_ReceiveOnly mode to BD_Sleep in case of an undervoltage on VBAT according

available.
implementation.
• Failure: none.



5.3.9.6.5 Postamble
•

Standard postamble.

Pass criteria:


Undervoltage VBAT, Failure = 0, from BD_ReceiveOnly

BD_ReceiveOnly mode to BD_Sleep in case of an undervoltage on VBAT according

available.
implementation.
• Failure: none.



5.3.9.7.5 Postamble
•

Standard postamble.

Pass criteria:



BD_Normal mode to BD_Sleep in case of an undervoltage on VIO according to
If the BD_Sleep mode is not implemented, see test case 5.3.7.31 and following and
skip this test case.

Control” or the Functional Class “Bus Driver Logic Level Adaptation” is not
implemented.
• Failure: none.



5.3.9.8.5 Postamble
•

Standard postamble.

Pass criteria:
• uINH1 of node 24 shall be in logical HIGH state (Not_Sleep) before VIO of




implemented.
• Failure: none.



5.3.9.9.5 Postamble
•

Standard postamble.

Pass criteria:


Undervoltage VIO & LowBat, Failure = 0, from BD_Normal


implemented.
• Failure: none.



•

Standard postamble.

Pass criteria:



BD_ReceiveOnly mode to BD_Sleep in case of an undervoltage on VIO according to

Control” or the Functional Class “Bus Driver Logic Level Adaptation” or the
BD_ReceiveOnly mode is not implemented.
• Failure: none.



•

Standard postamble.

Pass criteria:




• Failure: none.



•

Standard postamble.

Pass criteria:


Undervoltage VIO & LowBat, Failure = 0, from BD_ReceiveOnly


• Failure: none.



•

Standard postamble.

Pass criteria:



BD_Sleep by host command according to figure 8-2, transition number 12 in [01-PL

implementation.
• Failure: none.


of all nodes.


Pass criteria:
LOW state (Sleep).

• no error shall be signaled via the host interfaces of node 24.




implementation.
• Failure: none.


of all nodes.


Pass criteria:
LOW state (Sleep).





implementation.
• Failure: none.


of all nodes.


Pass criteria:
LOW state (Sleep).



Undervoltage VBAT, Failure = 0, from BD_Standby

BD_Standby mode to BD_Sleep in case of an undervoltage on VBAT according to

implementation.
• Failure: none.



•

Standard postamble.

Pass criteria:


Undervoltage VBAT, Failure = 0, from BD_Standby

BD_Standby mode to BD_Sleep in case of an undervoltage on VBAT according to

implementation.
• Failure: none.



•

Standard postamble.

Pass criteria:



BD_Standby mode to BD_Sleep in case of an undervoltage on VIO according to
no other stress condition is present.

implemented.
• Failure: none.



•

Standard postamble.

Pass criteria:




implemented.
• Failure: none.



•

Standard postamble.

Pass criteria:


Undervoltage VIO & LowBat, Failure = 0, from BD_Standby


implemented.
• Failure: none.



•

Standard postamble.

Pass criteria:


Standard, Failure = 0, remain in BD_Sleep

BD_Sleep mode if the wake-pulse width is insufficient according to section 8.11.2 in
[01-PL Spec] on page 55 while no stress condition is present.

implementation.
• Failure: none.

• Sleep preamble.



Pass criteria:
• uINH1 shall be in logical LOW state (Sleep) during test execution.



[01-PL Spec] on page 55 while ground shift is present.

implementation.
• Failure: none.

• Sleep preamble.



Pass criteria:


LowBat, Failure = 0, remain in BD_Sleep

[01-PL Spec] on page 55 while low battery voltage is present.

implementation.
• Failure: none.

• Sleep preamble.



Pass criteria:



with shortend idle phase and to remain in BD_Sleep mode according to section

o VCC power supply of all nodes except node 24: +5.0V.
o External VCC power supply of node 24: +5.0V.
o VIO power supply of all nodes except node 24: depends on
implementation.
o External VIO power supply of node 24: depends on implementation.
• Failure: none.





Pass criteria:
this time.
• uINH1 of node 24 shall be in logical LOW state (Sleep) during test
execution, i.e. node 24 shall remain in BD_Sleep.




with shortend low phase and to remain in BD_Sleep mode according to section

implementation.
• Failure: none.





Pass criteria:
this time.




up patterns and to remain in BD_Sleep mode according to section 8.11.1 in [01-PL
Spec] on page 54 while no stress condition is present.

implementation.
• Failure: none.





Pass criteria:
this time.


5.3.10 Mode.Bus Driver.ReceiveOnly


BD_ReceiveOnly by host command according to figure 8-2, transition number 7 in
[01-PL Spec] while no stress condition is present.

• Failure: none.



• Stimulate IUTs in all nodes except node 24 via host interface to enter
BD_ReceiveOnly. The IUT in node 24 remains in BD_Normal.
on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern,
followed by one TSS pattern, followed by one 50/50 pattern.

Pass criteria:
• uRxD of node 24 shall not contain any 50/50 pattern transmitted at uTxD

and uTxEN of all other nodes, i.e. the IUTs in all nodes except node 24
shall not transmit any data while in BD_ReceiveOnly mode.
• uRxD of all nodes except node 24 shall contain the 50/50 pattern
transmitted at uTxD and uTxEN of node 24, i.e. the IUTs in all nodes
except node 24 shall receive data while in BD_ReceiveOnly mode.
HIGH state before the IUT in node 24 is stimulated to transmit (falling edge
of uTxD and uTxEN of node 24) and shall be in logical LOW state while the
signal uRxD of the corresponding node signals the received pattern.



[01-PL Spec] while ground shift is present.

• Failure: none.





Pass criteria:




[01-PL Spec] while low battery voltage is present.
Control” or the BD_ReceiveOnly mode is not implemented.

• Failure: none.




Pass criteria:

execution.



[01-PL Spec] while no stress condition is present.

• Failure: none.





Pass criteria:




[01-PL Spec] while ground shift is present.

• Failure: none.





Pass criteria:




[01-PL Spec] while low battery voltage is present.
Control” or the BD_ReceiveOnly mode is not implemented.

• Failure: none.





Pass criteria:

execution.

5.3.11 Failure.Loss

Standard, Failure STBN unconnected

This test checks the behaviour of the IUT in case of an unconnected STBN signal
according to table 8-24 in [01-PL Spec].
This test case is skipped if the STBN signal (host interface option A) is not
implemented.

• Failure: STBN unconnected.

• Switch STBN signal of node 24 to unconnected according to Figure 3-5
and Table 3-4, failure FL9 and all available mode control signals (CTRLx)
to logical LOW state.



wake-up patterns.
• Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by two wake-up
patterns.

Pass criteria:
• uRxD of all nodes shall be in logical HIGH state while the IUT in node 24 is
stimulated to transmit (while uTxEN of node 24 is in logical LOW), i.e. the
IUT in node 24 shall not transmit any pattern in BD_Standby mode.
• uRxD of node 24 shall be in logical HIGH state before the first falling edge
of uTxD or uTxEN of node 1. After the wake-up event is detected, uRxD of
node 24 shall be in logical LOW state.
HIGH state before the first falling edge of uTxD or uTxEN of node 1. After
the wake-up event is detected, uRxEN of node 24 shall be in logical LOW
state.


Standard, Failure CTRL2 unconnected

This test checks the behaviour of the IUT in case of an unconnected CTRL2 signal
This test case is skipped if the host interface option A is not implemented or the
Functional Class “Bus Driver Voltage Regulator Control” is not implemented.

• Failure: CTRL2 unconnected.

• Switch CTRL2 signal of node 24 to unconnected according to Figure 3-5
and Table 3-4, failure FL18 and all other available mode control signals
(CTRLx) and STBN to logical LOW state.



wake-up patterns.
• Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by two wake-up
patterns.

Pass criteria:
stimulated to transmit (while uTxEN of node 24 is in logical LOW), i.e. the

IUT in node 24 shall not transmit any pattern in BD_Standby mode.
• uRxD of node 24 shall be in logical HIGH state before the first falling edge
of uTxD or uTxEN of node 1. After the wake-up event is detected, uRxD of
node 24 shall be in logical LOW state.
execution.
HIGH state before the first falling edge of uTxD or uTxEN of node 1. After
the wake-up event is detected, uRxEN of node 24 shall be in logical LOW
state.


Standard, Failure TxEN unconnected

This test checks the behaviour of the IUT in case of an unconnected TxEN signal
according to table 8-24 and table 8-25 in [01-PL Spec].

• Failure: TxEN unconnected.

• Switch TxEN signal of node 24 to unconnected according to Figure 3-5 and
Table 3-4, failure FL5.



pattern.
• Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one wake-up
pattern, followed by one TSS pattern, followed by one 50/50 pattern.

Pass criteria:

stimulated to transmit, i.e. the IUT in node 24 shall be fail silent while TxEN
is unconnected.
• uRxD of node 24 shall contain the 50/50 pattern transmitted by node 1.
HIGH state before the first falling edge of uTxD or uTxEN of node 1. Then,
uRxEN of node 24 shall be in logical LOW state while uRxD of node 24
signals the received patterns.


Standard, Failure TxD unconnected

This test checks the behaviour of the IUT in case of an unconnected TxD signal
according to table 8-24 and table 8-25 in [01-PL Spec].

• Failure: TxD unconnected.

• Switch TxD signal of node 24 to unconnected according to Figure 3-5 and



pattern.

Pass criteria:
• uRxD of all nodes except node 24 shall contain a logical LOW state

sequence of at least 10 bit times after the IUT in node 24 starts TSS
pattern transmission (corresponding falling edge of uTxEN of node 24), i.e.
the IUT in node 24 reads TxD as logical LOW state while TxD is
unconnected.
HIGH state before the first falling edge of uTxD or uTxEN of node 1. Then,
uRxEN of node 24 shall be in logical LOW state while uRxD of node 24


Standard, Failure BGE unconnected

This test checks the behaviour of the IUT in case of an unconnected BGE signal
This test case is skipped if the Functional Class “Bus Driver – Bus Guardian Control
Interface” is not implemented.

• Failure: BGE unconnected.

• Switch BGE signal of node 24 to unconnected according to Figure 3-5 and

• Observe and acquire uRxEN at TP_N24_RxEN of node 24.


pattern.

Pass criteria:

stimulated to transmit, i.e. the IUT in node 24 shall be fail silent while BGE
is unconnected.
• uRxEN of node 24 shall be in logical HIGH state before the first falling
edge of uTxD or uTxEN of node 1. Then, uRxEN of node 24 shall be in
logical LOW state while uRxD of node 24 signals the received patterns.


Standard, Failure VBAT interrupted, VCC implemented

This test checks the behaviour of the IUT in case of an interruption of VBAT according
to table 8-8 and table 8-25 in [01-PL Spec].

implementation.
• Failure: VBAT interrupted.

• Interrupt supply wire VBAT of the IUT in node 24 according to Figure 3-5
and Table 3-4, failure FL1.


Pass criteria:
execution.
• an error shall be signaled via the host interface of node 24.


Standard, Failure VBAT interrupted, VCC not implemented

This test checks the behaviour of the IUT in case of an interruption of VBAT according
to table 8-25 in [01-PL Spec].
Control” or the Functional Class “Bus Driver Internal Voltage Regulator” is not
implemented or a VCC supply input is although available.

• Failure: VBAT interrupted.

• Interrupt supply wire VBAT of the IUT in node 24 according to Figure 3-5


Pass criteria:
• uINH1 of node 24 shall be in logical LOW state during test execution.


Standard, Failure VCC interrupted, VBAT implemented

This test checks the behaviour of the IUT in case of an interruption of VCC according
to table 8-8 and table 8-25 in [01-PL Spec].

• Failure: VCC interrupted.

• Interrupt supply wire VCC of the IUT in node 24 according to Figure 3-5 and


Pass criteria:
execution.




Standard, Failure VCC interrupted, VBAT not implemented

This test checks the behaviour of the IUT in case of an interruption of VCC according
to table 8-25 in [01-PL Spec].
Control” is implemented.

• Failure: VCC interrupted.

• Interrupt supply wire VCC of the IUT in node 24 according to Figure 3-5 and


Pass criteria:


Standard, Failure VBAT and VCC interrupted

This test checks the behaviour of the IUT in case of an interruption of VBAT and VCC
supply input according to table 8-25 in [01-PL Spec].

• Failure: VBAT and VCC interrupted.

• Interrupt supply wires VBAT and VCC of the IUT in node 24 according to
Figure 3-5 and Table 3-4, failure FL3.


Pass criteria:
• uINH1 of node 24 shall be in logical LOW state during test execution.


Standard, Failure GND of IUT unconnected

This test checks the behaviour of the IUT in case of an unconnected GND
connection of the IUT according to table 8-25 in [01-PL Spec].

• Failure: GND of IUT unconnected.

• Switch GND connection of IUT in node 23 to unconnected according to

pattern.

Pass criteria:

• node 23 shall ignore the incoming data stream and shall signal Idle to the
bus.
observation window in the test execution.


Standard, Failure GND of Node unconnected

connection of the whole node according to table 8-25 in [01-PL Spec].


• Switch GND connection of whole node 23 to unconnected according to

pattern.

Pass criteria:

• node 23 shall ignore the incoming data stream and shall signal Idle to the
bus.
observation window in the test execution.

5.3.12 Failure.Short Circuits

Standard, Failure TxEN GND

This test checks the behaviour of the IUT when TxEN is shorted to GND according to
table 8-25 in [01-PL Spec].

• Failure: short circuit of TxEN and GND.


• Short-circuit TxEN and GND of the IUT in node 24 according to Figure 3-5

• Beginning with the falling edge of uTxEN of node 24, stimulate IUT in node
24 at TP_N24_TxD by a logical LOW state sequence of at least 15000µs.

Pass criteria:
Hint: For BranchActive timeout measurement, a trigger event on the falling edge of
uTxEN is required.
uTxEN of node 24. After the falling edge of uTxEN of node 24, uRxD of

node 23 shall change to logical LOW state and shall remain in logical LOW
state for at least 1500µs and not more than 15000µs. After this logical
LOW state phase, uRxD of node 23 shall return to logical HIGH state and
shall remain in logical HIGH state.
• an error shall be signaled via the host interface of node 24 not earlier than
1500µs and not later than 15000µs after the falling edge of uTxEN of node
24.

5.3.13 Power Supply.Undervoltage VBAT
5.3.13.1 Standard environment, Ground Shift = 0, Failure = 0, VCC = not

implemented, BD_Normal

This test checks the behaviour of the IUT under the fault condition of an
undervoltage of VBAT occurring in BD_Normal mode if VCC is not implemented and no
other stress condition is present according to table 8-25 in [01-PL Spec].
In case of an available VCC supply input, see test case 5.3.9.4 and following and skip
this test case.

implemented and if a VCC supply input is although available.
• External VBAT power supply of IUT in node 24: default.
implementation.
• Failure: none.


• After the falling edge of the error signal of node 24, stimulate IUT in node
24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern.



Pass criteria:
VBAT voltage at the IUTs supply input has dropped to +2.0V.
1000ms after undervoltage is applied.



implemented, BD_Standby

undervoltage of VBAT occurring in BD_Standby mode if VCC is not implemented and
no other stress condition is present according to table 8-25 in [01-PL Spec].
In case of an available VCC supply input, see test case 5.3.9.17 and following and

implementation.
• Failure: none.




Pass criteria:



implemented, BD_ReceiveOnly

undervoltage of VBAT occurring in BD_ReceiveOnly mode if VCC is not implemented
and no other stress condition is present according to table 8-25 in [01-PL Spec].
In case of an available VCC supply input, see test case 5.3.9.6 and following and skip
this test case.

implementation.
• Failure: none.




Pass criteria:


5.3.13.4 Standard environment, Ground Shift = 0, Failure = 0, BD_Sleep

undervoltage of VBAT occurring in BD_Sleep mode if no other stress condition is
present according to table 8-25 in [01-PL Spec].

implementation.
• Failure: none.

• Sleep preamble.



Pass criteria:


5.3.14 Power Supply.Undervoltage VCC
5.3.14.1 Standard environment, Ground Shift = 0, Failure = 0, VBAT = not

implemented, BD_Normal

undervoltage of VCC occurring in BD_Normal mode if VBAT is not implemented and no
other stress condition is present according to table 8-25 in [01-PL Spec].
In case of an available VBAT supply input, see test case 5.3.7.28 and following and

implementation.
• Failure: none.


• Set external VCC power supply of the IUT in node 24 to +2.0V.



Pass criteria:
VCC voltage at the IUTs supply input has dropped to +2.0V.



implemented, BD_Standby

undervoltage of VCC occurring in BD_Standby mode if VBAT is not implemented and
no other stress condition is present according to table 8-25 in [01-PL Spec].

implementation.
• Failure: none.




Pass criteria:



implemented, BD_ReceiveOnly

undervoltage of VCC occurring in BD_ReceiveOnly mode if VBAT is not implemented
and no other stress condition is present according to table 8-25 in [01-PL Spec].

implementation.
• Failure: none.




Pass criteria:



undervoltage of VCC occurring in BD_Sleep mode if no other stress condition is

implementation.
• Failure: none.

• Sleep preamble.



Pass criteria:

5.3.15 Power Supply.Undervoltage VIO

undervoltage of VIO occurring in BD_Sleep mode if no other stress condition is
implemented.

• Failure: none.

• Sleep preamble.

• Set external VIO power supply of the IUT in node 24 to +0.75V.


Pass criteria:
voltage at the IUTs supply input has dropped to +0.75V.


5.3.16 Dynamic Low Battery Voltage
5.3.16.1 Standard environment, Ground Shift = 0, Failure = 0,

BD_Normal, tr1 ramp

This test checks the behaviour of the IUT after a dynamic low battery voltage pulse
according to chapter 3.4 in BD_Normal mode.
Hint: This test case intends to test the capability of the bus driver to return to the
operating state that was active before the dynamic low battery pulse. This test case
is applicable to all IUTs, even if no VBAT supply input is implemented. In this case, the

input voltage of the VCC (and if implemented VIO) voltage regulator (the battery
voltage of the ECU) is stressed by the dynamic low battery voltage pulse.
o VBAT power supply of all nodes: 11.6V.
• Failure: none.
• Test signal: US/tr1 as specified in chapter 3.4.



pattern.
followed by one 50/50 pattern. Repeat this sequence. At least one more
sequence shall be transmitted after the end of the dynamic low battery
voltage pulse.
• After the first communication round trigger the dynamic low battery pulse.


Pass criteria:
• while VBAT ≥ +5.5V, i.e. sufficient supply voltage at VBAT and for the VCC
and VIO voltage regulator is present:
o uRxD of all nodes except the corresponding transmitting node shall
contain all 50/50 patterns transmitted by all nodes (according to
uTxD and uTxEN of all nodes), i.e. all data shall be transmitted and
received by the IUTs in all nodes.
o in case of an available INH1 signal uINH1 of all nodes shall be in
logical HIGH.
o no error shall be signalled via the host interfaces of all nodes.


BD_Normal, tr6 ramp

according to chapter 3.4 in BD_Normal mode.

• Failure: none.
• Communication: matrix A.




pattern.
voltage pulse.

Pass criteria:
uTxD and uTxEN of all nodes), i.e. all data shall be transmitted and
received by the IUTs in all nodes.
logical HIGH.


BD_Standby, tr1 ramp

according to chapter 3.4 in BD_Standby mode.

o VBAT power supply of all nodes except node 24: 11.6V.
o External VBAT power supply of node 24: default.
implementation.
• Failure: none.



pattern.

voltage pulse.

Pass criteria:
o uRxD of node 24 shall not contain any pattern of any other node, i.e.
nothing is transmitted by the IUTs of all nodes except node 24.
o uRxD of all nodes except node 24 shall not contain any pattern of
node 24, i.e. the IUTs in all nodes except node 24 shall not receive
any data.
logical HIGH.


BD_Standby, tr6 ramp

according to chapter 3.4 in BD_Standby mode.

implementation.
• Failure: none.



pattern.

voltage pulse.

Pass criteria:
o uRxD of node 24 shall not contain any pattern of any other node, i.e.
nothing is transmitted by the IUTs of all nodes except node 24.
o uRxD of all nodes except node 24 shall not contain any pattern of
node 24, i.e. the IUTs in all nodes except node 24 shall not receive
any data.
logical HIGH.

5.3.16.5 Standard environment, Ground Shift = 0, Failure = 0, BD_Sleep,

tr1 ramp

according to chapter 3.4 in BD_Sleep mode.
operating state that was active before the dynamic low battery pulse. The input
voltage of the optional VCC or VIO voltage regulator (the battery voltage of the ECU) is
stressed by the dynamic low battery voltage pulse, when implemented.

implementation.
• Failure: none.

• Sleep preamble.



pattern.
voltage pulse.


Pass criteria:
o uRxD of node 24 shall contain no pattern of any other node, i.e.
nothing shall be transmitted by any IUT of all nodes except node 24.
o uINH1 of all nodes except node 24 shall be in logical LOW.
o no error shall be signalled via the host interface of node 24.

5.3.16.6 Standard environment, Ground Shift = 0, Failure = 0, BD_Sleep,

tr6 ramp

according to chapter 3.4 in BD_Sleep mode.
operating state that was active before the dynamic low battery pulse. The input
voltage of the optional VCC or VIO voltage regulator (the battery voltage of the ECU) is
stressed by the dynamic low battery voltage pulse, when implemented.

implementation.
• Failure: none.

• Sleep preamble.



pattern.
voltage pulse.


Pass criteria:
o uRxD of node 24 shall contain no pattern of any other node, i.e.
nothing shall be transmitted by any IUT of all nodes except node 24.
o uINH1 of all nodes except node 24 shall be in logical LOW.
o no error shall be signalled via the host interface of node 24.


BD_ReceiveOnly, tr1 ramp

according to chapter 3.4 in BD_ReceiveOnly mode.

implementation.
• Failure: none.




pattern.
voltage pulse.

Pass criteria:
o uRxD of all nodes except node 24 shall contain the 50/50 patterns
transmitted by node 24 (according to uTxD and uTxEN of node 24)
but none of any other node, i.e. all data transmitted by the IUT in
node 24 shall be received by the IUTs in all other nodes but none of
them shall transmit anything.
logical HIGH.


BD_ReceiveOnly, tr6 ramp

according to chapter 3.4 in BD_ReceiveOnly mode.

implementation.
• Failure: none.




pattern.
voltage pulse.

Pass criteria:
o uRxD of all nodes except node 24 shall contain the 50/50 patterns
transmitted by node 24 (according to uTxD and uTxEN of node 24)
but none of any other node, i.e. all data transmitted by the IUT in
node 24 shall be received by the IUTs in all other nodes but none of
them shall transmit anything.
logical HIGH.

5.3.17 Communication.Timing.Masks


This test checks the network parameter dPathAsym of the overall physical layer if no
stress condition is present according to the timing constraints chapter 12.3 in [01-PL
Spec]. This test shall verify, that a protocol controller would decode the information
transmitted properly.

• Failure: none.


pattern.

followed by one 10Bit High pattern, followed by one 10Bit Low pattern,
followed by one 10Bit High pattern.

Pass criteria:
• the length of all received 10Bit Low patterns in uRxD of all nodes shall be
equal to the length of the 10Bit Low pattern in uTxD of the corresponding
transmitting node -30.75ns/+43.23ns, i.e. the signal path asymmetry shall
be within the allowed range, according to chapter 5.1.16.

• no error shall be signaled via the host interface of all nodes.



This test checks the network parameter dPathAsym of the overall physical layer if
ground shift is present according to the timing constraints chapter 12.3 in [01-PL
Spec]. This test shall verify, that a protocol controller would decode the information
transmitted properly.

• Failure: none.


pattern.


Pass criteria:


LowBat, Failure = 0

This test checks the network parameter dPathAsym of the overall physical layer if
low battery voltage is present according to the timing constraints chapter 12.3 in [01-
PL Spec]. This test shall verify, that a protocol controller would decode the
information transmitted properly.

• Failure: none.


pattern.


Pass criteria:

5.3.18 Communication.Truncation


This test checks the overall channel truncation if no stress condition is present
according to the sum of all allowed truncation effects specified in [01-PL Spec]. This
test shall verify, that only the transmission start sequence is affected by truncation
effects and that a protocol controller would decode the following data properly.

• Failure: none.


pattern.



Pass criteria:
• the width of all received TSS patterns (logical LOW phase from the falling
edge of the received TSS pattern to the rising edge of the first bit of the
following 10/90 pattern) in uRxD of all nodes except the corresponding

transmitting node shall be at least 100ns, i.e. the channel truncation shall
be within the allowed range.



This test checks the overall channel truncation if ground shift is present according to
the sum of all allowed truncation effects specified in [01-PL Spec]. This test shall
verify, that only the transmission start sequence is affected by truncation effects and
that a protocol controller would decode the following data properly.

• Failure: none.


pattern.


Pass criteria:


LowBat, Failure = 0

This test checks the overall channel truncation if low battery voltage is present

• Failure: none.


pattern.


Pass criteria:

5.3.19 Failure.Short Circuit Bus Wires

Standard, Failure = S/C BP to GND

This test checks the ability of the IUT to limit the absolute current in case of a short
circuit of the bus wire to GND.
Additionally it is checked that the IUT is not permanently damaged by the short
circuit.

• Failure: S/C BP to GND.
• Communication: Node 24 and 23 as transmitter.



• Observe and acquire iBPGNDShortMax at TP_N24_RiBP of node 24 (shall be at

TP1_N24).
• Short circuit BP (failure FL11) of node 24 to GND at TP2_N24.
• Stimulate IUT of node 24 at TP_N24_TxD and TP_N24_TxEN by 166 short
circuit pattern according to chapter 5.1.3.9 after the short circuit of the bus
wire.
• Trigger the data aquisition unit to start the measurement 100µs after the
short circuit of the bus wire. Take the reading of the short circuit of the bus
wire while IUT transmits Data_0, Idle and Data_1.
• Switch off short circuit BP (failure FL11) of node 24. Wait at least 12
seconds.
pattern, followed by one 50/50 pattern. Wait 500µs.


Pass criteria:
• iBPGNDShortMax ≤ 100mA.
• After switching off the failure:
o uRxD of the IUT in node 24 must receive the patterns and signal
them at TP_N24_RxD and TP_N24_RxEN that are stimulated at
TP_N23_TxD and TP_N23_TxEN of node 23.
o In case of an available RxEN signal uRxEN of the IUT in node 24
must be in logical LOW state while receiving the patterns at
TP_N24_RxD that are stimulated at TP_N23_TxD and
must be in logical LOW state while receiving the patterns at
TP_N23_RxD that are stimulated at TP_N24_TxD and


Standard, Failure = S/C BM to GND

circuit.

• Failure: S/C BM to GND.


• Observe and acquire iBMGNDShortMax at TP_N24_RiBM of node 24 (shall be at
TP1_N24).
• Short circuit BM (failure FL12) of node 24 to GND at TP2_N24.


wire.
• Switch off short circuit BM (failure FL12) of node 24. Wait at least 12
seconds.


Pass criteria:
• iBMGNDShortMax ≤ 100mA.
must receive the patterns and signal them at TP_N24_RxD and
TP_N24_RxEN that are stimulated at TP_N23_TxD and


Standard, Failure = S/C BP to VBAT

circuit of the bus wire to +48V23.
circuit.

• Failure: S/C BP to +48V23.


23
In case the IUT does not support 42V systems the VBAT shall be +27V

• Observe and acquire iBPBAT48ShortMax24 or iBPBAT27ShortMax25 at TP_N24_RiBP

of node 24 (shall be at TP1_N24).
• Short circuit BP (failure FL13) of node 24 to +48V23 at TP2_N24.
wire.
• Switch off short circuit BP (failure FL13) of node 24. Wait at least 12
seconds.


Pass criteria:
• In case the IUT does not support 42V systems: iBPBAT27ShortMax ≤ 100mA.
• In case the IUT does support 42V systems: iBPBAT48ShortMax ≤ 120mA.
24
In case the IUT does support 42V systems
25
In case the IUT does not support 42V systems


Standard, Failure = S/C BM to VBAT

circuit.

• Failure: S/C BM to +48V23.


• Observe and acquire iBMBAT48ShortMax24 or iBMBAT27ShortMax25 at
TP_N24_RiBM of node 24 (shall be at TP1_N24).
• Short circuit BM (failure FL14) of node 24 to +48V23 at TP2_N24.


wire.
• Switch off short circuit BM (failure FL14) of node 24. Wait at least 12
seconds.


Pass criteria:
• In case the IUT does not support 42V systems: iBMBAT27ShortMax ≤ 100mA.
• In case the IUT does support 42V systems: iBMBAT48ShortMax ≤ 120mA.

5.3.20 Communication.Shortened Bit Times

Hint: value of about 36ns is a snapshot of the current status. This value may change
in the future if new results are available

Standard, Failure = 0, Low Pattern

This test checks the ability of the IUT to receive shortened bits according to the
timing constraints chapter 12.3 in [01-PL Spec]. This test shall verify, that the IUT
itself does receive the shortened bits correctly and signals them to the CC.

The test hardware shall be calibrated for this test case.
• Failure: none.


or TP_Nx_INTN) of node 11 and node 12.


pattern, followed by three 10Bit Low patterns, followed by one 10/90
pattern, followed by two 10Bit Low patterns. The length of each single bit
shall be 36ns measured at TP4_N12 of node 12. In case the bit length is
too long the stimulated bits at the transmitter shall be shortened, otherwise
the bits shall be elongated.

Pass criteria:
•

the length of the received high bit in the 10/90 pattern as specified in the
observation window in uRxD of node 12 shall be equal to the length of the
high bit in uBus of the corresponding TP4_N12 of node 12 ±5ns, i.e. the
receiver asymmetry shall be within the allowed range, according to chapter
12.3 in [01-PL Spec].
• no error shall be signaled via the host interface of node 11 and 12.


Standard, Failure = 0, High Pattern


• Failure: none.


pattern, followed by three 10Bit High patterns, followed by one 90/10
pattern, followed by two 10Bit High patterns. The length of each single bit
shall be 36ns measured at TP4_N12 of node 12. In case the bit length is

too long the stimulated bits at the transmitter shall be shortened, otherwise
the bits shall be elongated.

Pass criteria:
• the length of the received low bit in the 90/10 pattern as specified in the
observation window in uRxD of node 12 shall be equal to the length of the
low bit in uBus of the corresponding TP4_N12 of node 12 ±5ns, i.e. the

12.3 in [01-PL Spec].
• no error shall be signaled via the host interface of node 11 and 12.

5.3.21 Dynamic Ground Shift
5.3.21.1 Standard environment, Ground Shift = dynamic at the

transmitter, Power Supply = Standard, Failure = 0

This test checks the ability of the IUT to transmit a test pattern while dynamic ground
shift is present.

• Ground shift: Dynamic at node 23.
• Failure: None.


wake-up pattern as described in chapter 5.1.3.1, followed by one TSS
pattern, followed by ten 50/50 patterns. Trigger the dynamic ground shift
curve synchronously with the first rising edge after the TSS pattern.

Pass criteria:
• the IUT of node 24 shall receive all 50/50 patterns ±5ns receiver
asymmetry after the trigger event in uRxD of node 24 equal to the pattern
in uTxD of node 23, i.e. the dynamic ground shift shall not disturb the
communication.

5.3.21.2 Standard environment, Ground Shift = dynamic at the receiver,


This test checks the ability of the IUT to receive a test pattern while dynamic ground
shift is present.

• Failure: None.


wake-up pattern as described in chapter 5.1.3.1, followed by one TSS
pattern, followed by ten 50/50 patterns. Trigger the dynamic ground shift
curve synchronously with the first rising edge after the TSS pattern.

Pass criteria:

• the IUT of node 23 shall receive all 50/50 patterns ±5ns receiver
asymmetry after the trigger event in uRxD of node 23 equal to the pattern
in uTxD of node 24, i.e. the dynamic ground shift shall not disturb the
communication.

5.3.22 Eye Diagram


This test checks the eye diagram at the receiver according to the eye diagram
chapter 7.4 in [01-PL Spec].
In this test case the bandwidth of the oscilloscope shall be limited to 20MHz.

• Failure: none.


• Limit the bandwidth of the oscilloscope to 20MHz.
• Observe and acquire uTxEN at TP_N1_TxEN of node 1 according to the
• Stimulate IUT in the node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS
pattern, followed by ten 50/50 pattern.


Pass criteria:
• The eye diagram obtained with the observed and acquired uBus signal at
TP4_N2 of node 2 shall not violate the mask of TP4 defined in Figure 7-4
in [01-PL Spec].
• no error shall be signaled via the host interface of node 1 and node 2.

5.4 Test Procedures
5.4.1 Signal Shape, Timing, Delay
PowerSupply_VBAT.IBatterySupplyConfig.Output()
PowerSupply_VBAT.IBatterySupplyConfig.EnableOutput(true)
PowerSupply_VGS.IDCPowerSupplyConfig.Output() *
PowerSupply_VGS.IDCPowerSupplyConfig.EnableOutput(true) *
NetServices.ISwitch.SetGroundShift() *

NetServices.ISwitch.SetTermination() **
PatternGenerator.IPatternGenerator.Configure()
PatternGenerator.IPatternGenerator.CreateComposedPattern()
Scope.IConfiguration.Configure()
Scope.IConfiguration.Acquisition()
Scope.IConfiguration.Channel()
Scope.IConfiguration.Trigger()
LogicAnalyzer.ILogicAnalyzer.Configure()
NetServices.IControl.SetOperatingMode()
Scope.IAcquireBusData.Initiate()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_VGS.IDCPowerSupplyConfig.EnableOutput(false) *
Scope.AcquireBusData.GetWaveform()
Scope.AcquireBusData.ObtainParameter()
NetServices.ISwitch.ResetNet()
PowerSupply_VBAT.IBatterySupplyConfig.EnableOutput(false)
*** Test cases with ground shift, only.

*** Test cases with specific termination, only.
Figure 5-43: Test Procedure for Signal Shape, Timing and Delay Test Cases

5.4.2 Truncation, Masks

Figure 5-44: Test Procedure for Truncation and Masks Test Cases

5.4.3 Mode
PowerSupply_ALT_VBAT.IDCPowerSupplyConfig.Output() *
PowerSupply_ALT_VBAT.IDCPowerSupplyConfig.EnableOutput(true) *
PowerSupply_ALT_VIO.IDCPowerSupplyConfig.Output() *
PowerSupply_ALT_VIO.IDCPowerSupplyConfig.EnableOutput(true) *
NetServices.ISwitch.SetSupplyConfig() *
PowerSupply_VGS.IDCPowerSupplyConfig.Output() **

PowerSupply_VGS.IDCPowerSupplyConfig.EnableOutput(true) **
NetServices.ISwitch.SetGroundShift() **
PatternGenerator.IPatternGenerator.Configure() ***
PatternGenerator.IPatternGenerator.CreateComposedPattern() ***
PowerSupply_ALT_VBAT.IDCPowerSupplyConfig.Output() ****
PowerSupply_ALT_VIO.IDCPowerSupplyConfig.Output() ****
NetServices.IControl.SetOperatingMode() *****
NetServices.IControl.SendLocalWakeup() ******
PowerSupply_VGS.IDCPowerSupplyConfig.EnableOutput(false) **
PowerSupply_ALT_VBAT.IDCPowerSupplyConfig.EnableOutput(false) *
PowerSupply_ALT_VIO.IDCPowerSupplyConfig.EnableOutput(false) *
****** Test cases with alternative power supply configuration, only.

****** Test cases with ground shift, only.
****** Required for setup state in some test cases, only.
****** Test cases with alternative power supply output change during test execution, only.
****** Test cases with operation mode change of IUT(s) during test execution, only.
****** Test cases with local wakeup of IUT(s) during test execution, only.
Figure 5-45: Test Procedure for Mode Test Cases

5.4.4 Failure
NetServices.ISwitch.SetSupplyConfiguration() *
NetServices.ISwitch.SetInterruptionOnBoard() **
NetServices.ISwitch.SetShortCircuitOnBoard() **

*** Test cases with alternative power supply configuration, only.

*** Test cases with on board interruptions or short circuits, only.
*** Required for setup state, only.
Figure 5-46: Test Procedure for Failure Test Cases

5.4.5 Undervoltage
PowerSupply_ALT_VCC.IDCPowerSupplyConfig.Output() *
PowerSupply_ALT_VCC.IDCPowerSupplyConfig.EnableOutput(true) *
PowerSupply_ALT_VIO.IDCPowerSupplyConfig.Output() *
PowerSupply_ALT_VIO.IDCPowerSupplyConfig.EnableOutput(true) *

PowerSupply_ALT_VCC.IDCPowerSupplyConfig.Output() ****
PowerSupply_ALT_VIO.IDCPowerSupplyConfig.Output() ****
PowerSupply_ALT_VIO.IDCPowerSupplyConfig.EnableOutput(false) *
PowerSupply_ALT_VCC.IDCPowerSupplyConfig.EnableOutput(false) *
**** Test cases with alternative power supply configuration, only.

**** Test cases with ground shift, only.
**** Required for setup state, only.
**** Test cases with alternative power supply output change during test execution, only.
Figure 5-47: Test Procedure for Undervoltage Test Cases

5.4.6 Dynamic Low Battery
PowerSupply_VBAT.IBatterySupplyConfig.DynamicLowBattery()

PowerSupply_VBAT.IBatterySupplyConfig.InitiateArbitraryFunction()
NetServices.IControl.SetOperatingMode() **
** Test cases with alternative power supply configuration, only.

** Test cases with op-mode change during test execution, only.
Figure 5-48: Test Procedure for Dynamic Low Battery Cases

6 Test Cases for Active Stars within a

homogeneous Topology
These test case section is applicable to all active stars, independent from an
implemented communication controller or bus guardian interface. In such case, TxD
and TxEN of the communication controller interface and BGE of the bus guardian
interface shall be set to logical HIGH state permanently, if implemented.
6.1 Configuration
6.1.1 Topology

As specified in chapter 2.4. All IUT of the active star are of the same type and from
the same manufacturer.
6.1.2 Test Planes

The active star has four specified test planes. Two test planes for the transmitting
branch and two for the receiving branch.
Transmitter Active Star Receiver

Transmitting Branch
Receiving Branch
BD AS BD
TPAS3_By TPAS4_By TPAS1_By TPAS2_By
Figure 6-1: Test Planes @ the Active Star for analog Signals
TP Name Signal Description
TPAS1_By uBus Transmitting branch, test plane as close as possible to the

IUT
TPAS1_By uBP Transmitting branch, test plane as close as possible to the

TP Name Signal Description

IUT
TPAS1_By uBM Transmitting branch, test plane as close as possible to the

IUT
TPAS2_By uBus Transmitting branch, test plane as close as possible to the

network
TPAS3_By uBus Receiving branch, test plane as close as possible to the

network
TPAS4_By uBus Receiving branch, test plane as close as possible to the IUT

Table 6-1: Test Planes @ the Active Star for analog Signals
11
2 AS 4
Figure 6-2: 4: Branches of the Active Star

The AS has 4 branches that are named for the test planes as TPASx_By where
• x stands for the test plane
• y stands for the branch of the AS
Example:
TPAS1_B2 represents the test plane 1 at the branch 2 of the AS.

The test planes at the AS for digital signals (observation by logic analyzer) are
specified as:

TP
AS
INH1
BD

Figure 6-3: Test Planes @ the AS
TP_AS_INH1 INH1 INH1 signal of the IUT
Table 6-2: Test Planes @ the AS (digital Signals)
6.1.2.3 Test Planes for current measurement

A shunt shall be implemented in order to measure the current of the bus wires:
• TP_AS_B126_RiBP
• TP_AS_B1_RiBM
6.1.3 Test Patterns
6.1.3.1 Babbling Idiot

This test signal simulates a babbling idiot:
26
Only branch 1 is affected

gdTSSTransmitter 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs
High
Node 12 TXEN Low
800µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 700µs
High
Node 13 TXEN Low
2000µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1000µs
High
Node 14 TXEN Low
16500µs
Figure 6-4: Test Pattern for a Babbling Idiot Simulation
6.1.3.2 Star Setup Delay

These test signals are specified to check the parameter dStarSetUpDelay.
Test signal of node 1:
gdBit
gdTSSTransmitter 0 1 2 3 4 5 6 7 8
High
TXD
Low
High
TXEN Low
Figure 6-5: Test Signal for Node 1 (Star Setup Delay)
Test signal of node 2:
gdBit
High
TXD
Low
High
TXEN Low
Figure 6-6: Test Signal for Node 2 (Star Setup Delay)

6.1.4.1 Parameters dStarDelay and dStarDelay0

High
TxD
Low
TxEN High
Low
10gdBit
Trigger Event Zoom
Zoom – Observation Window 1µs
0 1 2 3 4 5 6 7 8 9
High
TxD

Low
High
TxEN Low
Observation Window
Figure 6-7: Observation Point for the Analysis of the Star Delay
Trigger event: first positive edge of uBus signal at TPAS4_By of the
receiving branch, trigger level +300mV.
Start acquisition point 1: 43.55µs after the trigger event.
Start acquisition point 2: 20µs after acquisition point 2.
Observation Window: 1µs.
The [01-PL Spec] shows the measurement descriptions of the parameters
[dStarDelay, dStarDelay0] in figure 9-3.

6.1.4.2 Parameter dStarTruncation

High
TxD
Low
TxEN High
Low
10gdBit
Trigger Event Zoom
Zoom – Observation Window 1.6µs
gdTSSTransmitter
High
TxD
Low

High
TxEN Low
Observation Window
Figure 6-8: Observation point for the Analysis of the Active Star Truncation
receiving branch.
Observation Window: 1.6µs.
The [01-PL Spec] shows the measurement description of the parameter
dStarTruncation in figure 9-3.

6.1.4.3 Parameter dStarSetUpDelay

High
TxD
Node A Low
TxEN High
Low
dStarSetUpDelay
High Pattern A
TxD
Node B Low
TxEN High
Low
410 gdBit = 41µs dStarSetUpDelay
Pattern B
Zoom
Trigger Event
500 ns
Zoom - Observation Window 4.2µs
High
TxD

Low
dStarSetUpDelay Pattern A
High
TxEN Low
High
TxD
Low
dStarSetUpDelay Pattern B
High
TxEN Low
Observation Window
Figure 6-9: Observation point for the Analysis of the Active Star SetUp Delay
receiving branch.
Observation Window: 4.2µs.
The [01-PL Spec] shows the measurement description of the parameter
dStarSetUpDelay in figure 9-6.
6.1.4.4 Parameter dStarWakeUpReaction

This observation window is to verify the bus state change from Idle_LP to Idle after
detection of a remote wake-up event.
Observation Window: 100ms.

6.1.4.5 Parameter dStarGoToSleep

This observation window is to verify the bus state change from Idle to Idle_LP when
all branches are in Branch_Idle or Branch_FailSilent for longer than
dStarGoToSleep.
Observation Window: 64000ms.
6.1.4.6 Branch modes

This observation window is to verify the branch modes of the branches of the active
star, i.e. Branch_Idle (bus state Idle), Branch_Active (bus states Data_1, Data_0)

and Branch_FailSilent (bus state Idle).
6.1.4.7 Parameter dBranchActive

This observation window is to verify the branch noise detection time dBranchActive.
Trigger event: first positive edge of uBus signal at TPAS4_B4 of the
receiving branch 4.
6.1.4.8 Dynamic Low Battery – AS_Sleep

This observation window is to verify the bus state of the branches of the active star
during the dynamic low battery pulse. All branches shall be in Idle_LP state.
Start acquisition point: 0s after the trigger event.
Observation Window: 10.2s (ceiled duration of low battery voltage pulse).
6.1.5 Power Modes of the AS

The AS has the following power mode:
•
AS_Normal: receive/transmit possible, transition to AS_Sleep possible.
•
AS_Sleep: receive/transmit NOT possible, transition to AS_Normal
possible via wake-up symbol on the bus.
The AS reaches the power modes by:

Power Mode Enter by…

AS_Normal • Switching on the supply
• Wake-up pattern on the bus
AS_Sleep • End of communication after a specified
timeout
• Undervoltage condition

The used power supplies:
• The VCC supply is connected to the IUT with different voltages.
VCC= +2.0V, +5.0V.

• The VBAT supply input of the AS is optional and may be connected to the
IUT with different voltages.
VBAT= default, +7.0V, +5.5V, +2.0V.
6.1.7 Stress
The ground shift is located as shown in Figure 3-2.
The low battery affects the active star only.
Note that the common nodes including their bus drivers are not stressed at all in
active star test cases! All nodes are always supplied with all implemented supply
voltages and not stressed by low battery or ground shift.
6.1.8 Failures
Failures of the AS are also described in chapter 3.5.

The following features are optional as specified in [01-PL Spec] and must be tested
6.1.9.1 Functional Class “Active Star - Voltage Regulator Control”

o Signal INH1
o Power supply input VBAT
6.1.9.2 Functional Class “Active Star - Internal Voltage Regulator”

supply input and requires that the AS is fully operational without a VCC
supply.

6.1.10 Definition of Communication

Matrix C:
Some test instances need only 2 transmitters:
Message from Node

FlexRay Data
on the bus
1 2
t
Figure 6-10: Communication Matrix C

Delay between the messages: 500ns. The second transmitter (node 2) starts
transmission only 500ns after the first transmitter (node 1). So, the transmission of
node 2 shall reach the active star slightly later than 500ns after the transmission of
node 1, because the propagation delay between node 2 to the active star (3.5m) is
greater than between node 1 and the active star (1m).
Matrix E:
Some test cases need a matrix for the passive networks:
Message from Node x
Transmitters 12 23
t
Figure 6-11: Communication Matrix E

Pause between the messages: 20µs.
Single Transmitter
In some test cases only one transmitter is required:

11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Transmitter

Figure 6-12: Communication Single Transmitter
Node 1 and 2 as Transmitter

In some test cases node 1 and 2 as transmitter are required:
Transmitter 1 Point of Observation
11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Figure 6-13: Communication Node 1 and 2 as Transmitter
In this communication node 23 is the transmitter.

Message from Node
Transmitter 23

11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Transmitter

the configuration.
5. TxEN and TxD of all nodes shall be in logical HIGH (idle) state.
6. In case a BGE signal is available, this signal shall be in logical HIGH state in
all nodes.
7. Stimulate bus drivers of all nodes via host command to enter BD_Normal.


the configuration.

all nodes.
8. Wait 64000ms to make sure that the AS enters AS_Sleep.

1. Set ground shift to 0V.
2. Reset failures.
3. Switch off power supplies.
6.1.14 Services
Services correspond to chapter 5.1.17.


test is failed.
1. dBusTx01 Communication. Rise time differential voltage 5 25 ns

Signal Shape (-300mV 300mV)

2. dBusTx10 Communication. Fall time differential voltage 5 25 ns
Signal Shape (300mV -300mV)
3. uASTxactive Communication. Absolute differential voltage 600 2000 mV

Signal Shape while sending
4. uASTxidle Communication. Absolute differential voltage 0 30 mV

Signal Shape while Idle
5. uBusActiveHigh Communication. Upper receiver threshold for 150 425 mV

Threshold detecting activity
6. uBusActiveLow Communication. Lower receiver threshold for -425 -150 mV

Threshold detecting activity
7. dBranchActive Communication. Noise detection time 1500 15000 µs

Timing
8. dBranch Communication. Timeout for recovery after failure 10 µs

FailSilentIdle Timing
9. dActivity Communication. Allowed time for receiver to 100 300 ns

Detection Timing detect bus activity
10. dIdle Communication. Allowed time for receiver to 50 250 ns

Detection Timing detect bus Idle
11. RCM1, RCM2 Environment Common mode input resistance 10 40 kΩ
12. uCM Environment. Common mode voltage range -10 +15 V

Ground Shift
13. VBAT Power Transition to low power mode 2 5.5 V

monitoring Supply when voltage falls below product
specific threshold
14. VCC monitoring Power Transition to low power mode 2 Product V

Supply when voltage falls below product specific
specific threshold
15. dUV Power Reaction time for undervoltage 1000 ms

Supply detection

16. dStarTruncatio Communication. Shortening of the TSS 450 ns

n Truncation
17. iBPLeak Mode. Leakage current when all 25 µA

Bus Driver. supplies are switched off
Off.iBPLeak
18. iBMLeak Mode. Leakage current when all 25 µA

Bus Driver. supplies are switched off
Off.iBMLeak
19. iBMGNDShortMax Failure. Maximum output current when 100 mA

Short circuit.BM shorted to GND

20. iBPGNDShortMax Failure. Maximum output current when 100 mA
Short circuit.BP shorted to GND
21. iBMBAT48ShortMax Failure. Maximum output current when 120 mA

Short circuit.BP shorted to VBAT =48V
22. iBPBAT48ShortMax Failure. Maximum output current when 120 mA

Short circuit.BM shorted to VBAT =48V
23. Functional Functional Class Checks the complete implemen- - -

Class tation of all specified options
”Active Star –
Bus Guardian
interface
24. Functional Functional Class Checks the complete implemen- - -
Class tation of all specified options
”Active Star –
Communi-
cation
controller
interface”

6.3 Test Cases
6.3.1 Communication.Delay.dStarDelay


This test checks the FlexRay parameter dStarDelay (propagation delay of a positive
edge through the active star) in the test system while no stress condition is present.

o VCC power supply of active star: +5.0V.
o VBAT power supply of active star: default.
• Failure: none.
• Communication: matrix E; the delay is measured twice for each transmitted
data
o 1st pass according to chapter 6.1.4.1 (43.55µs, N12)
o 2nd pass according to chapter 6.1.4.1 (43.55µs + 20µs, N23)


• Observe and acquire uTxD at TP_Nx_TxD of the transmitting node
according to the observation window described in chapter 6.1.4.1.
• Observe and acquire uTxEN at TP_Nx_TxEN of the transmitting node
• Observe and acquire uBus at TPAS4_B4/2 of the receiving branches
• Observe and acquire uBus at TPAS1_B2/4 of the transmitting branches


TP_AS_INH1 of the active star.
• Stimulate the bus driver of the first transmitting node according to the
sequence described on matrix E at TP_Nx_TxD and TP_Nx_TxEN by one
wake-up pattern.
• Stimulate the bus drivers of the transmitting nodes according to the
TSS pattern, followed by one 10/90 pattern.
6.3.1.1.5 Postamble

Pass criteria:
• dStarDelay ≤ 250ns.

6.3.1.2 Standard environment, Ground Shift = active @ AS, Power


This test checks the FlexRay parameter dStarDelay (delay of a positive edge
through the active star) in the test system while ground shift at the active star is
present.

• Ground shift: +5V @ AS located according to the Figure 3-2.
• Failure: none.
data



wake-up pattern.
6.3.1.2.5 Postamble

Pass criteria:


6.3.1.3 Standard environment, Ground Shift = active @ node, Power


through the active star) in the test system while ground shift at a transmitting node is
present.

• Ground shift: +5V @ node 23 according to the Figure 3-2.
• Failure: none.
data



wake-up pattern.
6.3.1.3.5 Postamble

Pass criteria:



LowBat, Failure = 0

through the active star) in the test system while low battery voltage is present.
This test case is skipped if the Functional Class “Active Star - Voltage Regulator

o VBAT power supply of active star: +5.5V.
• Failure: none.
data


• Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Stimulate the bus driver if the first transmitting node according to the
wake-up pattern.


6.3.1.4.5 Postamble

Pass criteria:

6.3.2 Communication.Delay.dStarDelay0


This test checks the FlexRay parameter dStarDelay0 (propagation delay of a
negative edge through the active star) in the test system while no stress condition is
present.

• Failure: none.
data



wake-up pattern.
6.3.2.1.5 Postamble

Pass criteria:

• dStarDelay0 ≤ 250ns.



This test checks the FlexRay parameter dStarDelay0 (delay of a negative edge
through the active star) in the test system while ground shift at the active star is
present.

• Failure: none.
data



wake-up pattern.
6.3.2.2.5 Postamble

Pass criteria:




through the active star) in the test system while ground shift at a transmitting node is
present.

• Failure: none.
data



wake-up pattern.
6.3.2.3.5 Postamble

Pass criteria:



LowBat, Failure = 0

through the active star) in the test system while low battery voltage is present.

• Failure: none.
data


wake-up pattern.


6.3.2.4.5 Postamble

Pass criteria:

6.3.3 Communication.Delay.dStarAsym


This test checks the FlexRay parameter dStarAsym of the active star while no stress
condition is present.
This parameter is calculated as dStarAsym = | dStarDelay – dStarDelay0 | with
dStarDelay as measured in test case 6.3.1.1 and dStarDelay0 as measured in test
case 6.3.2.1.

The calculation is done twice:
• In case that node 12 is the transmitter

• No preamble needed.

• Calculation of dStarAsym = | dStarDelay – dStarDelay0 | as measured in
the test cases above.
6.3.3.1.5 Postamble
• No postamble needed.

Pass criteria:
• dStarAsym ≤ 8ns.

6.3.3.2 Standard environment, Ground Shift = active @ active star,


This test checks the FlexRay parameter dStarAsym of the active star while ground
shift at the active star is present.
case 6.3.2.2.



6.3.3.2.5 Postamble

Pass criteria:



This test checks the FlexRay parameter dStarAsym of the active star while ground
shift at the transmitting node is present.
case 6.3.2.3.



6.3.3.3.5 Postamble

Pass criteria:


LowBat, Failure = 0

This test checks the FlexRay parameter dStarAsym of the active star while low
battery voltage is present.

case 6.3.2.4.


6.3.3.4.5 Postamble

Pass criteria:

6.3.4 Communication.Delay.dStarSetUpDelay


This test checks the FlexRay parameter dStarSetUpDelay while no stress condition
is present. This test case verifies that a second incoming data stream reaching the
active star slightly after dStarSetUpDelay is ignored by the active star.

• Failure: none.
• Communication: matrix C.


• Observe and acquire uTxD at TP_Nx_TxD of the transmitting node.
• Observe and acquire uTxEN at TP_Nx_TxEN of the transmitting node.
• Observe and acquire uRxD at TP_Nx_RxD of all receiving nodes in the
branches B2 and B4 of the active star.
• Observe and acquire uBus at TPAS4_B1 of the receiving branches
• Observe and acquire uBus at TPAS1_B3 of the transmitting branches
sequence described on matrix C at TP_Nx_TxD and TP_Nx_TxEN by one
wake-up pattern.

sequence described on matrix C at TP_Nx_TxD and TP_Nx_TxEN by the
Star Setup Delay 127 pattern.
• Stimulate the bus driver of the second transmitting node according to the
Star Setup Delay 2 pattern. Start stimulation delayed by 500ns to the first
transmitting node.
6.3.4.1.5 Postamble

Pass criteria:

• the pattern sent by the second transmitting node shall not be retransmitted
by the active star because the incoming data stream shall be ignored after
dStarSetUpDelay.
• branch 2 and 4 must retransmit the pattern transmitted by node 1, only.
27
Test signals “Star Setup Delay 1 and 2" are specified in chapter 6.1.3.2.



This test checks the FlexRay parameter dStarSetUpDelay while ground shift at the
active star is present. This test case verifies that a second incoming data stream
reaching the active star slightly after dStarSetUpDelay is ignored by the active star.

• Failure: none.


wake-up pattern.

transmitting node.
6.3.4.2.5 Postamble

Pass criteria:

dStarSetUpDelay.
28



This test checks the FlexRay parameter dStarSetUpDelay while ground shift at a
receiving node is present. This test case verifies that a second incoming data stream
reaching the active star slightly after dStarSetUpDelay is ignored by the active star.

• Failure: none.


wake-up pattern.

transmitting node.
6.3.4.3.5 Postamble

Pass criteria:

dStarSetUpDelay.
29


LowBat, Failure = 0

This test checks the FlexRay parameter dStarSetUpDelay while low battery voltage
active star slightly after dStarSetUpDelay is ignored by the active star.

• Failure: none.


wake-up pattern.

transmitting node.
6.3.4.4.5 Postamble

Pass criteria:

dStarSetUpDelay.
30

6.3.5 Communication.Truncation.dTruncationM,N


This test checks the overall channel truncation while no stress condition is present

• Failure: none.


sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one
wake-up pattern.
6.3.5.1.5 Postamble


Pass criteria:



This test checks the overall channel truncation while ground shift at the active star is
present according to the sum of all allowed truncation effects specified in [01-PL
Spec]. This test shall verify, that only the transmission start sequence is affected by
truncation effects and that a protocol controller would decode the following data
properly.

• Ground shift: +5V at the AS located according to the Figure 3-2.
• Failure: none.


wake-up pattern.
6.3.5.2.5 Postamble


Pass criteria:



This test checks the overall channel truncation while ground shift at a node is
present according to the sum of all allowed truncation effects specified in [01-PL
Spec]. This test shall verify, that only the transmission start sequence is affected by
truncation effects and that a protocol controller would decode the following data
properly.

• Failure: none.


wake-up pattern.
6.3.5.3.5 Postamble


Pass criteria:


LowBat, Failure = 0

This test checks the overall channel truncation while low battery voltage is present

• Failure: none.


wake-up pattern.
6.3.5.4.5 Postamble


Pass criteria:

6.3.6 Communication.Truncation.dStarTruncation


This test checks the FlexRay parameter dStarTruncation while no stress condition is
present.

• Failure: none.
data
o 1st pass (receiving branch 2, node 12 as transmitter) according to
chapter 6.1.4.2 (41.95µs, N12)
o 2nd pass (receiving branch 2, node 12 as transmitter) according to
chapter 6.1.4.2 (41.95µs + 20µs, N23)




wake-up pattern.
6.3.6.1.5 Postamble

Pass criteria:
• dStarTruncation ≤ 450ns.



This test checks the FlexRay parameter dStarTruncation while ground shift at the
active star is present.

• Ground shift: +5V @ the AS located according to the Figure 3-2.
• Failure: none.
data
chapter 6.1.4.2 (41.95µs, N12)
chapter 6.1.4.2 (41.95µs + 20µs, N23)



wake-up pattern.
6.3.6.2.5 Postamble

Pass criteria:




This test checks the FlexRay parameter dStarTruncation while ground shift at a
transmitting node is present.

• Failure: none.
data
chapter 6.1.4.2 (41.95µs, N12)
chapter 6.1.4.2 (41.95µs + 20µs, N23)



wake-up pattern.
6.3.6.3.5 Postamble

Pass criteria:



LowBat, Failure = 0

This test checks the FlexRay parameter dStarTruncation while low battery voltage is
present.

• Failure: none.
data
chapter 6.1.4.2 (41.95µs, N12)
chapter 6.1.4.2 (41.95µs + 20µs, N23)



wake-up pattern.
6.3.6.4.5 Postamble

Pass criteria:


6.3.7 Mode.Active Star.Normal

Undervoltage VBAT, Failure = 0, VCC = standard

This test checks the ability of the active star to remain in operation mode AS_Normal
in case of an undervoltage on VBAT if VCC is still available according to table 9-4,
footnote (**) in [01-PL Spec] while no other stress condition is present.
Control” is not implemented or the Functional Class “Active Star - Internal Voltage

• VBAT power supply of active star: default.
• VCC power supply of active star: +5.0V.
• Failure: none.
• Communication: single transmitter.


• Set VBAT power supply of active star to +2.0V.
• Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by
one TSS pattern, followed by ten31 10Bit Low patterns. Repeat this
sequence with a pause between the messages of 20µs for at least 1000ms
to verify that communication is not disturbed even after the maximal
undervoltage detection timeout (dUV).
6.3.7.1.5 Postamble
31
The low phase shall be long enough to allow the logic state analyzer to detect each received low
phase in an observation period of at least 1000ms.


Pass criteria:
Hint: This test case requires acquisition of at least 1000ms by the logic state
analyzer. A bit level resolution is not required.
• uRxD of all observed nodes shall contain all logical LOW sequences
transmitted by node 2, i.e. the active star shall not enter AS_Sleep mode
and shall retransmit all patterns received on branch 3.
• uINH1 shall be in logical HIGH state during test execution, i.e. the active
star shall not enter AS_Sleep.



footnote (**) in [01-PL Spec] while ground shift is present.

• Ground shift: +5V @ the AS according to the Figure 3-2.
• Failure: none.


6.3.7.2.5 Postamble
32


Pass criteria:


Standard, Failure = 0, VBAT and VCC implemented

This test checks the ability of the active star to go to AS_Normal in case of power on
of VBAT and VCC while no stress condition is present.
Regulator” is implemented or a VCC supply input is not implemented.

• Failure: none.

• Set VBAT and VCC power supply of active star to 0V.

• Set VBAT power supply of active star to default.
• Set VCC power supply of active star to +5.0V.
one TSS pattern, followed by one 50/50 pattern.
6.3.7.3.5 Postamble

Pass criteria:
• uRxD of all observed nodes shall contain the 50/50 pattern transmitted by
node 2, i.e. the active star shall enter AS_Normal mode after power on and
re-transmit the test patterns of node 2.

• uINH1 shall be in logical HIGH state (Not_Sleep) after switching on the

power supplies up to the end of the test execution.



of VBAT and VCC while ground shift is present.

• Ground shift at the active star: +5V.
• Failure: none.


6.3.7.4.5 Postamble

Pass criteria:




Standard, Failure = 0, Only VCC implemented

of VCC while no stress condition is present.

• Failure: none.

• Set VCC power supply of active star to 0V.

6.3.7.5.5 Postamble

Pass criteria:



of VCC while ground shift is present.

• Ground shift at the active star: +5V.
• Failure: none.


6.3.7.6.5 Postamble

Pass criteria:


Standard, Failure = 0, Only VBAT implemented

of VBAT while no stress condition is present.
Regulator” is not implemented or a VCC supply input is implemented.

• Failure: none.

• Set VBAT power supply of active star to 0V.

6.3.7.7.5 Postamble

Pass criteria:


Standard, Failure = 0, Only VBAT implemented

of VBAT while ground shift is present.

• Ground shift: +5V.
• Failure: none.


6.3.7.8.5 Postamble

Pass criteria:

6.3.8 Mode.Active Star.Normal.GoToSleep


This test checks the ability of the active star to go to AS_Sleep mode if all branches
are in Branch_Idle for longer than dStarGoToSleep according to figure 9-4, transition
number 2 in [01-PL Spec] while no stress condition is present.

• Failure: none.

• Stimulate IUTs in nodes 21..24 (branch 2) and 11..14 (branch 4) via host
command to enter BD_Sleep. The IUTs in nodes 1 and 2 remain in
BD_Normal.

• Observe and acquire uBP at TPAS1_B2 of the transmitting branch 2
• Observe and acquire uBM at TPAS1_B2 of the transmitting branch 2


one wake-up pattern, followed by one TSS pattern, followed by one 10Bit
Low pattern.
• Trigger the logic state analyzer to start observation synchronously with the
stimuli at TP_N2_TxEN of node 2.
6.3.8.1.5 Postamble

Pass criteria:

Hint: The period to observe is very long in this test case. But a bit level resolution is
not required. The Go-To-Sleep timeout dStarGoToSleep shall be measured with an
error of less than 1%.
• for at least the first 640ms after the transmission of node 2, uBP and uBM
of branch 2 and 4 shall indicate idle state, i.e. uBP and uBM of branch 2
and 4 shall be between 1800mV and 3200mV (idle). Between 640ms and
64000ms after the transmission of node 2, uBP and uBM of branch 2 and 4
shall change to idle_LP state, i.e. uBP and uBM of branch 2 and 4 shall
change to a voltage level between -200mV and +200mV (idle_LP).
• in case of an available INH1 signal uINH1 shall be initially in logical HIGH
state for at least 640ms. Between 640ms and 64000ms after the start of
the observation, uINH1 shall change to logical LOW state.



number 2 in [01-PL Spec] while ground shift is present.

• Failure: none.

BD_Normal.

Low pattern.


6.3.8.2.5 Postamble

Pass criteria:



LowBat, Failure = 0

number 2 in [01-PL Spec] while low battery voltage is present.

• Failure: none.

BD_Normal.

Low pattern.


6.3.8.3.5 Postamble

Pass criteria:

• uINH1 shall be initially in logical HIGH state for at least 640ms. Between
640ms and 64000ms after the start of the observation, uINH1 shall change

6.3.9 Mode.Active Star.Normal.GoToSleep_Fail


This test checks the ability of the active star to go to AS_Sleep mode if one branch is
in Branch_FailSilent and all other branches are in Branch_Idle for longer than
dStarGoToSleep according to figure 9-4, transition number 2 in [01-PL Spec] while

• Failure: babbling idiot.

• Stimulate IUTs in nodes 1 (branch 1), 21..24 (branch 2) and 2 (branch 3)
via host command to enter BD_Sleep. The IUTs in nodes 11..14 (branch 4)
remain in BD_Normal.

• Observe and acquire uBus at TPAS4_B4 of the receiving branch 4

• Stimulate the bus drivers of nodes 12, 13 and 14 at TP_Nx_TxEN by one

babbling idiot pattern as defined in chapter 6.1.3.1. Repeat this pattern for
at least 64000ms+ 15000µs.
• Trigger the scope to start observation synchronously with the begin of the
babbling idiot stimuli.
begin of the babbling idiot stimuli.
6.3.9.1.5 Postamble

Pass criteria:

Hint: uBP and uBM of branch 2 indicate Data_1 state initially, i.e. the active star
retransmits the babbling idiot pattern before branch 4 enters Branch_FailSilent.
Then, branch 2 enters idle state.
• Between 640ms and 64000ms after branch 2 has entered idle state, i.e.
uBP and uBM of branch 2 are between 1800mV and 3200mV (idle), uBP
and uBM of branch 2 shall change to idle_LP state, i.e. uBP and uBM of
branch 2 and 4 shall change to a voltage level between -200mV and
+200mV (idle_LP).
state for at least 640ms + 1500µs. Between 640ms + 1500µs and
64000ms + 15000µs after the start of the observation, uINH1 shall change







6.3.9.2.5 Postamble

Pass criteria:

+200mV (idle_LP).
64000ms + 15000µs after the start of the observation, uINH1 shall change


LowBat, Failure = 0





6.3.9.3.5 Postamble

Pass criteria:

+200mV (idle_LP).
• uINH1 shall be initially in logical HIGH state for at least 640ms + 1500µs.
Between 640ms + 1500µs and 64000ms + 15000µs after the start of the
observation, uINH1 shall change to logical LOW state.

6.3.10 Mode.Active Star.Low Power.Sleep

Undervoltage VCC, Failure = 0

This test checks the ability of the active star to change its operation mode from
AS_Normal to AS_Sleep in case of an undervoltage on VCC according to figure 9-4,
transition number 3 in [01-PL Spec] while no other stress condition is present.
This test case is skipped if the Functional Class “Active Star - Internal Voltage

o External VCC power supply of active star: +5.0V.
• Failure: none.


• Set external VCC power supply of active star to +2.0V.
• Wait 1000ms (dUV) to let the active star detect the undervoltage condition.


Pass criteria:
• uRxD of nodes 11..14 except the corresponding transmitting node shall
contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active
star shall not disturb the communication on the passive bus (branch 4) and
shall not retransmit patterns received on other branches.
star shall not disturb the communication on the passive star (branch 2) and
• uRxD of nodes 1 and 2 shall be in logical HIGH state during test execution,
i.e. the active star shall not disturb branch 1 and branch 3 and shall not

retransmit patterns received on other branches.
• in case of an available INH1 signal uINH1 shall change to logical LOW
state not later than 1000ms (dUV) after the undervoltage is applied, i.e. the
active star shall enter AS_Sleep.



transition number 3 in [01-PL Spec] while ground shift is present.

• Failure: none.



Pass criteria:



Undervoltage VCC & LowBat, Failure = 0

transition number 3 in [01-PL Spec] while low battery voltage is present.

• VBAT power supply of active star: +5.5V.
• External VCC power supply of active star: +5.0V.
• Failure: none.



Pass criteria:

• uINH1 shall change to logical LOW state not later than 1000ms (dUV) after
the undervoltage is applied, i.e. the active star shall enter AS_Sleep.


Undervoltage VBAT, Failure = 0, VCC = not implemented

AS_Normal to AS_Sleep in case of an undervoltage on VBAT in case of VCC is not
implemented according to figure 9-4, transition number 3 in [01-PL Spec] while no
Control” or the Functional Class “Active Star - Internal Voltage Regulator” is not
implemented and a VCC supply input is available.

• Failure: none.



Pass criteria:




implemented according to figure 9-4, transition number 3 in [01-PL Spec] while

• Failure: none.



Pass criteria:



Undervoltage VCC and VBAT, Failure = 0

AS_Normal to AS_Sleep in case of an undervoltage on VCC and VBAT at the same
time according to figure 9-4, transition number 3 in [01-PL Spec] while no other
stress condition is present.

• Failure: none.


• Set external VCC power supply of active star to +2.0V and set VBAT power
supply of active star to +2.0V.

Pass criteria:





time according to figure 9-4, transition number 3 in [01-PL Spec] while ground shift is
present.

• Failure: none.



Pass criteria:



6.3.11 Mode.Active Star.Low Power.Sleep.Wake-up


This test checks the ability of the active star to wake-up after a wake-up reaction
time of dStarWakeUpReaction and to change the operation mode from AS_Sleep to
AS_Normal according to figure 9-4, transition number 1 in [01-PL Spec] while no

• Failure: none.

• Sleep preamble, step 1-9.
BD_Normal.
• Wait 64000ms to make sure that the AS has entered AS_Sleep.



one wake-up pattern.

Pass criteria:

not required. The wake-up reaction time dStarWakeUpReaction shall be measured
with an error of less than 1%.
• uBP and uBM of branch 2 and 4 shall indicate idle_LP initially, i.e. uBP and
uBM of branch 2 and 4 shall be between -200mV and +200mV (idle_LP).
After the detection of the remote wake-up event, uBP and uBM of branch 2
and 4 shall indicate idle state, i.e. uBP and uBM of branch 2 and 4 shall
change to a voltage level between 1800mV and 3200mV (idle) within
100ms.
• in case of an available INH1 signal uINH1 shall be in logical LOW state
initially. Then, uINH1 shall change to logical HIGH state within 100ms, i.e.
after the detection of the remote wake-up event.



AS_Normal according to figure 9-4, transition number 1 in [01-PL Spec] while ground
shift is present.

• Failure: none.

BD_Normal.




Pass criteria:

100ms.
• in case of an available INH1 signal uINH1 shall be in logical LOW state
initially. Then, uINH1 shall change to logical HIGH state within 100ms, i.e.
after the detection of the remote wake-up event.


LowBat, Failure = 0

AS_Normal according to figure 9-4, transition number 1 in [01-PL Spec] while low

• Failure: none.

BD_Normal.




Pass criteria:

100ms.
• uINH1 shall be in logical LOW state initially. Then, uINH1 shall change to
logical HIGH state within 100ms, i.e. after the detection of the remote
wake-up event.



This test checks the ability of the active star to re-transmit a sufficient number of
received wake-up symbols during the operation mode transition from AS_Sleep to

• Failure: none.


• Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by 32
wake-up patterns, i.e. a sequence of 64 wake-up symbols.

Pass criteria:

• uRxD of all observed nodes shall contain at least 34 wake-up symbols, i.e.
34 logical low sequences corresponding to the wake-up symbols
transmitted by node 2.



shift is present.

• Failure: none.



Pass criteria:



LowBat, Failure = 0


• Failure: none.



Pass criteria:



Standard, Failure = 0, remain in AS_Sleep

with shortend idle phase and to remain in AS_Sleep mode according to section

• Failure: none.
• Communication: Single transmitter.

• Sleep preamble.

TP_AS_INH1 of the AS.

Pass criteria:
this time.

• uINH1 of the AS shall be in logical LOW state (Sleep) during test

execution, i.e. the AS shall remain in AS_Sleep.



with shortend low phase and to remain in AS_Sleep mode according to section

• Failure: none.

• Sleep preamble.


Pass criteria:
this time.





up patterns and to remain in AS_Sleep mode according to section 8.11.1 in [01-PL
Spec] on page 54 while no stress condition is present.

• Failure: none.

• Sleep preamble.


Pass criteria:
this time.



6.3.12 Mode.Active Star.Branch.Active


This test checks the ability of the active star to change its branch mode from
Branch_Idle to Branch_Active according to figure 9-5, transition number 1 in [01-PL

• Failure: none.


• Observe and acquire uBus at TPAS1_By of the transmitting branches
• Trigger the scope synchronously with the stimuli at TP_N2_TxD and


Pass criteria:
node 2, i.e. the active star repeats the patterns received at branch 3 at all
other branches.
• uBus at TPAS1_By of all transmitting branches shall be within idle range at
the beginning of the observation window, i.e. the absolute bus voltage shall
be smaller than 30mV (uBDTxidle) – the branches are in Branch_Idle state.
uBus at TPAS1_By shall exceed idle range within 700ns (dStarDelay +
dStarTruncation = 250ns + 450ns) after uBus at TPAS4_B3 has exceeded
idle range, i.e. all transmitting branches enter Branch_Active.





• Failure: none.



Pass criteria:
other branches.


LowBat, Failure = 0


• Failure: none.



Pass criteria:
other branches.

6.3.13 Mode.Active Star.Branch.Idle

Standard, Failure = 0, Branch_Active

Branch_Active to Branch_Idle according to figure 9-5, transition number 2 in [01-PL

• Failure: none.



Standard postamble.

Pass criteria:
other branches.
• uBus at TPAS1_By of all transmitting branches shall exceed idle range
while the patterns received at branch 3 are retransmitted, i.e. the absolute
bus voltage shall exceed 30mV (uBDTxidle) – the branches are in
Branch_Active state. uBus at TPAS1_By shall re-enter idle range within a
timespan of 300ns to 500ns (dIdleDetectionmin + dStarDelay to

dIdleDetectionmax + dStarDelay = 50ns + 250ns to 250ns + 250ns) after
uBus at TPAS4_B3 has dropped below 30mV (uBDTxidle) again, i.e. the
receiving branch is in idle state again and all transmitting branches re-enter
Branch_Idle after the transmission.


Standard, Failure = 0, Branch_Active


• Failure: none.



Pass criteria:
other branches.



LowBat, Failure = 0, Branch_Active


• Failure: none.



Pass criteria:
other branches.



Standard, Failure = 0, Branch_FailSilent

Branch_FailSilent to Branch_Idle according to figure 9-5, transition number 4 in [01-
PL Spec] while no stress condition is present.



• Observe and acquire uTxEN at TP_N12_TxEN of node 12, TP_N13_TxEN
of node 13 and TP_N14_TxEN of node 14.
babbling idiot pattern as defined in chapter 6.1.3.1.
• After 15000µs from the start of the babbling idiot sequence stimulate IUT in
node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by
one 50/50 pattern.
• 10µs after the end of the babbling idiot sequence stimulate IUT in node 2
at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one
50/50 pattern.


Pass criteria:
• uRxD of all observed nodes except nodes 11..14 (branch 4) shall contain
the 50/50 patterns transmitted by node 2 after 15000µs from the start of
the babbling idiot sequence, i.e. the active star has switched branch 4 to
Branch_FailSilent within the maximal noise detection timeout of
dBranchActivemax = 15000µs and has excluded this branch from
communication.

node 2 after the end of the babbling idiot sequence, i.e. the active star
switches branch 4 back to Branch_Idle within the failure recovery timeout
of dBranchFailSilentIdle ≤ 10µs.


Standard, Failure = 0, Branch_FailSilent

PL Spec] while ground shift is present.



one 50/50 pattern.
50/50 pattern.


Pass criteria:
communication.



LowBat, Failure = 0, Branch_FailSilent

PL Spec] while low battery voltage is present.



one 50/50 pattern.
50/50 pattern.


Pass criteria:
communication.


6.3.14 Mode.Active Star.Branch.FailSilent

Standard, Failure = Babbling Idiot

This test checks the parameter dBranchActive and the ability of the active star to
change its branch mode from Branch_Active to Branch_FailSilent according to figure
9-5, transition number 3 in [01-PL Spec] while no stress condition is present.



• Observe and acquire uBus at TPAS1_B2 of the transmitting branch 2
• Observe and acquire uTxD at TP_N12_TxD of node 12, TP_N13_TxD of
node 13 and TP_N14_TxD of node 14.


Pass criteria:
• uBus of all observed transmitting branches shall change to Data_1 state,
i.e. uBus shall raise above 600mV (uBDTxactive), and shall remain in
Data_1 state for at least 1500µs and not more than 15000µs and shall
return to idle state afterwards, i.e. the absolute bus voltage shall no more
exceed 30mV (uBDTxidle). This means than the active star shall switch
branch 4 from Branch_Active to Branch_FailSilent within the allowed range
of the noise detection timeout of dBranchActivemin = 1500µs to
dBranchActivemax = 15000µs.



Standard, Failure = Babbling Idiot

9-5, transition number 3 in [01-PL Spec] while ground shift is present.





Pass criteria:


LowBat, Failure = Babbling Idiot

9-5, transition number 3 in [01-PL Spec] while low battery voltage is present.




Pass criteria:

6.3.15 Failure.Loss

Standard, Loss of VCC

This test checks the behaviour of the active star in case of loss of the VCC supply
power if VBAT is still available according to section 9.2.3 Active star – power supply
interface in [01-PL Spec] while no other stress condition is present.

• Failure: loss of VCC.


• Interrupt supply wire VCC of the active star according to chapter 3.5.
• Wait 1000ms (dUV) to let the active star detect the loss of VCC
(undervoltage condition).

Pass criteria:


• uRxD of nodes 1 and 2 shall be in logical HIGH state if other nodes are
stimulated to transmit, i.e. the active star shall not disturb branch 1 and
branch 3 and shall not retransmit patterns received on other branches.
the loss of VCC, i.e. the active star shall enter AS_Sleep.


Standard, Loss of VCC, VBAT not implemented

This test checks the behaviour of the active star in case of loss of the VCC supply
power if VBAT is not implemented according to section 9.2.3 Active star – power
supply interface in [01-PL Spec] while no other stress condition is present.
Control” is implemented and a VBAT supply input is available.

• Failure: loss of VCC.


• Interrupt supply wire VCC of the active star according to chapter 3.5.
• Wait 1000ms (dUV) to let the active star detect the loss of VCC.

Pass criteria:



Standard, Loss of VBAT

This test checks the behaviour of the active star in case of loss of the VBAT supply
power if VCC is still available according to section 9.2.3 Active star – power supply
interface in [01-PL Spec] while no other stress condition is present.

• Failure: loss of VBAT.


• Interrupt supply wire VBAT of the active star according to chapter 3.5.
33


Pass criteria:


Standard, Loss of VBAT, VCC not implemented

This test checks the behaviour of the active star in case of loss of the VBAT supply
power if VCC is not implemented according to section 9.2.3 Active star – power
supply interface in [01-PL Spec] while no other stress condition is present.
Regulator” is not implemented or a VCC supply input is although available.

• Failure: loss of VBAT.


• Interrupt supply wire VBAT of the active star according to chapter 3.5.
• Wait 1000ms (dUV) to let the active star detect the loss of VBAT.

Pass criteria:


• uINH1 shall break down to logical LOW state after the loss of VBAT, i.e. the
active star shall shut down.


Standard, Loss of VBAT and VCC

This test checks the behaviour of the active star in case of loss of the VCC and VBAT
supply power if both supply inputs are available according to section 9.2.3 Active star
– power supply interface in [01-PL Spec] while no other stress condition is present.

• Failure: loss of VCC and VBAT.


• Interrupt supply wires VCC and VBAT of the active star according to chapter
3.5.
• Wait 1000ms (dUV) to let the active star detect the loss of VCC and VBAT.

Pass criteria:


• uINH1 shall break down to logical LOW state after the loss of VCC and
VBAT, i.e. the active star shall shut down.





• Switch GND connection of all IUTs in the AS to unconnected according to

• Observe and acquire uBus at TPAS1_B1 of the transmittng branch of the
AS according to the observation window described in chapter 5.1.4.2.
• Observe and acquire uBus at TPAS1_B3 of the receiving branch of the AS
• Stimulate node 2 at TP_N2_TxD and TP_N2_TxEN by one wake-up

Pass criteria:

• the AS shall ignore the incoming data stream and shall signal Idle to the
bus.
• uBus of branch 1 of the AS shall be in idle range |uBus|<30mV.


Standard, Failure GND of Node unconnected

connection of the whole AS according to table 8-25 in [01-PL Spec].

• Failure: GND of node unconnected.

• Switch GND connection of whole AS to unconnected according to Figure
3-9 and Table 3-4, failure FL16.

• Observe and acquire uBus at TPAS1_B1 of the AS.
• Observe and acquire uBus at TPAS1_B3 of the AS.

Pass criteria:
bus.



AS_Normal, tr1 ramp

according to chapter 3.4 in AS_Normal mode.
Hint: This test case intends to test the capability of the active star to return to the

input voltage of the VCC voltage regulator (the battery voltage) is stressed by the
dynamic low battery voltage pulse.
o VBAT power supply of active star: 11.6V.
• Failure: none.


wake-up pattern.


TSS pattern, followed by one 50/50 pattern. Repeat this sequence. At least
one more sequence shall be transmitted after the end of the dynamic low
battery voltage pulse.

Pass criteria:

voltage regulator is present:
uTxD and uTxEN of all nodes), i.e. all data shall be retransmitted by
the active star.
o in case of an available INH1 signal uINH1 of the active star shall be
in logical HIGH.


AS_Normal, tr6 ramp

according to chapter 3.4 in AS_Normal mode.

• Failure: none.


wake-up pattern.

TSS pattern, followed by one 50/50 pattern. Repeat this sequence. At least
one more sequence shall be transmitted after the end of the dynamic low
battery voltage pulse.

Pass criteria:

uTxD and uTxEN of all nodes), i.e. all data shall be retransmitted by
the active star.
in logical HIGH.

6.3.16.3 Standard environment, Ground Shift = 0, Failure = 0, AS_Sleep,

tr1 ramp

according to chapter 3.4 in AS_Sleep mode.

• Failure: none.

• Sleep preamble.
• Stimulate bus drivers in all nodes via host command to enter BD_Sleep.

• Observe and acquire uBP at TPASx_B2 of branch 2 according to the
• Observe and acquire uBM at TPASx_B2 of branch 2 according to the


• Trigger the dynamic low battery voltage pulse.
• Trigger scope observation synchonously with the dynamic low battery
voltage pulse.

Pass criteria:

o uBP and uBM of branch 2 and 4 shall be in idle_LP state, i.e. shall
have a voltage level between -200mV and +200mV (idle_LP).
in logical LOW.

6.3.16.4 Standard environment, Ground Shift = 0, Failure = 0, AS_Sleep,

tr6 ramp

according to chapter 3.4 in AS_Sleep mode.

• Failure: none.

• Sleep preamble.
• Stimulate bus drivers in all nodes via host command to enter BD_Sleep.



• Trigger the dynamic low battery voltage pulse.
• Trigger scope observation synchonously with the dynamic low battery
voltage pulse.

Pass criteria:

o uBP and uBM of branch 2 and 4 shall be in idle_LP state, i.e. shall
have a voltage level between -200mV and +200mV (idle_LP).
in logical LOW.

6.3.17 Failure.Short Circuit Bus Wires

Standard, Failure = S/C BP to GND


• Failure: S/C BP to GND.


• Observe and acquire iBPGNDShortMax at TP_AS_B1_RiBP of the AS (shall be
at TPAS1_B1).
• Short circuit BP (failure FL11) of the AS to GND at TPAS2_B1.
• Stimulate the bus driver of the transmitting node 2 at TP_N2_TxD and
TP_N2_TxEN by 166 short circuit pattern according to chapter 5.1.3.9 after
the short circuit of the bus wire.


Pass criteria:
• iBPGNDShortMax ≤ 100mA.


Standard, Failure = S/C BM to GND


• Failure: S/C BM to GND.


• Observe and acquire iBMGNDShortMax at TP_AS_B1_RiBM of the AS (shall be
at TPAS1_B1).
• Short circuit BM (failure FL12) of the AS to GND at TPAS2_B1.

Pass criteria:

• iBMGNDShortMax ≤ 100mA.


Standard, Failure = S/C BP to +48V


• Failure: S/C BP to +48V34.


• Observe and acquire iBPBAT48ShortMax35 or iBPBAT27ShortMax36 at
TP_AS_B1_RiBP of the AS (shall be at TPAS1_B1).
• Short circuit BP (failure FL13) of the AS to +48V34 at TPAS2_B1.
34
In case the IUT does not support 42V systems the VBAT shall be +27V
35
In case the IUT does support 42V systems
36
In case the IUT does not support 42V systems

• Switch off short circuit BP (failure FL13) of the AS at TPAS2_B1. Wait 12

seconds.

Pass criteria:

• In case the IUT does not support 42V systems: iBPBAT27ShortMax ≤ 100mA.
• In case the IUT does support 42V systems: iBPBAT48ShortMax ≤ 120mA.
• After switching off the failure the IUT in node 1 must receive the patterns
and signal them at TP_N1_RxD and TP_N1_RxEN that are stimulated at


Standard, Failure = S/C BM to +48V

This test case is skipped if the IUT shall not be used in 42V systems.
•

In case that only VCC is implemented:
• Failure: S/C BM to +48V34.


• Observe and acquire iBMBAT48ShortMax35 or iBMBAT27ShortMax36 at
TP_AS_B1_RiBM of the AS (shall be at TPAS1_B1).
• Short circuit BM (failure FL14) of the AS to +48V34 at TPAS2_B1.
• Switch off short circuit BM (failure FL14) of the AS at TPAS2_B1. Wait 12
seconds.



Pass criteria:
• In case the IUT does not support 42V systems: iBMBAT27ShortMax ≤ 100mA.
• In case the IUT does support 42V systems: iBMBAT48ShortMax ≤ 120mA.



transmitter, Power Supply = Standard, Failure = 0

This test checks the ability of the AS to receive a test pattern while dynamic ground
shift is present at the transmitter.

• Failure: None.


TP_N23_TxEN by one wake-up pattern as described in chapter 5.1.3.1,
followed by one TSS pattern, followed by ten 50/50 patterns. Trigger the
dynamic ground shift curve synchronously with the first rising edge after
the TSS pattern.

Pass criteria:
• All observed nodes shall receive all 50/50 patterns after the trigger event in
uRxD at TP_Nx_RxD equal to the pattern in uTxD of node 23, i.e. the
dynamic ground shift at node 23 shall not disturb the communication.

6.3.18.2 Standard environment, Ground Shift = dynamic at the AS,


This test checks the ability of the IUT to receive and re-transmit a test pattern while
dynamic ground shift is present.

• Ground shift: Dynamic at the AS.
• Failure: None.


the TSS pattern.

Pass criteria:

• All observed nodes shall receive all 50/50 patterns after the trigger event in
uRxD at TP_Nx_RxD equal to the pattern in uTxD of node 23, i.e. the
dynamic ground shift at node 23 shall not disturb the communication.

6.3.18.3 Standard environment, Ground Shift = dynamic at the receiver,


This test checks the ability of the IUT to receive and transmit a test pattern while
dynamic ground shift is present.

• Failure: None.


the TSS pattern.

Pass criteria:
• node 23 shall receive all 50/50 patterns after the trigger event in uRxD of
node 23 equal to the pattern in uTxD of node 2, i.e. the dynamic ground
shift at node 23 shall not disturb the communication.
• no error shall be signaled via the host interface of node 23 and node 2.

6.3.19 Eye Diagram


This test checks the eye diagram at the receiver according to the eye diagram
chapter 7.4 in [01-PL Spec].
In this test case the bandwidth of the oscilloscope shall be limited to 20MHz.

• Failure: none.


• Limit the bandwidth of the oscilloscope to 20MHz.
• Observe and acquire uBus at TPAS4_B3 of the AS according to the
TP_N2_TxEN by one TSS pattern, followed by ten 50/50 patterns.


Pass criteria:
• The eye diagram obtained with the observed and acquired uBus signal at
TPAS4_B3 of the AS shall not violate the mask of TP4 defined in Figure 7-
4 in [01-PL Spec].

6.4 Test Procedures
6.4.1 Delay

PatternGenerator.IPatternGenerator.CreateComposedPattern() **
PatternGenerator.IPatternGenerator.CreateParticularPattern() **

*** Some test cases require particular patterns, the other ones standard patterns.
Figure 6-16: Test Procedure for Delay Test Cases

6.4.2 Truncation
Scope.IConfiguration.Configure() **

Scope.IConfiguration.Acquisition() **
Scope.IConfiguration.Channel() **
Scope.IConfiguration.Trigger() **
Scope.IAcquireBusData.Initiate() **
Scope.AcquireBusData.GetWaveform() **
Scope.AcquireBusData.ObtainParameter() **

*** Test cases with oscilloscope acquisition, only.
Figure 6-17: Test Procedure for Truncation Test Cases

6.4.3 Mode

PatternGenerator.IPatternGenerator.CreateParticularPattern() ***
Scope.IConfiguration.Configure() ****
Scope.IConfiguration.Acquisition() ****
Scope.IConfiguration.Channel() ****
Scope.IConfiguration.Trigger() ****
Scope.IAcquireBusData.Initiate() ****
PowerSupply_ALT_VBAT.IDCPowerSupplyConfig.Output() *****
PowerSupply_ALT_VCC.IDCPowerSupplyConfig.Output() *****
Scope.AcquireBusData.GetWaveform() ****
Scope.AcquireBusData.ObtainParameter() ****
****** Test cases with alternative power supply configuration, only.

****** Test cases with ground shift, only.
****** Some test cases require particular patterns, the other ones standard patterns.
****** Test cases with oscilloscope acquisition, only.
****** Test cases with alternative power supply output change during test execution, only.

6.4.4 Failure
NetServices.ISwitch.SetInterruptionOnBoard()


PatternGenerator.IPatternGenerator.Configure() **
PatternGenerator.IPatternGenerator.CreateComposedPattern() **
Scope.IConfiguration.Configure() ***

Scope.IConfiguration.Acquisition() ***
Scope.IConfiguration.Channel() ***
Scope.IConfiguration.Trigger() ***
LogicAnalyzer.ILogicAnalyzer.Configure() ****
Scope.IAcquireBusData.Initiate() ***
NetServices.IControl.SetOperatingMode() *****
Scope.AcquireBusData.GetWaveform() ***
Scope.AcquireBusData.ObtainParameter() ***
***** Test cases with alternative power supply configuration, only.

***** Required for setup state in some test cases, only.
***** Test cases with oscilloscope acquisition, only.
***** In some test cases required for observation of pattern generator, only.
***** Test cases with op-mode change during test execution, only.
Figure 6-20: Test Procedure for Dynamic Low Battery Test Cases

7 Test Cases for AS with CC Interface within a

homogeneous Topology
These test cases apply to active stars with communication controller interface or bus
guardian interface, only. This test case chapter is skipped if neither the Functional
Class “Active Star - Communication Controller Interface” nor the Functional Class
“Active Star - Bus Guardian Interface” is implemented.
7.1 Configuration
7.1.1 Topology

The topology corresponds to chapter 6.1.1.
7.1.2 Test Planes

The test planes at the FlexRay active star for analog signal measurement are
specified as:
Transmitter Active Star Receiver

Transmitting Branch
Receiving Branch
BD AS BD
TPAS3_By TPAS4_By TPAS1_By TPAS2_By
Figure 7-1: Test Planes @ the analog Interface
TPAS1_By37 uBus Differential bus signal of the transmitting branch, as close

as possible to the IUT
37
y stands for the number of the branch of the AS

TPAS4_By37 uBus Differential bus signal of the receiving branch, as close

as possible to the IUT
Table 7-1: Test Planes @ the analog Interface

The naming of the branches corresponds to chapter 6.1.2.1.

The test planes at the FlexRay active star for digital signals are specified as:

TxEN
TxD
RxEN
RxD
BGE
INH1 IUT
Figure 7-2: Test Planes @ Digital Interfaces of the Active Star for the Logic
Analyzer
TP_AS_TxD TxD Transmit Data signal of the IUT
TP_AS_TxEN TxEN Transmit Enable Not signal of the IUT
TP_AS_RxD RxD Receive Data signal of the IUT
TP_AS_BGE BGE Bus Guardian Enable signal of the IUT (optional)
TP_AS_RxEN RxEN Receive Enable Not signal of the IUT (optional)
TP_AS_INH1 INH1 Inhibit signal of the IUT (optional)
Table 7-2: Test Planes @ Digital Interfaces of the Active Star for the Logic
Analyzer
7.1.2.3 Naming Convention

This chapter corresponds to chapter 5.1.2.3 where “Nx” shall be read as “AS”.

7.1.2.4 Test Planes for the Oscilloscope

The oscilloscope observes the following test planes:
• TP_AS_RxD
• TPAS1_By37
• TPAS4_By37
• TP_AS_GND (local ground of the AS)
7.1.3 Test Patterns

This chapter corresponds to chapters 5.1.3 and 6.1.3.

This chapter corresponds to chapter 5.1.3.10 where “BD” shall be read as “AS”.

This chapter corresponds to chapter 6.1.5.

7.1.7 Stress
7.1.8 Failures
Failures of the AS are also described in chapter 3.5.

The following features are optional as specified in [01-PL Spec] and must be tested
7.1.9.1 Functional Class “Active Star - Communication Controller

Interface”
o Signal RxD
o Signal TxD
o Signal TxEN
7.1.9.2 Functional Class “Active Star - Bus Guardian Interface”


o Signal RxEN
o Signal BGE
7.1.9.3 Functional Class “Active Star - Voltage Regulator Control”

o Signal INH1
o Power supply input VBAT
7.1.9.4 Functional Class “Active Star - Internal Voltage Regulator”


supply input and requires that the AS is fully operational without a VCC
supply.

Matrix F: (round robin test only with terminated node):
In some test instances it is necessary that every terminated node and the AS are the
transmitter and all other terminated nodes and the AS are the receivers.
This matrix is used for observation of bus signals.
Message from Node x and AS
Transmitters 1 2 AS 12 23
t
Receivers *) *) *) *) *)
*) all terminated nodes except the transmitter

t
Figure 7-3: Communication Matrix F

Pause between the messages: 20µs.
Active Star as transmitter:

In some test instances it is necessary that the AS is the transmitter (digital interface)
and all other terminated nodes are the receivers.
This communication is used for testing the digital interface.

Message from Node
Transmitter AS
t
Receivers All
Figure 7-4: Communication Active Star as transmitter (Timing)

1
Transmitter
11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Figure 7-5: Communication Active Star as transmitter (Topology)
Single Transmitter
In some test cases only one transmitter is required to stimulate one receiving branch
of the active star:

11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Transmitter

Figure 7-6: Communication Single Transmitter
Node 1 and AS as Transmitter

In some test cases node 1 and the AS are required for collision scenarios in the AS:
Message
AS,
Transmitters
N1
t
Receivers All
Figure 7-7: Communication Node 1 and AS (Timing)
Transmitters
11
PS 2 AS 4
24 23 22 21 2 14 13 12 11

Figure 7-8: Communication Node 1 and AS (Topology)
In this communication node 23 is the transmitter.
Message from Node
Transmitter 23

11
PS 2 AS 4
24 23 22 21 2 14 13 12 11
Transmitter

the configuration.
all nodes.



the configuration.
all nodes.
8. Wait 64000ms to make sure that the AS enters AS_Sleep.
7.1.13 Services
Services correspond to chapter 5.1.17.

test is failed.
1. dRxAsym Communication. Receiver delay 5 ns

Delay mismatch
2. dStarRx10 Communication. Receiver delay, 100 ns

Delay positive edge
3. dStarRx01 Communication. Receiver delay, 100 ns

Delay negative edge
4. dStarRxai Communication. Idle reaction time 50 400 ns

Timing

5. dStarRxia Communication. Activity reaction time 100 450 ns

Timing
6. dTxAsym Communication. Transmitter delay 4 ns

Delay mismatch
7. dStarTx10 Communication. Transmitter delay, 100 ns

Delay positive edge
8. dStarTx01 Communication. Transmitter delay, 100 ns

Delay negative edge
38
9. dStarTxai Communication. Propagation delay 400 ns
Delay active idle

26
10. dStarTxia Communication. Propagation delay 450 ns
Delay idle active
11. dBusTxai 26 Communication. Transition time 30 ns

Signal Shape active idle
12. dBusTxia 26 Communication. Transition time 30 ns

Signal Shape idle active
13. dBusTx01 26 Communication. Rise time differential 5 25 ns

(10% 90%)
14. dBusTx10 26 Communication. Fall time differential 5 25 ns

(90% 10%)
15. uASTxactive 26 Communication. Absolute differential 600 2000 mV

Signal Shape voltage while sending
16. uASTxidle 26 Communication. Absolute differential 0 30 mV

Signal Shape voltage while Idle
17. uVDIG-OUT-HIGH Communication. Threshold for 0.8xuVDIG 39 0.8xuVDIG 20 -

output, when in
logical high state
18. uVDIG-OUT-LOW Communication. Threshold for 0.8xuVDIG 20 -

output, when in
logical low state
38
39
In case a reference voltage for digital IO is available via a VIO pin, then uVDIG = uVIO, otherwise
uVDIG= uVCC

19. uVDIG-IN-HIGH Communication. Threshold for 0.8xuVDIG 20 -

input as on logical
high
20
20. uVDIG-IN-LOW Communication. Threshold for 0.8xuVDIG -
input as on logical low
21. VBAT for Power Supply Battery voltage 7 V

WU detector required for wake-up
detector operation
22. VBAT monitoring Power Supply Transition to low 2 5.5 V

power when voltage
falls below product
specific threshold
23. VCC monitoring Power Supply Transition to low 2 Product V

power when voltage specific
falls below product
specific threshold
24. dUV Power Supply Reaction time for 1000 ms

undervoltage
detection

7.3 Test Cases
7.3.1 Communication.Delay.dStarTx01


This test checks the transmitter delay dStarTx01 from low to high according to figure

• Failure: none.
• Communication: Active Star as transmitter.


• Observe and acquire uTxD at TP_AS_TxD of the active star according to
the observation window described in chapter 5.1.4.1.
• Observe and acquire uBus at TPAS1_B2 of the active star according to the
• Stimulate IUT (the active star) at TP_AS_TxD and TP_AS_TxEN by one
pattern.
7.3.1.1.5 Postamble


Pass criteria:
• dStarTx01 ≤ 100ns.



8-8 in [01-PL Spec] while ground shift at the transmitter (AS) is present.

• Failure: none.


pattern.
7.3.1.2.5 Postamble

Pass criteria:





8-8 in [01-PL Spec] while ground shift at a receiver is present.

• Failure: none.


pattern.
7.3.1.3.5 Postamble

Pass criteria:




LowBat, Failure = 0


• Failure: none.


pattern.
7.3.1.4.5 Postamble

Pass criteria:


Standard, Failure = 0, Min Bus Load




pattern.
7.3.1.5.5 Postamble

Pass criteria:



Standard, Failure = 0, Max Bus Load




pattern.
7.3.1.6.5 Postamble

Pass criteria:


7.3.2 Communication.Delay.dStarTx10


This test checks the transmitter delay dStarTx10 from high to low according to figure

• Failure: none.


pattern.
7.3.2.1.5 Postamble

Pass criteria:




8-8 in [01-PL Spec] while ground shift at the transmitter (AS) is present.

• Failure: none.


pattern.
7.3.2.2.5 Postamble

Pass criteria:





8-8 in [01-PL Spec] while ground shift at a receiver is present.

• Failure: none.


pattern.
7.3.2.3.5 Postamble

Pass criteria:




LowBat, Failure = 0


• Failure: none.


pattern.
7.3.2.4.5 Postamble

Pass criteria:






pattern.
7.3.2.5.5 Postamble

Pass criteria:







pattern.
7.3.2.6.5 Postamble

Pass criteria:


7.3.3 Communication.Delay.dTxAsym


parameters dStarTx01 (chapter 7.3.1.1) and dStarTx10 (chapter 7.3.2.1) according
to figure 8-8 in [01-PL Spec] while no stress condition is present.



• Calculation of |dStarTx10-dStarTx01| as measured in the test cases above.
7.3.3.1.5 Postamble

Pass criteria:
• |dStarTx10-dStarTx01| ≤ 4ns.



to figure 8-8 in [01-PL Spec] while ground shift at the transmitter (AS) is present.


7.3.3.2.5 Postamble

Pass criteria:



to figure 8-8 in [01-PL Spec] while ground shift at a receiver is present.


7.3.3.3.5 Postamble

Pass criteria:


Bat, Failure = 0

to figure 8-8 in [01-PL Spec] while low battery voltage is present.



7.3.3.4.5 Postamble

Pass criteria:



to figure 8-8 in [01-PL Spec] while minimal bus load is present.


7.3.3.5.5 Postamble

Pass criteria:



to figure 8-8 in [01-PL Spec] while maximal bus load is present.


7.3.3.6.5 Postamble

Pass criteria:

7.3.4 Communication.Delay.dStarRx01


This test checks the receiver delay dStarRx01 from low to high according to figure 8-
6 in [01-PL Spec] while no stress condition is present.

• Failure: none.


• Observe and acquire uTxEN at TP_N23_TxD of node 23.
• Observe and acquire uRxD at TP_AS_RxD of the active star according to
• Stimulate the bus driver in node 23 at TP_N23_TxD and TP_N23_TxEN by
one wake-up pattern, followed by one TSS pattern, followed by one 50/50
pattern.
7.3.4.1.5 Postamble


Pass criteria:
• dStarRx01 ≤ 100ns.



6 in [01-PL Spec] while ground shift at the transmitter is present.

• Failure: none.


pattern.
7.3.4.2.5 Postamble

Pass criteria:




6 in [01-PL Spec] while ground shift at a receiver (AS) is present.

• Failure: none.


pattern.
7.3.4.3.5 Postamble

Pass criteria:



LowBat, Failure = 0

6 in [01-PL Spec] while low battery voltage is present.

• Failure: none.


pattern.
7.3.4.4.5 Postamble

Pass criteria:




6 in [01-PL Spec] while minimal bus load is present.


• Switch bus load at the AS to the minimum value as described in FL7.

pattern.
7.3.4.5.5 Postamble

Pass criteria:



6 in [01-PL Spec] while maximal bus load is present.


• Switch bus load at the AS to the maximum value as described in FL8.

pattern.
7.3.4.6.5 Postamble

Pass criteria:

7.3.5 Communication.Delay.dStarRx10


6 in [01-PL Spec] while no stress condition is present.

• Failure: none.


pattern.
7.3.5.1.5 Postamble


Pass criteria:



6 in [01-PL Spec] while ground shift at the transmitter is present.

• Failure: none.


pattern.
7.3.5.2.5 Postamble

Pass criteria:




6 in [01-PL Spec] while ground shift at the receiver (AS) is present.

• Failure: none.


pattern.
7.3.5.3.5 Postamble

Pass criteria:



LowBat, Failure = 0

6 in [01-PL Spec] while low battery voltage is present.

• Failure: none.


pattern.
7.3.5.4.5 Postamble

Pass criteria:




6 in [01-PL Spec] while minimal bus load is present.


• Switch bus load at the AS to the minimum value as described in FL7.

pattern.
7.3.5.5.5 Postamble

Pass criteria:



6 in [01-PL Spec] while maximal bus load is present.


• Switch bus load at the AS to the maximum value as described in FL8.

pattern.
7.3.5.6.5 Postamble

Pass criteria:

7.3.6 Communication.Delay.dRxAsym


parameters dStarRx01 (chapter 7.3.4.1) and dStarRx10 (chapter 7.3.5.1) according
to figure 8-6 in [01-PL Spec] while no stress condition is present.



• Calculation of |dStarRx10-dStarRx01| as measured in the test cases
above.
7.3.6.1.5 Postamble

Pass criteria:
• |dStarRx10-dStarRx01| ≤ 5ns.



to figure 8-6 in [01-PL Spec] while ground shift at the transmitter is present.


above.
7.3.6.2.5 Postamble

Pass criteria:



to figure 8-6 in [01-PL Spec] while ground shift at the receiver (AS) is present.


above.
7.3.6.3.5 Postamble

Pass criteria:


Bat, Failure = 0

to figure 8-6 in [01-PL Spec] while low battery voltage is present.



above.
7.3.6.4.5 Postamble

Pass criteria:



to figure 8-6 in [01-PL Spec] while minimal bus load is present.


above.
7.3.6.5.5 Postamble

Pass criteria:



to figure 8-6 in [01-PL Spec] while maximal bus load is present.


above.
7.3.6.6.5 Postamble

Pass criteria:

7.3.7 Mode.Active Star.Normal


footnote (**) in [01-PL Spec] while no other stress condition is present. Additionally,
the behaviour at the local communication controller interface and, if available, the
local bus guardian interface is verified.

• External VBAT power supply of active star: default.
• Failure: none.
• Communication: matrix F (round robin including AS).


• Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23.
• Observe and acquire uTxD at TP_AS_TxD of the active star.
• Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23.
• Observe and acquire uTxEN at TP_AS_TxEN of the active star.
• Observe and acquire uRxD at TP_AS_RxD of the active star.
TP_AS_RxEN of the active star.
• Stimulate the bus drivers and the IUT (active star) according to the
sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN

by one TSS pattern, followed by ten40 10Bit Low patterns. Repeat this
sequence for at least 1000ms to verify that communication is not disturbed
even after the maximal undervoltage detection timeout (dUV).
7.3.7.1.5 Postamble

Pass criteria:
• uRxD of all nodes shall contain all logical LOW sequences transmitted by

the active star, i.e. the active star shall not enter AS_Sleep mode and shall
transmit all patterns received on the local communication controller
interface.
• uRxD of the active star shall contain all logical LOW sequences transmitted
by node 1, 2, 12 and 23, i.e. the active star shall not enter AS_Sleep mode
and shall signal all patterns received on all branches at the local
communication controller interface.
• uINH1 of the active star shall be in logical HIGH state during test
execution, i.e. the active star shall not enter AS_Sleep.
• in case of an available RxEN signal uRxEN of the active star shall be in
logical HIGH state before the first node according to the sequence
described on matrix F is stimulated (falling edge of uTxD and uTxEN of
node 1) and shall be in logical LOW state while uRxD of the active star
40



footnote (**) in [01-PL Spec] while ground shift is present. Additionally, the behaviour
at the local communication controller interface and, if available, the local bus
guardian interface is verified.

• Failure: none.



by one TSS pattern, followed by ten41 10Bit Low patterns. Repeat this
sequence for at least 1000ms to verify that communication is not disturbed
even after the maximal undervoltage detection timeout (dUV).
7.3.7.2.5 Postamble

Pass criteria:
• uRxD of all nodes shall contain all logical LOW sequences transmitted by

the active star, i.e. the active star shall not enter AS_Sleep mode and shall
transmit all patterns received on the local communication controller
interface.
• uRxD of the active star shall contain all logical LOW sequences transmitted
by node 1, 2, 12 and 23, i.e. the active star shall not enter AS_Sleep mode
and shall signal all patterns received on all branches at the local
communication controller interface.
execution, i.e. the active star shall not enter AS_Sleep.
described on matrix F is stimulated (falling edge of uTxD and uTxEN of
node 1) and shall be in logical LOW state while uRxD of the active star
41



of VBAT and VCC while no stress condition is present.

• Failure: none.
• Communication: AS as transmitter.


• Observe and acquire uTxD at TP_AS_TxD of the AS.
• Observe and acquire uTxEN at TP_AS_TxEN of the AS.
• Observe and acquire uINH1 at TP_AS_INH1.
• Stimulate the AS at TP_AS_TxD and TP_AS_TxEN by one TSS pattern,
7.3.7.3.5 Postamble

Pass criteria:
the AS, i.e. the active star shall enter AS_Normal mode after power on and
transmit the test patterns of the AS.





of VBAT and VCC while ground shift is present.

• Failure: none.


7.3.7.4.5 Postamble

Pass criteria:





of VCC while no stress condition is present.

• Failure: none.


7.3.7.5.5 Postamble

Pass criteria:
transmit the test patterns.



of VCC while ground shift is present.

• Failure: none.


7.3.7.6.5 Postamble

Pass criteria:
transmit the test patterns.


Standard, Failure = 0, VBAT implemented

of VBAT while no stress condition is present.

• Failure: none.


7.3.7.7.5 Postamble

Pass criteria:


Standard, Failure = 0, VBAT implemented

of VBAT while ground shift is present.

• Failure: none.


7.3.7.8.5 Postamble

Pass criteria:

7.3.8 Mode.Active Star.Normal.GoToSleep


number 2 in [01-PL Spec] while no stress condition is present. Additionally, the
behaviour at the local communication controller interface and, if available, the local
bus guardian interface is verified.

• Failure: none.


• Stimulate the IUT (AS) at TP_AS_TxD and TP_AS_TxEN by one wake-up
pattern, followed by one TSS pattern, followed by one 10Bit Low pattern.
stimuli at TP_AS_TxEN of the active star.

7.3.8.1.5 Postamble

Pass criteria:
• uRxD of the active star shall be in logical HIGH state after the stimuli at
uTxD and uTxEN and during the rest of the test execution.
• in case of an available INH1 signal uINH1 shall initially be in logical HIGH

logical HIGH state after the stimuli at uTxD and uTxEN and during the rest
of the test execution.



number 2 in [01-PL Spec] while ground shift is present. Additionally, the behaviour at
the local communication controller interface and, if available, the local bus guardian
interface is verified.

• Failure: none.


7.3.8.2.5 Postamble


Pass criteria:



LowBat, Failure = 0

number 2 in [01-PL Spec] while low battery voltage is present. Additionally, the

• Failure: none.


7.3.8.3.5 Postamble


Pass criteria:
• uINH1 shall initially be in logical HIGH state for at least 640ms. Between
640ms and 64000ms after the start of the observation, uINH1 shall change


7.3.9 Mode.Active Star.Normal.GoToSleep_Fail


no stress condition is present. Additionally, the behaviour at the local communication
controller interface and, if available, the local bus guardian interface is verified.



7.3.9.1.5 Postamble


Pass criteria:
• uRxD of the active star shall be in logical LOW state for at least 1500µs
initially, i.e. the active star signals the babbling idit pattern received at
branch 4 on the local communication controller interface.
• uRxD of the active star shall change to logical HIGH state between 1500µs
and 15000µs after the start of the babbling idiot sequence. Then, uRxD of

the active star shall remain in logical HIGH state during test execution, i.e.
branch 4 is excluded from communication by the active star after the noise
detection timeout dBranchActive.
logical LOW state for at least 1500µs initially, i.e. the active star signals the
babbling idiot pattern received at branch 4 on the local communication
controller interface.
• in case of an available RxEN signal uRxEN of the active star shall change
to logical HIGH state between 1500µs and 15000µs after the start of the
babbling idiot sequence. Then, uRxD of the active star shall remain in
logical HIGH state during test execution, i.e. branch 4 is excluded from
communication by the active star after the noise detection timeout
dBranchActive.
64000ms + 15000µs after the start of the babbling idiot sequence, uINH1
shall change to logical LOW state, i.e. the active star shall enter AS_Sleep
mode if all branches are in Branch_Idle or Branch_FailSilent for
dStarGoToSleep.



ground shift is present. Additionally, the behaviour at the local communication



7.3.9.2.5 Postamble


Pass criteria:

dBranchActive.
64000ms + 15000µs after the start of the babbling idiot sequence, uINH1
shall change to logical LOW state, i.e. the active star shall enter AS_Sleep
mode if all branches are in Branch_Idle or Branch_FailSilent for
dStarGoToSleep.


LowBat, Failure = 0

low battery voltage is present. Additionally, the behaviour at the local communication



7.3.9.3.5 Postamble

Pass criteria:

dBranchActive.
• uINH1 shall initially be in logical HIGH state for at least 640ms + 1500µs.
Between 640ms + 1500µs and 64000ms + 15000µs after the start of the
babbling idiot sequence, uINH1 shall change to logical LOW state, i.e. the
active star shall enter AS_Sleep mode if all branches are in Branch_Idle or
Branch_FailSilent for dStarGoToSleep.

7.3.10 Mode.Active Star.Low Power.Sleep


transition number 3 in [01-PL Spec] while no other stress condition is present.
Additionally, the behaviour at the local communication controller interface and, if
available, the local bus guardian interface is verified.

• Failure: none.


• Observe and acquire uRxD at TP_Nx_RxD of nodes 1, 2, 12 and 23.

by one TSS pattern, followed by one 50/50 pattern.

Pass criteria:
VCC voltage at the IUTs (ASs) supply input has dropped to +2.0V. Adaptation of

thresholds for digital signals may be required.
• uRxD of nodes 1, 2, 12, 23 shall not contain the 50/50 patterns transmitted
by the active star, i.e. the active star shall not retransmit patterns received
on the local communication controller interface.
• uRxD of of the active star shall not contain the 50/50 patterns transmitted
by nodes 1, 2, 12 and 23, i.e. the active star shall not signal patterns
received on any branch to the local communication controller interface.
described on matrix F is stimulated to transmit. After stimulation, uRxEN
may change to logical LOW state (bus activity may be detected as wake-
up event).



transition number 3 in [01-PL Spec] while ground shift is present. Additionally, the

• Failure: none.




Pass criteria:

up event).


Undervoltage VCC & LowBat, Failure = 0

transition number 3 in [01-PL Spec] while low battery voltage is present. Additionally,
the behaviour at the local communication controller interface and, if available, the
local bus guardian interface is verified.

• VBAT power supply of active star: +5.5V.
• Failure: none.




Pass criteria:

up event).



implemented according to figure 9-4, transition number 3 in [01-PL Spec] while no
other stress condition is present. Additionally, the behaviour at the local
communication controller interface and, if available, the local bus guardian interface
is verified.

• Failure: none.




Pass criteria:
VBAT voltage at the IUTs (ASs) supply input has dropped to +2.0V. Adaptation of

up event).



implemented according to figure 9-4, transition number 3 in [01-PL Spec] while
ground shift is present. Additionally, the behaviour at the local communication

• Failure: none.




Pass criteria:
VBAT voltage at the IUTs (ASs) supply input has dropped to +2.0V. Adaptation of

up event).



time according to figure 9-4, transition number 3 in [01-PL Spec] while no other
stress condition is present. Additionally, the behaviour at the local communication

• Failure: none.




Pass criteria:
VCC/VBAT voltages at the IUTs (ASs) supply inputs have dropped to +2.0/+2.0V.
Adaptation of thresholds for digital signals may be required.

up event).



time according to figure 9-4, transition number 3 in [01-PL Spec] while ground shift is
present. Additionally, the behaviour at the local communication controller interface
and, if available, the local bus guardian interface is verified.

• Failure: none.




Pass criteria:
VCC/VBAT voltages at the IUTs (ASs) supply inputs have dropped to +2.0/+2.0V.
Adaptation of thresholds for digital signals may be required.

up event).

7.3.11 Mode.Active Star.Low Power.Sleep.Wake-up


stress condition is present. Additionally, the behaviour at the local communication

• Failure: none.

• Sleep preamble.



Pass criteria:
• uRxD of the AS shall be in logical HIGH state while test execution.
• in case of an available RxEN signal uRxEN of the AS shall be in logical
HIGH state while test execution.
• in case of an available INH1 signal uINH1 of the AS shall be in logical
LOW state before the wake-up pattern is transmitted by node 2. Then,

uINH1 of the AS shall change to logical HIGH state within 100ms, i.e. the
AS enters AS_Normal after the detection of the remote wake-up event.



shift is present. Additionally, the behaviour at the local communication controller
interface and, if available, the local bus guardian interface is verified.

• Failure: none.

• Sleep preamble.



Pass criteria:



LowBat, Failure = 0

battery voltage is present. Additionally, the behaviour at the local communication

• Failure: none.

• Sleep preamble.


Pass criteria:

7.3.12 Mode.Active Star.Branch.Idle


This test checks the activation of the transmitter of the active star via the TxEN
signal of the local communication controller interface according to section 9.2.1 in
[01-PL Spec] while no stress condition is present and the branches of the active star
are in Branch_Idle state and signal idle to the central logic of the active star
respectively.

• Failure: none.


• Stimulate the IUT (AS) at TP_AS_TxD and TP_AS_TxEN by one TSS


Pass criteria:
• uRxD of all nodes shall be in logical HIGH state before the IUT is
stimulated to transmit.
• uRxD of all nodes shall contain the 50/50 pattern transmitted by the IUT.
• in case of an available INH1 signal uINH1 of the active star shall be in
logical HIGH state during test execution.



[01-PL Spec] while ground shift is present and the branches of the active star are in
Branch_Idle state and signal idle to the central logic of the active star respectively.

• Failure: none.



Pass criteria:



LowBat, Failure = 0

[01-PL Spec] while low battery voltage is present and the branches of the active star
are in Branch_Idle state and signal idle to the central logic of the active star
respectively.

• Failure: none.



Pass criteria:

execution.



This test checks the FlexRay parameter dStarSetUpDelay while no stress condition
active star (to a branch of the AS) slightly after dStarSetUpDelay is ignored by the
active star while the CC interface receives already a data stream.

• Failure: none.
• Communication: Node 1 and AS as transmitter.


• Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 1
(branch 1).
• Stimulate node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS pattern,
followed by one 10/90 pattern. Start stimulation of node 1 500ns after the
start of the transmission at the CC interface of the AS.

Pass criteria:
• uRxD of all observed nodes shall contain the 50/50 pattern applied to the
communication controller interface of the Active Star, only.
• the pattern that was stimulated at node 1 shall not be retransmitted by the
active star because the incoming data stream at branch 1 shall be ignored
after dStarSetUpDelay.



This test checks the FlexRay parameter dStarSetUpDelay while ground shift at the
AS is present. This test case verifies that a second incoming data stream reaching
the active star (to a branch of the AS) slightly after dStarSetUpDelay is ignored by
the active star while the CC interface receives already a data stream.

• Failure: none.


(branch 1).

Pass criteria:


LowBat, Failure = 0

This test checks the FlexRay parameter dStarSetUpDelay while low battery voltage
active star (to a branch of the AS) slightly after dStarSetUpDelay is ignored by the
active star while the CC interface receives already a data stream.

• Failure: none.


(branch 1).


Pass criteria:
execution.

7.3.13 Mode.Active Star.Branch.Active


[01-PL Spec] while no stress condition is present. Activation shall not be possible
when the branches of the active star are in Branch_Active already, i.e. it shall not be
possible to disturb ongoing communication via the local communication controller

interface.
• Failure: none.
• Communication: Node 1 and Active Star as transmitter.




one TSS pattern, followed by five 50/50 patterns.
pattern, followed by one 10Bit HIGH pattern. Start stimulation delayed by
1µs to node 1, i.e. the stimulus at the local communication controller
interface of the active star occurs while the branches are in Branch_Active
already.

Pass criteria:

• uRxD of all observed nodes shall contain all 50/50 patterns transmitted by
node 1, i.e. the stimulus at the local communication controller interface of
the active star does not disturb ongoing communication.
• uRxD of the active star shall contain all 50/50 patterns transmitted by node
1, i.e. the stimulus at the local communication controller interface of the
active star does not disturb ongoing communication.
logical LOW state while uRxD of the active star signals the patterns
received from node 1 and in logical HIGH state otherwise.



[01-PL Spec] while ground shift is present. Activation shall not be possible when the
branches of the active star are in Branch_Active already, i.e. it shall not be possible
to disturb ongoing communication via the local communication controller interface.

• Failure: none.




already.

Pass criteria:



LowBat, Failure = 0

[01-PL Spec] while low battery voltage is present. Activation shall not be possible
when the branches of the active star are in Branch_Active already, i.e. it shall not be
possible to disturb ongoing communication via the local communication controller
interface.

• Failure: none.




already.

Pass criteria:

execution.

7.3.14 Mode.Active Star.Branch.FailSilent


[01-PL Spec] while no stress condition is present. Activation shall solely be possible
when the branches of the active star are in Branch_Idle state or Branch_FailSilent
state and signal idle to the central logic of the active star respectively.



• Observe and acquire uRxD at TP_Nx_RxD of all nodes except nodes 11,
12, 13 and 14 (branch 4).
pattern, followed by one 50/50 pattern. Start stimulation 15000µs after the
start of the babbling idiot sequence, i.e. after branch 4 shall have been
excluded from communication and shall have entered Branch_FailSilent.


Pass criteria:
• uRxD of all observed nodes in branches 1 to 3 shall contain the 50/50
pattern transmitted by the IUT (AS), i.e. activation of the transmitter of the
active star via the TxEN signal of the local communication controller
interface shall be possible while branch 4 is in Branch_FailSilent mode.



[01-PL Spec] while ground shift is present. Activation shall solely be possible when
the branches of the active star are in Branch_Idle state or Branch_FailSilent state
and signal idle to the central logic of the active star respectively.



12, 13 and 14 (branch 4).


Pass criteria:


LowBat, Failure = 0

[01-PL Spec] while low battery voltage is present. Activation shall solely be possible
when the branches of the active star are in Branch_Idle state or Branch_FailSilent
state and signal idle to the central logic of the active star respectively.



12, 13 and 14 (branch 4).


Pass criteria:
execution.

7.3.15 Failure.Loss

Standard, Failure TxEN unconnected

This test checks the behaviour of the IUT in case of an unconnected TxEN signal

• Failure: TxEN unconnected.

• Switch TxEN signal of the active star to unconnected according to chapter
3.5, failure FL5.



Pass criteria:
• uRxD of the active star shall contain all 50/50 patterns transmitted by
nodes 1, 2, 12 and 23, i.e. the active star shall signal all patterns received
on all branches at the local communication controller interface.

• uRxD of all nodes (except the active star) shall not contain the 50/50
pattern applied to the communication controller interface of the active star,
i.e. the active star shall read the unconnected TxEN input as logical HIGH
and shall not be able to transmit anything.
logical LOW state while uRxD of the active star signals the received
patterns and shall be logical HIGH state otherwise.


Standard, Failure TxD unconnected

This test checks the behaviour of the IUT in case of an unconnected TxD signal

• Failure: TxD unconnected.

• Switch TxD signal of the active star to unconnected according to chapter
3.5, failure FL6.



Pass criteria:
• uRxD of all nodes (except the active star) shall contain a logical LOW
sequence with the length of the 50/50 pattern instead of the 50/50 pattern
applied to the communication controller interface of the active star, i.e. the
active star shall read the unconnected TxD input as logical LOW and shall

transmit sequences of logical LOW if enabled to transmit.


Standard, Failure BGE unconnected

This test checks the behaviour of the IUT in case of an unconnected BGE signal
This test is skipped if the Functional Class “Active Star - Bus Guardian Interface” is
not implemented.
•

• Failure: BGE unconnected.

• Switch BGE signal of the active star to unconnected according to chapter
3.5, failure FL10.

• Observe and acquire uRxEN at TP_AS_RxEN of the active star.


Pass criteria:

• uRxD of all nodes (except the active star) shall not contain the 50/50
pattern applied to the communication controller interface of the active star,
i.e. the active star shall read the unconnected BGE input as logical LOW
and shall not be able to transmit anything.
• uRxEN of the active star shall be in logical LOW state while uRxD of the
active star signals the received patterns and shall be logical HIGH state
otherwise.





• Switch GND connection of all IUTs in the AS to unconnected according to

• Stimulate the AS at TP_AS_TxD and TP_AS_TxEN by one wake-up

Pass criteria:
bus.



Standard, Failure GND of AS unconnected

connection of the whole AS according to table 8-25 in [01-PL Spec].

• Failure: GND of AS unconnected.

• Switch GND connection of whole AS to unconnected according to Figure
3-9 and Table 3-4, failure FL16.


Pass criteria:
bus.


7.3.16 Failure.Short Circuits

Standard, Failure TxEN GND

This test checks the behaviour of the IUT in case of TxEN is hot-wired to GND

• Failure: short-circuit TxEN to GND.


• Short-circuit TxEN and GND of the IUT (AS) according to chapter 3.5,
failure FL4.
• Beginning with the falling edge of uTxEN of the active star, stimulate IUT
(AS) at TP_AS_TxD by a logical LOW state sequence of at least 15000µs.


Pass criteria:
Hint: For BranchActive timeout measurement, a trigger event on the falling edge of
uTxEN is required.
• uRxD of all nodes shall be in logical HIGH state before the falling edge of
uTxEN of the active star. After the falling edge of uTxEN of the active star,
uRxD of all nodes shall change to logical LOW state and shall remain in
logical LOW state for at least 1500µs and not more than 15000µs. After
this logical LOW state phase, uRxD of all nodes shall return to and remain
in logical HIGH state.

• in case of an available RxEN signal uRxEN of the active star shall be in:
o logical HIGH state during test execution if no loopback functionality
is implemented, or
o another logical state that has to be defined if the bus guardian
interface is finalized, e.g. logical LOW state until the local
communication controller interface is excluded from communication
or logical LOW state permanently.


AS_Normal, tr1 ramp

according to chapter 3.4 in AS_Normal mode. Additionally, the behaviour at the local
is verified.

• Failure: none.




by one TSS pattern, followed by one 50/50 pattern. Repeat this sequence.
At least one more sequence shall be transmitted after the end of the


Pass criteria:
o uRxD of all observed nodes shall contain all 50/50 patterns applied
to the local communication controller interface of the active star
(according to uTxD and uTxEN of the active star), i.e. all data shall
be transmitted by the active star.
o uRxD of the active star shall contain all 50/50 patterns transmitted
by nodes 1, 2, 12 and 23 (according to uTxD and uTxEN of the
corresponding node), i.e. the active star shall signal all patterns
received on all branches to the local communication controller
interface.
o in case of an available RxEN signal uRxEN of the active star shall
be in logical LOW state while uRxD of the active star signals the
received patterns and shall be logical HIGH state otherwise.


AS_Normal, tr6 ramp

according to chapter 3.4 in AS_Normal mode. Additionally, the behaviour at the local
is verified.

• Failure: none.




by one TSS pattern, followed by one 50/50 pattern. Repeat this sequence.
At least one more sequence shall be transmitted after the end of the

Pass criteria:
o uRxD of all observed nodes shall contain all 50/50 patterns applied
to the local communication controller interface of the active star
(according to uTxD and uTxEN of the active star), i.e. all data shall
be transmitted by the active star.
o uRxD of the active star shall contain all 50/50 patterns transmitted
by nodes 1, 2, 12 and 23 (according to uTxD and uTxEN of the
corresponding node), i.e. the active star shall signal all patterns
received on all branches to the local communication controller
interface.
o in case of an available RxEN signal uRxEN of the active star shall
be in logical LOW state while uRxD of the active star signals the
received patterns and shall be logical HIGH state otherwise.

7.3.18 Communication.Truncation


This test checks the overall channel truncation if no stress condition is present

• Failure: none.




Pass criteria:
• the width of the received TSS pattern transmitted by the active star (logical
LOW phase from the falling edge of the received TSS pattern to the rising
edge of the first bit of the following 10/90 pattern) in uRxD of all nodes shall

be at least 100ns, i.e. the channel truncation shall be within the allowed
range.
• the width of all received TSS patterns transmitted by nodes 1, 2, 12 and 23
(logical LOW phase from the falling edge of the received TSS pattern to
the rising edge of the first bit of the following 10/90 pattern) in uRxD of the
active star shall be at least 100ns, i.e. the channel truncation shall be
within the allowed range.



This test checks the overall channel truncation if ground shift is present according to
the sum of all allowed truncation effects specified in [01-PL Spec]. This test shall
verify, that only the transmission start sequence is affected by truncation effects and
that a protocol controller would decode the following data properly.

• Failure: none.




Pass criteria:
range.



LowBat, Failure = 0

This test checks the overall channel truncation if low battery voltage is present

• Failure: none.




Pass criteria:
range.

execution.


transmitter (node), Power Supply = Standard, Failure = 0

shift is present at the transmitting node.

• Failure: None.


• Observe and acquire uGS_dyn at TP_AS_GND of node 23 according to
• Observe and acquire uRxD at TP_AS_RxD of the AS.
pattern as described in chapter 5.1.3.1, followed by one TSS pattern,

followed by ten 50/50 patterns. Trigger the dynamic ground shift curve
synchronously with the first rising edge after the TSS pattern.

Pass criteria:
• uRxD of the AS shall contain all 50/50 patterns transmitted by node 23, i.e.
the dynamic ground shift at node 23 shall not disturb the communication.
• In case of an available INH1 signal uINH1 of the AS shall be in logical
HIGH state (Not_Sleep) during test execution

• In case of an available RxEN signal uRxEN of the AS shall be in logical
LOW state while uRxD of the active star signals the received patterns of
node 23 and in logical HIGH state otherwise.


transmitter (AS), Power Supply = Standard, Failure = 0

shift is present at the AS.

• Failure: None.


• Observe and acquire uTxD at TP_AS_TxD of the AS according to the

Pass criteria:


7.3.19.3 Standard environment, Ground Shift = dynamic at the receiver

(AS), Power Supply = Standard, Failure = 0

shift is present at the AS.

• Failure: None.


• Observe and acquire uRxD at TP_AS_RxD of the AS according to the


Pass criteria:

7.3.19.4 Standard environment, Ground Shift = dynamic at the receiver

(node), Power Supply = Standard, Failure = 0

shift is present at the receiving node.

• Failure: None.


• Observe and acquire uTxD at TP_AS_TxD of the AS according to the

Pass criteria:

• uRxD of node 23 shall contain all 50/50 patterns transmitted by the AS, i.e.

7.3.20 Communication.Shortened Bit Times

Hint: value of about 36ns is a snapshot of the current status. This value may change
in the future if new results are available

Standard, Failure = 0, Low Pattern


• Failure: none.




followed by three 10Bit Low patterns, followed by one 10/90 pattern,
followed by two 10Bit Low patterns. The length of each single bit shall be
36ns measured at TPAS4_B3 of the AS. In case the bit length is to long
the stimulated bits at the transmitter shall be shortened, otherwise the bits
shall be elongated.

Pass criteria:
•

the length of the received high bit in the 10/90 pattern as specified in the
observation window in uRxD of the AS shall be equal to the length of the
high bit in uBus of the corresponding TPAS4_B3 of the AS ±5ns, i.e. the
12.3 in [01-PL Spec].


Standard, Failure = 0, High Pattern

timing constraints chapter 12.3 in [01-PL Spec]. This test shall verify, that a protocol
controller would decode the information received properly.

• Failure: none.


followed by three 10Bit High patterns, followed by one 90/10 pattern,
followed by two 10Bit High patterns. The length of each single bit shall be
36ns measured at TPAS4_B3 of the AS. In case the bit length is to long
the stimulated bits at the transmitter shall be shortened, otherwise the bits
shall be elongated.


Pass criteria:
• the length of the received low bit in the 90/10 pattern as specified in the
observation window in uRxD of the AS shall be equal to the length of the
low bit in uBus of the corresponding TPAS4_B3 of the AS ±5ns, i.e. the
12.3 in [01-PL Spec].

7.4 Test Procedures
7.4.1 Signal Shape, Timing, Delay

NetServices.ISwitch.SetTermination() ***
*** Test cases with alternative power supply configuration, only.

*** Test cases with termination change during test execution, only.
Figure 7-11: Test Procedure for Signal Shape, Timing and Delay Test Cases

7.4.2 Failure
NetServices.ISwitch.SetInterruptionOnBoard() *
NetServices.ISwitch.SetShortCircuitOnBoard() *

*** Test cases with on board interruptions or short circuits, only.

Scope.IConfiguration.Configure() *
Scope.IConfiguration.Acquisition() *
Scope.IConfiguration.Channel() *
Scope.IConfiguration.Trigger() *

LogicAnalyzer.ILogicAnalyzer.Configure() **
Scope.IAcquireBusData.Initiate() *
NetServices.IControl.SetOperatingMode() ***
Scope.AcquireBusData.GetWaveform() *
Scope.AcquireBusData.ObtainParameter() *
*** Test cases with oscilloscope acquisition, only.

*** In some test cases required for observation of pattern generator, only.
*** Test cases with op-mode change during test execution, only.
Figure 7-13: Test Procedure for Dynamic Low Battery Test Cases

7.4.4 Mode

PowerSupply_ALT_VCC.IDCPowerSupplyConfig.Output() ****
**** Test cases with alternative power supply configuration, only.

**** Test cases with ground shift, only.
**** In some test cases required for setup state, only.
**** Test cases with alternative power supply output change during test execution, only.

7.4.5 Truncation

Figure 7-15: Test Procedure for Truncation Test Cases

8 Test Cases for Bus Drivers within a

heterogeneous Topology
8.1 Configuration
8.1.1 Topology
The position of the IUT in the topology is shown with a different color:
22
• Reference Device

24
• IUT

Version 1.0
Battery
VBAT 3m
3m
0.1m 0.1m GNDNode24
8.1.2 Test Planes

VCC VCC
3m 3m
VBat 2m
Battery
VBAT VBAT
3m 3m
0.1m
1m
0.1m GNDNode24
See chapter corresponds to chapter 5.1.2.

11 passive bus
cable shield 3 2
length of 11m 2 4
1
PS AS 1.5m 0.15m 10m
December-2005
0.
m 0.2 VCC 4m 2m
0.2
5 5m
0.2m
0.2m
0.2m
GND 0.5m
1m
0. 2
5m
3.5m
VGS 2m
24 23 22 21 2 14 13 12 11
VIO 4m VGS 2m
Figure 8-1: Positions of BD IUT in heterogeneous Topology

Page 795 of 816


8.1.3 Test Patterns

8.1.4 Power Modes of the Bus Driver


8.1.6 Stress

8.1.7 Failures

8.1.9 Definition of Communication and Control


8.1.11 Standby Preamble


8.1.13 ReceiveOnly Preamble


8.1.15 Receiver Masks


8.1.16 Services


The IUT must successfully pass the test with the same static test cases as specified
in chapter 5.2.
8.3 Test Cases

The executed test cases within the heterogeneous topology are the same test cases
as specified in the homogeneous topology (chapter 5.3). The numeration of the test
cases differs: instead of 5 it is 8.
8.4 Test Procedures

This chapter corresponds to chapter 5.4.

9 Test Cases for Active Stars within a

9.1 Configuration
9.1.1 Topology
The position of the IUT in the topology is shown with a different color:
24
• Reference Device

AS
• IUT

Version 1.0
Battery
VBAT 3m
3m
0.1m 0.1m GNDNode24
9.1.2 Test Planes

VCC VCC
3m 3m
VBat 2m
Battery
VBAT VBAT
3m 3m
0.1m
1m
0.1m GNDNode24
passive bus

11
cable shield 3 2
length of 11m 2 4
1
PS AS 1.5m 0.15m 10m
December-2005
0.
m 0.2 VCC 4m 2m
0.2
5 5m
0.2m
0.2m
0.2m
GND 0.5m
1m
0. 2
5m
3.5m
VGS 2m
24 23 22 21 2 14 13 12 11
VIO 4m VGS 2m
Figure 9-1: Positions of AS IUT in heterogeneous Topology

Page 800 of 816


9.1.3 Test Patterns



9.1.6 Stress

9.1.7 Failures





9.1.13 Services


The IUT must successfully pass all tests as specified in chapter 6.2.
9.3 Test Cases

9.4 Test Procedures


10 Test Cases for AS with CC Interface within a

10.1 Configuration
10.1.1 Topology
10.1.2 Test Planes


10.1.3 Test Patterns

10.1.5 Stress



The IUT must successfully pass the test with the same static test cases as specified
in chapter 7.2.
10.3 Test Cases

10.4 Test Procedures


11 Appendix
11.1 FlexRay Parameters
FlexRay Parameter Description Min Max Unit
gdBit Nominal duration of one bit time 10042 ns
Number of repetitions of Number of repetitions 2 63 -

pWakeupPattern
gdTSSTransmitter Overall truncation with one AS 600 1100 43 ns

gdWakeupSymbol Length of the low part of the wake-up 6 µs
TxLow symbol
gdWakeupSymbol Length of the idle part of the wake-up 18 µs

TxIdle symbol
dPropagationDelayM,N Propagation delay from node M to N 2500 ns
dTruncationM,N Truncation on path from node M to N 1400 ns
RDCLoad DC bus load 40 55 Ω
iBPLeak, iBMLeak Absolute leakage current, when 25 µA

unpowered
uBusActiveHigh Upper receiver threshold for 150 425 mV

detecting activity
uBusActiveLow Lower receiver threshold for -425 -150 mV

detecting activity
uData_1 Receiver threshold for detecting 150 300 mV

Data_1
uData_0 Receiver threshold for detecting -300 -150 mV

Data_0
∆uData Mismatch of receiver thresholds 10 %
dIdleDetection Idle detection time 50 250 ns
dActivityDetection Activity detection time 100 300 ns
42
Currently there is only one data rate specified: 10Mbit/s.
43
In the CT the maximum truncation is limited because there is only one AS in the topology.

dBDRxai Idle reaction time 50 400 ns
dBDRxia Activity reaction time 100 450 ns
uRx uBus @ TP4 425 435 mV
dRxia Transition time Idle Data_0 18 22 ns
dRxai Transition time Data_0 Idle 18 22 ns
dActive Minimum time Data_0 590 610 ns

dIdle Minimum time Idle 590 610 ns
dBDRx10 Receiver delay, negative edge 100 ns
dBDRx01 Receiver delay, positive edge 100 ns
dRxAsym Receiver delay mismatch 5 ns
uRxData uBus @ TP4 400 410 mV
uRx10 Transition time Data_1 Data_0 21.5 22.5 ns
uRx01 Transition time Data_0 Data_1 21.5 22.5 ns
dRx0 Minimum time Data_0 80 120 ns
dRx1 Minimum time Data_1 80 120 ns
uBDTxactive Absolute differential voltage, while 600 2000 mV

sending
uBDTxidle Absolute differential voltage, while 0 30 mV

idle
iBPGNDShortMax Maximum output current when 100 mA

shorted to GND
iBMGNDShortMax Maximum output current when 100 mA

shorted to GND
iBPBAT27ShortMax Absolute maximum output current 100 mA

when shorted to 27V
iBMBAT27ShortMax Absolute maximum output current 100 mA

when shorted to 27V

when shorted to 48V


when shorted to 48V

when shorted to 60V

when shorted to 60V
iBMBPShortMax Absolute maximum output current 100 mA

when BM shorted to BP
iBPBMShortMax Absolute maximum output current 100 mA

when BP shorted to BM
dBDTx10 Transmitter delay, negative edge 100 ns
dBDTx01 Transmitter delay, positive edge 100 ns
dTxAsym Transmitter delay mismatch 4 ns
dBusTx10 Fall time differential bus voltage 5 25 ns
dBusTx01 Rise time differential bus voltage 5 25 ns
dBDTxia Propagation delay idle to active 100 ns
dBDTxai Propagation delay active to idle 100 ns
dBusTxia Signal slope idle to active (BD) 30 ns
dBusTxai Signal slope active to idle (BD) 30 ns
dTxEN0 Time span of bus activity 550 650 ns
dWU01, dWU02 Duration of Data_0 phase in WU >4 µs
dWUIdle1, dWUIdle2 Duration of Idle phase in WU >4 µs
dWU Duration of valid wake-up pattern >16 <48 µs
dWU0Detect Time for detection of a Data_0 phase 1 4 µs

in WU symbol
dWUIdleDetect Time for detection of a Idle phase in 1 4 µs

WU symbol
dWUTimeout Acceptance timeout for WU 48 140 µs

recognition
dWakePulse Duration of a valid wake pulse 1 500 µs

dUV Undervoltage detection filter time 1000 ms
dStarDelay Propagation delay trough an active 250 ns

star
dStarDelay0 Propagation delay trough an active 250 ns

star
dStarAsym Asymmetric propagation delay 8 ns
dStarTruncation Truncation 450 ns
dStarGoToSleep Go-to-Sleep timeout 640 64000 ms

dStarWakeUpReaction Active star wake-up reaction time 100 ms
dBranchActive Noise detection time 1500 15000 µs
dBranchFailSilentIdle Timeout for recovery after failure 10 µs
dStarSetUpDelay Set up delay 500 ns
uVDIG-IN-HIGH Threshold for detecting a digital input 0.7xuVDIG -

as on logical high
uVDIG-IN-LOW Threshold for detecting a digital input 0.3xuVDIG -

as on logical low
uVDIG-OUT-HIGH Threshold for detecting a digital 0.8xuVDIG 1.0xuVDIG -

output, when in logical high state
uVDIG-OUT-LOW Threshold for detecting a digital 0.2xuVDIG -

output, when in logical low state
RCM1, RCM2 Common mode input resistance 10 40 kΩ
uCM Common mode voltage range -10 +15 V
SPI interface speed Characteristics of the optional SPI 0.01 1 Mbit/s

bus driver to host interface
uBias – BD_Normal Voltage @ BP & BM during bus state 1800 3200

Idle
uBias – Low Power Voltage @ BP & BM during bus state -200 +200
Idle_LP

VBAT for WU detector Battery voltage required for wake-up 7 V

detector operation
VBAT monitoring Transition to low power when voltage 2 5.5 V

falls below product specific threshold
VCC monitoring Transition to low power when voltage 2 Product V

falls below product specific threshold specific
iBPLeak Leakage current when all supplies 25 µA

are switched off

iBMLeak Leakage current when all supplies 25 µA
are switched off
dStarTxia Propagation delay idle active 450 ns
dStarTxai Propagation delay active idle 400 ns
Table 11-1: FlexRay Parameters
11.2 References to the EPL Specification

Used version: FlexRay Communications System Electrical Physical Layer
Specification V2.1 Rev A.
Reference description Table Figure Chapter Page
Cable termination 4-1 4.3 19
DC bus load 4-5 4.6 21
Eye diagram at TP4 7-4 7.4 33
Bus Driver - Host interface 8.6 40
Receiver timing characteristics 8-13 8-6 8.9.3 46
Transmitter characteristics 8-17 8-8 8.9.5 50
Operating mode transitions (of BD) 8-1 8-2 8.3 37
Bus Driver - power supply interface 8-8 8.7 42
Remote wake-up event 8.11.1 54
Local wake-up event 8.11.2 55

Reference description Table Figure Chapter Page
Voltage monitoring 8.12 56
Behaviour of unconnected digital input pins 8-24 8.16 58
Bus Driver behaviour under fault conditions 8-25 8.17 59
Active Star - CC interface 9.2.1 65
Active Star - power supply interface 9.2.3 65
dStarTruncation 9-2 9-3 9.3 66
Active Star operation mode transitions 9-4 9-4 9.7 69

Operating states of branches 9-7 9-5 9.9 71
Collisions 9-6 9.10 72
General features for FlexRay parts 11 81
Bahaviour of unconnected digital input pins 11-5 11.6.1 83

(SPI interface)
Resulting timing constraints for the signal 12-3 12.3 86

path
Table 11-2: FlexRay EPL Specification References
11.3 Index
battery splice .................................... 22 ISO 7637 ..........................................45
Bus Cable ......................................... 33 local test method ..............................16
Bus Connector.................................. 35 lower tester .......................................16
cable shield ...................................... 26 Passive Bus......................................32
chassis.............................................. 22 Passive Star .....................................30
CMC ................................................. 29 physical channel ...............................18
Common mode choke ...................... 18 Power Supply Cable .........................34
DIN 40839 ........................................ 45 SOVS................................................53
EMC.................................................. 52 SOVS Communication .....................54
ESD .................................................. 26 SOVS Failure....................................63
ground shift....................................... 38 SOVS Ground Shift ..........................63

SOVS Mode ..................................... 59 test topology .....................................18

SOVS Power Supply ........................ 62 unterminated node............................29
split termination ................................ 27 upper tester ......................................16
Static Tests....................................... 54 VBAT splice ........................................22
supervisor ......................................... 16 VCC splice..........................................22
Temperature Test............................. 52 VECU ..................................................44
test coordination procedure.............. 16 VIO splice...........................................22
test planes ...................................... 438

11.4 List of Tables
Table 2-1: Test Topology Description ........................................................................ 20
Table 2-2: Cable Overview of Test Topology............................................................. 25
Table 2-3: Shield Connection Components ............................................................... 26
Table 2-4: ESD Load Circuit ...................................................................................... 27
Table 2-5: Split Termination Components ................................................................. 28
Table 2-6: Passive Star Implementation .................................................................... 32
Table 2-7: Bus Cable Impedance............................................................................... 34
Table 2-8: Bus Cable Characteristics ........................................................................ 34
Table 2-9: Supply Cable Characteristics.................................................................... 34
Table 2-10: Connectors Characteristics..................................................................... 35
Table 2-11: VBAT Power Supply Characteristics......................................................... 36
Table 2-12: VCC Power Supply Characteristics.......................................................... 37
Table 2-13: VIO Power Supply Characteristics........................................................... 37
Table 2-14: Ground Shift Generator Characteristics ................................................. 38
Table 2-15: Low Battery Generator Characteristics................................................... 39
Table 2-16: Signal Generator Characteristics............................................................ 39
Table 2-17: Analog Measurement Device Characteristics......................................... 40
Table 2-18: Digital Measurement Device Characteristics.......................................... 40
Table 2-19: Data Acquisition Unit............................................................................... 41
Table 2-20: Broadband Amplifier ............................................................................... 41
Table 2-21: Arbitrary Function Generator .................................................................. 42

Table 3-1: Ground Shift .............................................................................................. 43

Table 3-2: Stress Condition Static Low Battery Voltage inside operational Range... 45
Table 3-3: Stress signal 4’.......................................................................................... 46
Table 3-4: Faulty Lines Test Parameter..................................................................... 48
Table 5-1: Test Planes @ the Nodes (analog Signals).............................................. 67
Table 5-2: Test Planes @ the Nodes (digital Signals) ............................................... 69
Table 5-3: Power Modes of the Bus Driver ................................................................ 79
Table 5-4: Static Test Cases....................................................................................101
Table 6-1: Test Planes @ the Active Star for analog Signals..................................439

Table 6-2: Test Planes @ the AS (digital Signals)...................................................440
Table 7-1: Test Planes @ the analog Interface .......................................................620
Table 7-2: Test Planes @ Digital Interfaces of the Active Star for the Logic Analyzer
..........................................................................................................................620
Table 11-1: FlexRay Parameters .............................................................................808
Table 11-2: FlexRay EPL Specification References................................................809
11.5 List of Figures

Figure 2-1: Local Test Method ................................................................................... 16
Figure 2-2: Upper Tester............................................................................................ 17
Figure 2-3: Lower Tester............................................................................................ 17
Figure 2-4: Conformance Test Topology ................................................................... 21
Figure 2-5: Cable Shield Connection ......................................................................... 26
Figure 2-6: ESD Load Circuit ..................................................................................... 27
Figure 2-7: Terminated Node ..................................................................................... 28
Figure 2-8: Unterminated Node.................................................................................. 29
Figure 2-9: Common Mode Choke Implementation................................................... 29
Figure 2-10: Passive Star Implementation................................................................. 31
Figure 2-11: Passive Bus Implementation ................................................................. 33
Figure 3-1: Usage of Ground Shift ............................................................................. 43

Figure 3-2: Location of Ground Shift .......................................................................... 44

Figure 3-3: Description of VBAT and VECU ................................................................... 45
Figure 3-4: Stress signal 4’ ........................................................................................ 46
Figure 3-5: Location of the onboard Failures ............................................................. 47
Figure 3-6: Failure/Loss of Supplies .......................................................................... 49
Figure 3-7: Failures of digital Signals TxEN, TxD, BGE and STBN .......................... 49
Figure 3-8: Failures of Bus Wires BP and BM ........................................................... 50
Figure 3-9: Failures of GND Wire............................................................................... 50
Figure 3-10: Location of Termination Changes inside a Node .................................. 50

Figure 3-11: Dynamic Ground Shift Curve - Input ..................................................... 51
Figure 3-12: Dynamic Ground Shift Curve - possible Output .................................... 52
Figure 4-1: Overview of the SOVS Parameters ......................................................... 53
Figure 4-2: SOVS Static Tests ................................................................................... 54
Figure 4-3: SOVS Communication with Sub Items.................................................... 54
Figure 4-4: SOVS Delay with FlexRay Parameters ................................................... 55
Figure 4-5: SOVS Signal Shape with FlexRay Parameters....................................... 56
Figure 4-6: SOVS Threshold with FlexRay Parameters ............................................ 57
Figure 4-7: SOVS Timing with FlexRay Parameters ................................................. 58
Figure 4-8: SOVS Masks ........................................................................................... 58
Figure 4-9: SOVS Truncation with FlexRay Parameters ........................................... 59
Figure 4-10: SOVS Mode with Sub Items .................................................................. 60
Figure 4-11: SOVS Branch with Sub Items................................................................ 61
Figure 4-12: SOVS Low Power with Sub Items ......................................................... 61
Figure 4-13: SOVS Normal with Sub Items ............................................................... 61
Figure 4-14: SOVS Normal with Sub Items ............................................................... 62
Figure 4-15: SOVS Normal with Sub Item ................................................................. 62
Figure 4-16: SOVS ReceiveOnly ............................................................................... 62
Figure 4-17: SOVS Power Supply.............................................................................. 62
Figure 4-18: SOVS Environment................................................................................ 63
Figure 4-19: SOVS Dynamic Low Battery Voltage .................................................... 63
Figure 4-20: SOVS Ground Shift................................................................................ 63

Figure 4-21: SOVS Failure with Sub Items ................................................................ 64

Figure 4-22: SOVS Babbling Idiot .............................................................................. 64
Figure 4-23: SOVS Loss with several Sub Items....................................................... 65
Figure 4-24: SOVS Short Circuit with Sub Items ....................................................... 65
Figure 4-25: SOVS Termination................................................................................. 65
Figure 4-26: SOVS Functional Class ......................................................................... 66
Figure 5-1: Test Planes @ the Nodes (analog Signals) ............................................ 67
Figure 5-2: Test Planes @ the Nodes (digital Signals).............................................. 68
Figure 5-3: Test Planes for the Oscilloscope ............................................................. 70

Figure 5-4: Wake-up Symbol for the Test Pattern ..................................................... 71
Figure 5-5: Test Pattern for the TSS Symbol............................................................. 72
Figure 5-6: Test Pattern for Data Signal 50/50 .......................................................... 72
Figure 5-9: Test Pattern 10Bit Low ............................................................................ 73
Figure 5-10: Test Pattern 10Bit High ......................................................................... 73
Figure 5-11: Test Pattern SymbolTxLow_Idle............................................................ 74
Figure 5-12: Test Pattern for Current Measurement of Bus Wires ............................ 74
Figure 5-13: Test Pattern for non suitable Wake-up short idle Phase....................... 74
Figure 5-14: Test Pattern for non suitable Wake-up short low Phase ....................... 75
Figure 5-15: Test Pattern for non suitable Wake-up prolonged Pattern .................... 75
Figure 5-16: Observation Point for the Analysis of the Timing Characteristics ......... 75
Figure 5-17: Observation Point for the shortened Bits with Low State ...................... 76
Figure 5-18: Observation Point for the shortened Bits with High State ..................... 77
Figure 5-19: Observation Point for Dynamic Ground Shift ........................................ 77
Figure 5-20: Observation Window for Eye Diagram .................................................. 78
Figure 5-21: Communication Matrix A ....................................................................... 81
Figure 5-22: Communication with Node 11 as Transmitter (Time Diagram) ............. 81
Figure 5-23: Communication with Node 11 as Transmitter (Topology) ..................... 82

Figure 5-26: Communication with Node 1 as Transmitter (Time Diagram) ............... 83

Figure 5-27: Communication with Node 1 as Transmitter (Topology) ....................... 84
Figure 5-32: Communication with Node 24 as observed Transmitter (Time Diagram)
............................................................................................................................ 86
Figure 5-33: Communication with Node 24 as observed Transmitter (Topology) ..... 86

Figure 5-34: Communication with Node 24 and 1 as Transmitter (Time Diagram) ... 87
Figure 5-35: Communication with Node 24 and 1 as Transmitter (Topology)........... 87
Figure 5-36: Host Command to IUTs ......................................................................... 88
Figure 5-37: Oscilloscope Services............................................................................ 91
Figure 5-38: Pattern Generator Services ................................................................... 92
Figure 5-39: Logic Analyzer Services ........................................................................ 93
Figure 5-40: Logic Analysis System Services............................................................ 93
Figure 5-41: Power Supply Services.......................................................................... 94
Figure 5-42: Network Services................................................................................... 95
Figure 5-43: Test Procedure for Signal Shape, Timing and Delay Test Cases.......432
Figure 5-44: Test Procedure for Truncation and Masks Test Cases.......................433
Figure 5-45: Test Procedure for Mode Test Cases .................................................434
Figure 5-46: Test Procedure for Failure Test Cases ...............................................435
Figure 5-47: Test Procedure for Undervoltage Test Cases .....................................436
Figure 5-48: Test Procedure for Dynamic Low Battery Cases ................................437
Figure 6-1: Test Planes @ the Active Star for analog Signals ................................438
Figure 6-2: 4: Branches of the Active Star ...............................................................439
Figure 6-3: Test Planes @ the AS ...........................................................................440
Figure 6-4: Test Pattern for a Babbling Idiot Simulation ..........................................441
Figure 6-5: Test Signal for Node 1 (Star Setup Delay) ............................................441
Figure 6-6: Test Signal for Node 2 (Star Setup Delay) ............................................441
Figure 6-7: Observation Point for the Analysis of the Star Delay ............................442

Figure 6-8: Observation point for the Analysis of the Active Star Truncation..........443
Figure 6-9: Observation point for the Analysis of the Active Star SetUp Delay.......444
Figure 6-10: Communication Matrix C .....................................................................447
Figure 6-11: Communication Matrix E .....................................................................447
Figure 6-12: Communication Single Transmitter .....................................................448
Figure 6-13: Communication Node 1 and 2 as Transmitter.....................................448
Figure 6-14: Communication with Node 23 as Transmitter (Time Diagram) ...........449
Figure 6-15: Communication with Node 23 as Transmitter (Topology) ...................449
Figure 6-16: Test Procedure for Delay Test Cases .................................................614

Figure 6-17: Test Procedure for Truncation Test Cases .........................................615
Figure 6-20: Test Procedure for Dynamic Low Battery Test Cases ........................618
Figure 7-1: Test Planes @ the analog Interface ......................................................619
Figure 7-2: Test Planes @ Digital Interfaces of the Active Star for the Logic Analyzer
..........................................................................................................................620
Figure 7-3: Communication Matrix F........................................................................622
Figure 7-4: Communication Active Star as transmitter (Timing)..............................623
Figure 7-5: Communication Active Star as transmitter (Topology)..........................623
Figure 7-6: Communication Single Transmitter .......................................................624
Figure 7-7: Communication Node 1 and AS (Timing)..............................................624
Figure 7-8: Communication Node 1 and AS (Topology)..........................................625
Figure 7-9: Communication with Node 23 as Transmitter (Time Diagram) .............625
Figure 7-10: Communication with Node 23 as Transmitter (Topology) ...................625
Figure 7-11: Test Procedure for Signal Shape, Timing and Delay Test Cases.......789
Figure 7-13: Test Procedure for Dynamic Low Battery Test Cases ........................791
Figure 7-15: Test Procedure for Truncation Test Cases .........................................793
Figure 8-1: Positions of BD IUT in heterogeneous Topology ..................................795
Figure 9-1: Positions of AS IUT in heterogeneous Topology ..................................800


Flexray - Physical Layer Conformance Test Specification V1.0

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FlexRay Physical Layer Conformance Test Specification

FlexRay Physical Layer

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Copyright © 2004 - 2005 FlexRay Consortium. All rights reserved.

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2.5.5 Ground Shift Generator ........................................................................ 38

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4.4 Power Supply............................................................................................... 62

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5.3 Test Cases.................................................................................................102

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6 Test Cases for Active Stars within a homogeneous Topology..........................438

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6.3.13 Mode.Active Star.Branch.Idle.............................................................559

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8.1.3 Test Patterns ......................................................................................796

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9.1.12 Standard Postamble ...........................................................................801

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1.3 Terms and Definitions

1.4 Acronyms and Abbreviations

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ASP ................. Abstract Service Primitive

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1.5 Notational Conventions

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2.2 Test Method

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Figure 2-1: Local Test Method

2.2.1 Upper Tester

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Upper Tester Upper Tester

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Figure 2-2: Upper Tester

2.2.2 Lower Tester

Figure 2-3: Lower Tester

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• Generate and control bus failures

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2.3 Test Environment

2.4 Test Topology

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Local ground of node 24

3m Splice for power supply wires

1.5m Bus wire

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