A clocking block specifies timing and synchronization for group of signals.

clocking cb @(posedge clk);

default input #10ns output #2ns;
output read,enable,addr;
input negedge data;
endclocking

The fourth line adds the signal data to the clocking block as input. Fourth line also
contains negedge which overrides the skew ,so that data is sampled on the negedge of
the clk.

Skew can be specified in 3 ways.

#d : The skew is d time units. The time unit depends on the timescale of the block.
#dns : The skew is d nano seconds.
#1step : Sampling is done in the preponed region of current time stamp.

If skew is not specified, default input skew is 1step and output skew is 0.

Cycle delay: ##

## 8; // wait 8 clock cycles

## (a + 1); // wait a+1 clock cycles

Using clocking blocks,cycle delays syntax gets reduced.

Insted of writing repeat(3) @(posedge clock); sync_block.a <= 1;

Just use ##3 sync_block.a <= 1;

To schedule the assignment after 3 clocks,

Just use, sync_block.a <= ##3 1;

To simply wait for 3 clock cycles, ##3; can be used.

But there may be more than one clocking block is defined in a project.
##3 waits for 3 clocks cycles,of the block which is defined as default.

default clocking sync_block @(posedge clock);