EL2095 Digital System

Flip-Flops, Registers, Counters, and A Simple

Processor (Ch 7)
 Why Need Memory?
• Example application:
– A sensor triggers an alarm
– Alarm stays on even if sensor goes inactive
– Need a memory element to remember

Set
Sensor
Memory On  Off
Alarm
element
Reset

Timing example
 A Simple Memory
Element
A B
Stable when
A=1,B=0 or
A=0,B=1

How to get it to
switch states?
 A Controlled Memory
Load
Element
A B
Data Output
TG1

TG2

• When Load=1
– Point A gets value of Data
– feedback is disabled
 Bistable element
• The simplest sequential circuit
• Two states
– One state variable, say, Q
HIGH LOW

LOW HIGH
 Bistable element
• The simplest sequential circuit
• Two states
– One state variable, say, Q
LOW HIGH

HIGH LOW
 Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V
 Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V
2.5 V 2.5 V

2.5 V 2.5 V
 Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V
2.5
4.8
2.51VV 2.5 V
2.0
0.0

2.5 V
2.0
0.0 4.8
5.0
2.5 V
 Metastability
• Metastability is inherent in any bistable
circuit
Another look at
metastability
 Set-Reset Latch (SR latch)
Q Q
N1 N1
S N2 Q S N2 Q
R
(a) (b)

S
N1 Q
S Q

R Q
N2 Q
R
(c) (d)
 S-R (set-reset) Latch
R Truth table
Qa
S R Qa Qb

0 0 0/1 1/0 (no change)

0 1 0 1
1 0 1 0
Qb characteristic
S 1 1 0 0
table

t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

1
R
0

1
S
0

1
Qa
0

1
Qb
0
 Example
10
• Complete timing diagram R
01 0
Qa
• Assume 1 unit propagation delay

Qb
S 01 0
10

S 1 0

R 1 0

Qa 0 1 0

Qb 0 1 0
 NAND SR Latch
S S=0 S=1
S
N1 Q Q

R N2 Q R=0 R=1 Q
R

(a) (b)

S
Q

Q
R

(c)

S Q S Q

R Q R Q

(d) (e)
Set-Reset Latch Timing Diagram
S

R
Q

Set Reset Set Illegal

inputs
Unknown values
(a)

R
Q

Set Reset Set Illegal

inputs
Unknown values
(b)
 Gated S-R Latch
• Allow latch to change state only when a control signal
is asserted
Gated S-R Latch
Gated S-R Latch with NAND gates
• Uses only NAND gates (fewer transistors than AND
gates)
• Note that S,R are switched Characteristic table

S
Q

Clk

Q
R
Example – Switch Debouncing
• Most mechanical switches will bounce for a short time
(10-20 ms)
• If switch is being used to say, count events, this
leads to erroneous count

VDD

Data

Timing diagram
 Example – Switch
Debouncing
• When switch at bottom,
VDD
R=0 and Data=0
• When switch thrown to
R
top, S=0 so Data=1
Single-pole
double-throw S • When switch bounces to
switch Data middle, S=R=1 so Data
retains last value

R S-R latch

VDD
Gated D-Latch
Instead of a
separate set (S)
and reset (R), it is
easier to think of a
latch as storing
some data (D)

Eliminates “weird case”

when both S and R
asserted
Gated D-Latch
 D Latch Timing Constraints

• Setup Time: D input must be stable before clock

change
• Hold Time: D input must remain stable after clock
change
• Minimum Pulse Width: Clock width that guarantee a
correct state change
 Flip-flops
• Flip-flops vs latches
– Latches change state whenever inputs change (as
long as control/enable is asserted)
– Flip-flops only change state at the rising or falling
edge of a clock signal

• We’ll look at
– D flip-flops
– T flip-flops
– JK flip-flops
 Clock Signals for a Latch

• How do we know when it’s safe to set C=1?

– Most common solution –make C pulse up/down
• C=0: Safe to change X, Y Level-sensitive SR latch
• C=1: Must not change X, Y X
S
S1
• We’ll see how to ensure that later
– Clock signal -- Pulsing signal used to enable C
latches Clk

• Because it ticks like a clock Q

R
– Sequential circuit whose storage components allY R1
use clock signals: synchronous circuit
• Most common type
• Asynchronous circuits – important topic, but left
for advanced course
 Clocks

• Clock period: time interval between

pulses Freq Period
100 GHz 0.01 ns
– Above signal: period = 20 ns 10 GHz 0.1 ns
• Clock cycle: one such time interval 1 GHz
100 MHz
1 ns
10 ns
– Above signal shows 3.5 clock cycles 10 MHz 100 ns

• Clock frequency: 1/period

– Above signal: frequency = 1 / 20 ns =
50 MHz (1 Hz = 1/s)
 D flip-flop
• Can create using two D latches D Q

• (this configuration is called a master-slave Q

f/f)
Master Slave
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q

Characteristic table
• When Clock=1, master follows the input signal (Qm = D),
slave retains last state
• When Clock goes to 0, master is frozen, slave follows
master (Qs = Qm)
• Thus, Qs takes the value of D when the clock fell ↓
 D flip-flop (alternative
design) Positive edge triggered
1 P3

P1
2
5 Q

Clock

P2 6 Q
3

D Q

Clock Q
4 P4
D

(a) Circuit (b) Graphical symbol

 Example

• Complete timing diagram

D D Q Qa

Clock Clk Q Qa
Clock

D Q Qb D

Q Qb Qa

Qb
D Q Qc

Q Qc Qc
D Flip-flops with Clear and
Preset
• It is useful to initially force the f/f to a known state
– Clear=0 forces to 0 Preset

– Preset=0 forces to 1 D Q

Q
Preset
Clear

D
Q

Clock

Clear

Master-slave design
Asynchronous vs synchronous
clear and preset
• Asynchronous clear (or preset) – takes effect
immediately
• Synchronous clear (or preset) – takes effect on edge
of clock

Example design for D f/f

Clear with synchronous clear
D Q Q
D

Clock Q Q

How would you implement

both synchronous clear and
synchronous preset?
 T Flip-flop
• Flips (toggles) its
state on clock edge T Qt + 1
T Q
0 Qt 
• Useful for counter 1 Qt 
Q

circuits

Clock

Q
 T flip-flop (continued)
• We can design a T f/f out of a D f/f
– If T=0, then make D=Q
– If T=1, then make D=Q’
– So D = TQ’ + T’Q
 T flip-flop (continued)
• We can design a T f/f out of a D f/f
– If T=0, then make D=Q
– If T=1, then make D=Q’
– So D = TQ’ + T’Q = T EXOR Q

D Q Q

T
Q Q

Clock
 JK flip-flop
J K Q  t + 1
0 0 Q t J Q
0 1 0
1 0 1 K Q
1 1 Q t 

• Combines behavior of SR and T flip-flops

• Not nearly as common
• Can also design out of a D flip-flop
 JK flip-flop from D f/f
• D = JQ’ + K’Q

J
D Q Q
K Q Q

Clock
 Flight-Attendant Call Button
Using D Flip-Flop
• D flip-flop will store bit Call
Flight Blue
• Inputs are Call, Cancel, and present
button light
attendant
Cancel call-button
value of D flip-flop, Q button system

• Truth table shown below

Preserve value: if Circuit derived from truth table,

Q=0, make D=0; if using Chapter 2 combinational
Q=1, make D=1 logic design process

Cancel -- make Call Call

but ton Blue
D=0 D Q’
light
Cancel
but ton
Cancel
Clk Q
Call -- make D=1 Q

Let’s give priority

to Call -- make
D=1
 Registers
• A collection of D flip-flops

8-bit register
D0 D Q Q0

pre
D[7..0]
D1 D Q Q1 Q[7..0]

Clk
clr

Dn-1 D Q Qn-1
Parallel load,
parallel access

Useful for storing

Clk numbers
Example – Accumulator Circuit
• Keeps adding the input number to a sum that is being
accumulated in the register

In Quartus, can create using LPM (library of parameterized modules) –

lpm_add_sub, lpm_ff
 Timing of accumulator
circuit
• Assume
– tpd for register is 2 ns
– tpd for adder is 12 ns
– tsu for register is 3 ns

Clk

Data[3..0] 0001

Q[3..0] 0000 0001

2 ns
result[3..0] 0001 0010
12 ns 3 ns

Minimum period is 17 ns → max frequency is 1/17ns = 58 MHz

 Shift Register
serial in
Q1 Q2 Q3 Q4
In D Q D Q D Q D Q Out

serial out
Clock Q Q Q Q

Sample sequence
• Useful for dividing or
multiplying by two
In Q1 Q2 Q3 Q4 = Out
t0 1 0 0 0 0
t1 0 1 0 0 0 • Or for converting serial
t2 1 0 1 0 0 data to parallel
• Unidirection or
t3 1 1 0 1 0
t4 1 1 1 0 1
bidirection
 Serial Data Transfer
• Serial mode → Data is transferred one
bit at a time
 Shift Register
parallel out

serial in
Q1 Q2 Q3 Q4
In D Q D Q D Q D Q Out
serial out
Clock Q Q Q Q

Sample sequence

In Q1 Q2 Q3 Q4 = Out • Serial in parallel

out
t0 1 0 0 0 0
t1 0 1 0 0 0
t2 1 0 1 0 0
t3 1 1 0 1 0
t4 1 1 1 0 1
Shift Register with Parallel
Load Parallel output

Q3 Q2 Q1 Q0

D Q D Q D Q D Q

Q Q Q Q

Serial Clock
input Shift/Load Parallel input
Universal Shift Register
Example Using Registers:
Temperature Display
• Temperature history display
– Sensor outputs temperature as 5-bit binary number
– Timer pulses C every hour
– Record temperature on each pulse, display last three
recorded values
Present 1 hour ago 2 hours ago
Display Display Display

x4 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
x3
x2
x1 TemperatureHistoryStorage
x0
timer
C
(In practice, we would actually avoid connecting the timer output
C to a clock input, instead only connecting an oscillator output to a clock input.)
 Example Using Registers:
Temperature Display
• Use three 5-bit registers
a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
I4 Q4 I4 Q4 I4 Q4
x4
I3 Q3 I3 Q3 I3 Q3
x3
I2 Q2 I2 Q2 I2 Q2
x2
I1 Q1 I1 Q1 I1 Q1
x1
I0 Q0 I0 Q0 I0 Q0
x0
Ra Rb Rc
C
TemperatureHistoryStorage

x4...x0 15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27

Ra 0 18 21 24 25 26 27

Rb 0 0 18 21 24 25 26

Rc 0 0 0 18 21 24 25
 Counters
• Counts in binary or other codes
• Counters normally count 0 … (2N-1 -1)
– N is the number of bits
• Modulo-N counter
 Ripple Counter 3-bit “up”
counter

Also called
1 T Q T Q T Q
“ripple”
Clock Q Q Q counter

Q0 Q1 Q2

(a) Circuit asynchronous

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 6 7 0

(b) Timing diagram

 Synchronous Counters
• Want FF’s to
change state
simultaneously with
Clock cycle Q2 Q1 Q0
clock
Q1 changes
• Note that any Qi 0 0 0 0
changes only when 1 0 0 1 Q2 changes
all the preceding 2 0 1 0
Q’s are 1’s 3 0 1 1
• So make 4 1 0 0
T0 = 1 5 1 0 1
T1 = Q0 6 1 1 0
T2 = Q0 Q1 7 1 1 1
T3 = Q0 Q1 Q2 8 0 0 0
:
 Synchronous Counters
• Want FF’s to 1 T Q Q0
change state
simultaneously with
clock
• Note that any Qi Q0 T Q Q1
changes only when
all the preceding
Q’s are 1’s
• So make Q0
Q1
T Q Q2
T0 = 1
T1 = Q0
T2 = Q0 Q1
Q0
T3 = Q0 Q1 Q2 Q1 T Q Q3
: Q2

Clk
Alternative Synchronous Counter
1 T Q T Q T Q T Q
Q0 Q1 Q2 Q3
Clock Q Q Q Q

(a) Circuit

Clock

Q0

Q1

Q2

Q3

Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

(b) Timing diagram

 Up-Down Binary Counter
• Can count
up (0000 →
1111) or
down (1111
→ 0000)
binary
sequence
Some additional capabilities
• It’s helpful to be able to
74x163
– Clear the counter
CLK
– Enable counting CLR
QA
– Load an initial value LD
QB
ENP
• Example: 74163 ENT
QC
QD
– synchronous 4-bit counter
A
RCO
B

– ENP, ENT enables C

D
– LD loads the value DCBA
– RCO = ripple carry out
• asserted when
QD,QC,QB,QA = 1111
4-bit Enable
0
D Q Q0

counter with
1
D0
Q

parallel load
0
D Q Q1
D1 1

0
D Q Q2
D2 1

0
D Q Q3
D3 1

Output
carry
Load
Clock
 Cascading Counters
• Example: 8 bit counter
CLK

74x163 74x163

CLK CLK
1 CLR 1 CLR
QA Q0 QA Q4
1 LD 1 LD
QB Q1 QB Q5
1 ENP ENP
1 QC Q2 QC Q6
ENT ENT
QD Q3 QD Q7
A A
RCO RCO
B B
C C
D D
 Reset Synchronization
• Counters normally count 0..(2N-1 -1)
• What if you want to count up to some other
limit?
• We can test the current count against the
limit … when it matches, force a reset (or load
zero)
Q2 Q1 Q0
• Example: 0 0 0
– Count from 0..5 on a 3-bit counter 0 0 1
– We’ll check for the value (Q2 Q1 Q0) = (101) 0 1 0
0 1 1
Actually, it is enough to Q2
check for Q2=1, Q0=1 1 0 0
Q1
1 0 1
Q0
Modulo-6
Counter
1 Enable
0 D0 Q0
0 D1 Q1
0 D2 Q2
Load
Clock
Clock

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1

(b) Timing diagram

 Example
• Design a counter to count from 3..12
• (this is called “excess 3” code for decimal)
QD QC QB QA
0 0 1 1
0 1 0 0
CLK CLK
0 1 0 1
1 CLR
LD
QA 0 1 1 0
QB 0 1 1 1
1 QC
A 1 0 0 0
QD
1 B 1 0 0 1
0 C
1 0 1 0
0 D
1 0 1 1
1 1 0 0
Binary Coded Decimal (BCD)
Counter
• Counts 0..9 in binary (0000 → 1001)
QD QC QB QA
0 0 0 0
0 0 0 1
CLK CLK
0 0 1 0
CLR
QA 0 0 1 1
1 LD
QB 0 1 0 0
0 A
QC 0 1 0 1
QD
0 B 0 1 1 0
0 C 0 1 1 1
0 D 1 0 0 0
1 0 0 1
Two Digit BCD counter
1 Enable
0 D0 Q0
0 D1 Q1
D2 Q2 BCD 0
0
0 D3 Q3

Load
Clock
Clock

Clear Enable
0 D0 Q0
0 D1 Q1
D2 Q2 BCD 1
0
0 D3 Q3

Load
Clock
 Ring Counter
• Generate the sequence of 1-out-of-N words
• Example: 0001, 0010, 0100, 1000, 0001, …
Q0 Q1 Qn ” 1

Start

D Q D Q D Q

Q Q Q

Clock

• Start sets first f/f to 1, the others to zero

• Clock rotates to the right
Application – Stepper
Motors
 Johnson Counter
• Feed the complement of the bit shifted out, back into
the input
Q0 Q1 Q2 Q3

D Q D Q D Q D Q

Q Q Q Q

Reset
Clock
• Sequence (from reset)?
Johnson
counter

 “Twisted ring”
counter
 VHDL for Sequential
Circuits
• Storage elements are LIBRARY ieee ;
created using USE ieee.std_logic_1164.all ;
“implied memory” … if
code doesn’t specify ENTITY latch IS
PORT ( D, Clk : IN STD_LOGIC ;
a signal value, then it
Q : OUT STD_LOGIC) ;
keeps its old value END latch ;

• Example: Gated D- ARCHITECTURE Behavior OF latch IS

latch BEGIN
PROCESS ( D, Clk )
BEGIN
IF Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
 Code for D flip-flop
• 'EVENT is an LIBRARY ieee ;
attribute of Clock. USE ieee.std_logic_1164.all ;
It refers to any
change in the clock ENTITY flipflop IS
signal. PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;
• Combining
Clock'EVENT ARCHITECTURE Behavior OF flipflop IS
condition with the BEGIN
condition Clock = '1' PROCESS ( Clock )
refers to a positive BEGIN
clock edge IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
 Alternative Code for D
flip-flop
• Sensitivity list is LIBRARY ieee;
omitted because USE ieee.std_logic_1164.all;
the wait until
construct implies
ENTITY flipflop IS
that the
sensitivity list PORT ( D, Clock : IN STD_LOGIC ;
includes ONLY Q : OUT STD_LOGIC ) ;
the clock signal. END flipflop ;

• In synthesis ARCHITECTURE Behavior OF flipflop IS

VHDL, this BEGIN
statement must PROCESS
be the first one BEGIN
in the process. WAIT UNTIL Clock'EVENT AND Clock = '1' ;
Q <= D ;
END PROCESS ;
END Behavior ;
D flip-flop with asynchronous
reset
LIBRARY ieee ;
• If any USE ieee.std_logic_1164.all ;
change in
signal ENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Resetn, Q : OUT STD_LOGIC) ;
process runs END flipflop ;
immediately
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
D flip-flop with synchronous
reset
• Process only
runs on
positive-
going clock
edge
Ex - T flip-flop with asynch
reset
ENTITY TFF IS
PORT ( T, Resetn, Clock : IN STD LOGIC ;
Q : OUT STD LOGIC ) ;
END TFF ;
T Q

ARCHITECTURE Behavior OF TFF IS

SIGNAL Qint : STD LOGIC ;
BEGIN
PROCESS ( Resetn, Clock )
• You can’t read BEGIN
a signal of IF Resetn = ’0’ THEN Qint <= ’0’ ;
type “OUT” ELSIF Clock’EVENT AND Clock = ’1’ THEN
IF T = ’1’ THEN Qint <= NOT Qint ;
• You could,
ELSE Qint <= Qint ;
however,
END IF ;
declare Q as
END IF ;
type “BUFFER”
END PROCESS ;
Q <= Qint ;
END Behavior ;
 Registers in VHDL
• Similar to single flip-flops

is this synchronous
reset or asynchronous
reset?
 Changing Register Sizes
• GENERIC statement – define a variable (“compile
time”)
 Example – Shift Register
• Can use a hierarchical design
Q3 Q2 Q1 Q0

Shift/load

Serial in D Q D Q D Q D Q Serial
out

clk clk clk clk

D3 D2 D1 D0
D flip-flop with mux
component
Sel

D0 D Q Q
D1

clk
Top level structure
Alternative Design - Shift
Register

what if you
reversed the order
of the assignment
statements?
 Counters in VHDL
• Can use arithmetic operators “+”, “-
”
• Need “ieee.std_logic.unsigned.all”
library
Counters – architecture def
 Example: 24-bit up/down
counter
LIBRARY ieee ;
USE ieee.std logic 1164.all ; Load L
USE ieee.std logic unsigned.all ; Up/down U 24
Q
ENTITY prob721 IS 24
PORT ( R : IN STD LOGIC VECTOR(23 DOWNTO 0) ; R
Clock, Resetn, L, U : IN STD LOGIC ;
Q : BUFFER STD LOGIC VECTOR(23 DOWNTO 0) ) ; Clock
END prob721 ;
Resetn
ARCHITECTURE Behavior OF prob721 IS
BEGIN
PROCESS ( Clock, Resetn )
BEGIN Parallel load,
IF Resetn = ’0’ THEN
Q <= (OTHERS => ’0’) ; asynch reset
ELSIF Clock’EVENT AND Clock = ’1’ THEN
IF L = ’1’ THEN Q <= R ;
ELSIF U = ’1’ THEN Q <= Q+1 ;
ELSE Q <= Q−1 ;
END IF ;
END IF ;
END PROCESS ;
END Behavior ;
Bus Structures (Sect 7.14.1)
• Bus (a set of wires) common in computers
• Used to transfer data between devices
• Many devices can be attached to the bus
• Only one device can “drive” the bus at a time
• Control signals determine which device can drive

ROM Graphics RAM

data bus

CPU Hard Disk CD

 Example – a bunch of
registers on a bus
external input source

common
clock

3-state
buffers
control signals

says what task to do

 Example Task
• Assume we have 3 registers R1, R2, R3
• Task is to swap R1 and R2, using R3 for
temporary storage
• 3 steps:
1. Copy contents of R2 into R3
2. Copy contents of R1 into R2
3. Copy contents of R3 into R1
• This is done in 3 clock cycles:
1. Assert R2out, R3in
2. Assert R1out, R2in
3. Assert R3out, R1in
 Control Circuit
• Control circuit needs to generate the control signals
R1in, R1out, R2in, R2out, etc
• One possibility is a shift register:

When w changes to 1, swap operation starts at the next clock cycle

 Better control circuit
• When w changes to 1, want to start swap sequence right way, not
wait another cycle
• This circuit does that:
Timing simulation
VHDL implementation – registers
ENTITY regn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;

ARCHITECTURE Behavior OF regn IS

BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Rin = '1' THEN
Q <= R ;
END IF ;
END PROCESS ;
END Behavior ;
VHDL – tristate buffers
ENTITY trin IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
E : IN STD_LOGIC ;
F : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END trin ;

ARCHITECTURE Behavior OF trin IS

BEGIN
F <= (OTHERS => 'Z') WHEN E = '0' ELSE X ;
END Behavior ;
VHDL – shift register
ENTITY shiftr IS -- left-to-right shift register with async reset
GENERIC ( K : INTEGER := 4 ) ;
PORT ( Resetn, Clock, w : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(1 TO K) ) ;
END shiftr ;

ARCHITECTURE Behavior OF shiftr IS

BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Genbits: FOR i IN K DOWNTO 2 LOOP
Q(i) <= Q(i-1) ;
END LOOP ;
Q(1) <= w ;
END IF ;
END PROCESS ;
END Behavior ;
 VHDL top level
ENTITY swap IS
PORT ( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Resetn, w : IN STD_LOGIC ;
Clock, Extern : IN STD_LOGIC ;
RinExt : IN STD_LOGIC_VECTOR(1 TO 3) ;
BusWires : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END swap ;

ARCHITECTURE Behavior OF swap IS

SIGNAL Rin, Rout, Q : STD_LOGIC_VECTOR(1 TO 3) ;
SIGNAL R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
BEGIN
control: shiftr GENERIC MAP ( K => 3 )
PORT MAP ( Resetn, Clock, w, Q ) ;
Rin(1) <= RinExt(1) OR Q(3) ;
Rin(2) <= RinExt(2) OR Q(2) ;
Rin(3) <= RinExt(3) OR Q(1) ;
Rout(1) <= Q(2) ; Rout(2) <= Q(1) ; Rout(3) <= Q(3) ;

tri_ext: trin PORT MAP ( Data, Extern, BusWires ) ;

reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;
reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;
reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;
tri1: trin PORT MAP ( R1, Rout(1), BusWires ) ;
tri2: trin PORT MAP ( R2, Rout(2), BusWires ) ;
tri3: trin PORT MAP ( R3, Rout(3), BusWires ) ;
END Behavior ;