Академический Документы
Профессиональный Документы
Культура Документы
RA1511004010352
reg Q=0;
reg Qb=1;
always @(S or R or posedge(clk))
begin
if(clk==1)
begin
if(S==1&R==0)
begin
Q<=1; Qb<=0;
end
if (S==0&R==1)
begin
Q<=0; Q<=1;
end
end
end
endmodule
Output:
Pradyumna Hegade
RA1511004010352
Pradyumna Hegade
RA1511004010352
Q2. Use CASE statement to design negative edge triggered JK and T flip flop.
JK Flip Flop
Main code: Testbench Code:
module JKff_bh(Q,Q1,J,K,clk);
output Q,Q1;
input J,K,clk;
reg Q,Q1;
initial
begin
Q=1'b0; Q1=1'b1;
end
always @ (negedge clk)
begin
case({J,K})
{1'b0,1'b0}:begin Q=Q; Q1=Q1; end
{1'b0,1'b1}: begin Q=1'b0; Q1=1'b1; end
{1'b1,1'b0}:begin Q=1'b1; Q1=1'b0; end
{1'b1,1'b1}: begin Q=~Q; Q1=~Q1; end
endcase
end
endmodule
Output:
Pradyumna Hegade
RA1511004010352
Pradyumna Hegade
RA1511004010352
T Flip Flop
Main code: Testbench Code:
module Tff_bh(Q,Q1,T,clk);
output Q,Q1;
input T,clk;
reg Q,Q1;
initial
begin
Q=1'b0; Q1=1'b1;
end
always @ (negedge clk)
begin
case(T)
(1'b0):begin Q=Q; Q1=Q1; end
(1'b1):begin Q=~Q; Q1=~Q1; end
endcase
end
endmodule
Output:
Pradyumna Hegade
RA1511004010352
Pradyumna Hegade
RA1511004010352
Q3. Use T flip flop as a sub module to design 4-bit ripple counter.
4-bit Ripple Counter
Main code: Testbench Code:
Output:
Q4. Use behavioral model to design Up-Down Counter. When Mode=1, do up counting for
Mode=0, do down counting.
Up-Down Counter
Main code: Testbench Code:
Pradyumna Hegade
RA1511004010352
Pradyumna Hegade
RA1511004010352
Mode 1:
Pradyumna Hegade
RA1511004010352