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• Overview
– Programming languages
High-level language, assembly language, machine code
– Register organisation of MC68000
– Assembly language program
Statement structure, program structure, assembly directives
– Instruction set
– Addressing modes
Direct, immediate, absolute, indirect, relative
• References
A. Clements, “The principles of computer hardware,” Chapters 5, 6.
Programming Languages
Introduction
• All modern computer systems are built upon the von Neumann
model: a general-purpose processor, called the central processing
unit or CPU, is used to perform arithmetic-logical operations, and a
memory is used to store programs and data.
• Data is the object to be manipulated by the computer, and a program
is a collection of instructions, defining how to manipulate the data.
I/O
CPU Memory
devices
Bus
Architecture of a computer system
• The memory in a computer system can only store binary numbers.
Therefore the programs must be encoded into binary numbers –
called machine code or binary code.
• Usually different CPUs (e.g. Pentium or Motorola) use different
binary codes to represent the same operation.
• In earlier years, people wrote programs directly using the machine
code. For example, the following program
0011 1010 0011 1000 ($3A38)
0001 0010 0000 0000 ($1200) Reminder:
1101 1010 0111 1000 ($DA78) 1 hex digits = 4 bits
0001 0010 0000 0010 ($1202) So 3A = 8 bits = 1 byte
0011 0001 1100 0111 ($31C5) 1200 = 16 bits = 2 bytes
0001 0010 0000 0100 ($1204)
may encode the operations of fetching two numbers from the
memory, adding them, and saving the sum back into the memory.
• The binary instructions are understood by the CPU and are ready for
execution; but human programmers have great difficulty in
understanding them!
• Today, programming has become easier, and programs may be
developed by using programming languages, at either a high level
or a low level.
• Examples of high-level programming languages include Basic,
Fortran, Pascal, Cobal, C, C++, Java, … (some people view C as an
intermediate language).
• Low-level programming languages particularly refer to the assembly
languages.
1.2 High level language vs. assembly language
Assembler
• Programs in different levels are differentiated by their extensions,
e.g. high-level - .c, .java; assembly - .asm; binary - .obj, .bin, .exe.
“obj” means object, “bin” means binary, “exe” means executable.
• Because an assembly instruction is just a symbolic form of a
machine instruction, it is possible to obtain the equivalent assembly
program from the binary program by using a disassembler.
Disassembler Assembler
Bit no: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1
Op-code Operand(s)
The first field is called op-code (operation code), which defines the
operation to be conducted (e.g. ADD, SUB, AND, OR ...); the
second field, if existing, contains operand(s), which correspond to
the data to be processed by the instruction.
• While the MC68000 is internally 32 bits wide, it has a only 16-bit
data bus and thus fetches/sends only 16 bits at a time from/to the
memory. So, by definition, in MC68000, a word is 16 bits (2 bytes)
wide, and a long word is 32 bits (4 bytes) wide.
2.2 Data register model
• Data registers are used to hold temporary or intermediate results
during a calculation, so that these can be accessed much faster than
writing to memory then reading back.
• In addition, data registers can be used to hold frequently-used
operands thereby reducing the number of accesses to the main
memory. This can significantly speed up the execution.
• In the MC68000, three type of operations – byte (.B), word (.W)
and long word (.L) – can be applied to the data register, which
affect its lower 8, 16 and the complete 32 bits, respectively; the
other unused bits will not be affected.
• The result of operation will set the CCR.
• The MC68000 data register model:
D00 to D31 are used to denote the individual bits in a data register.
D31 D16 D15 D08 D07 D00 D0
D1
..
.
D7
Byte (.B)
Word (.W)
Word (.W)
24 bit address
Instruction
Address
Memory
$400 3 A 3 C
$402 5 8 5 8
$404 DA 7 8
2.5 Condition code register
• The CCR is an 8-bit register, included as part of the processor’s
status register. The definition of CCR, and its relationship with the
ALU are shown as follows.
• The CCR contains five flag bits, which are set by the ALU, to hold
information about the result of an arithmetic or logical operation
instruction that has just been executed.
Pre: D0 5 5 5 5 5 5 8 2 Post: D0 5 5 5 5 5 5 8 2
D1 3 3 3 3 3 3 2 8 D1 3 3 3 3 3 3 A A
Pre: D1 1 2 3 4 5 6 7 8 Post: D1 1 2 3 4 5 6 7 8
D3 0 0 0 0 0 0 0 0 D3 1 2 3 4 5 6 7 8
Pre: A1 3 6 2 2 3 4 5 6 Post: A1 3 6 2 2 3 4 5 6
D3 0 0 0 0 8 8 8 8 D3 0 0 0 0 B C D E
Pre: D5 F F F F 0 0 0 0 Post: D5
• Example: Add two numbers using immediate addressing
NUM EQU $47
ORG $400
CLR.W D1 * D1 0: clear a word of D1
MOVE.B #NUM, D1 * put $47 into D1.B
MOVE.B #$62, D2 * put $62 into D2.B
ADD.B D2, D1 * D1.B D1.B + D2.B
* so D1.B = $47 + $62 = $A9
MOVE.B #9, D0 * exit from program
TRAP #15
5.2.3 Absolute addressing
• This mode refers to the actual memory location where the operand
is stored. For example,
MOVE.W $4000, D0 * source ea is a location in memory
SUB.W D0, $4002 * dest. ea is a location in memory
• In a real program, the address would normally be referred to by a
label (see previous discussions for label, DC, DS).
• Example:
SUB.W D0, DATA * dest. ea is a memory cell
* at location DATA
Operation: Mem[DATA] Mem[DATA] – D0. Effect: e.g.
Memory Memory
Pre: DATA 4 4 A B Post: DATA 3 2 7 7
D0 0 0 0 0 1 2 3 4 D0 0 0 0 0 1 2 3 4
5.3 Example summarizing simple addressing modes
• The following shows some possible addressing modes for the
function ADD <ea>, D3.
NUM EQU $1234
ORG $4000
DATA DC.W $1234
ORG $400
ADD.W D0, D3 * data register direct
ADD.W A0, D3 * address register direct
ADD.W DATA, D3 * absolute refer to a specific
ADD.W $4002, D3 * absolute memory location
ADD.W #NUM, D3 * immediate (word) refer to an
ADD.L #$12345678, D3 * immediate (long) actual value
MOVE.B #9, D0 * exit from program
TRAP #15
5.4 Instruction set summary
• The MC68000’s instructions may be classified into four main types
– Data movement instructions
move data between memory locations, general-purpose
registers, e.g. MOVE, LEA
– Arithmetic and logical instructions
perform arithmetic or logical operations on binary numbers,
memory locations and registers, e.g. ADD, SUB, AND, OR
– Program control instructions
perform branches, jumps and subroutine calls to control the
sequence of program execution, e.g. JMP, JSR, BRA, BEQ etc.
– System control instructions
instructions which call system routines for handling exceptions,
privileging interrupt requests, and transferring control, etc., e.g.
TRAP
• The above classification is also applicable to the instruction sets of
many other microprocessors.
• For a full description of the above instructions, see the Practical
Booklet, in particular the table called Addressing Modes.
– Columns Mnemonic (instruction) and Boolean (operation) are
the most relevant.
– Use these two columns to investigate MC68000 instruction set.
– For conditional branch instructions Bcc (branch on condition
cc), see table Conditional Tests, which gives the available
condition-codes cc. Branches will be discussed in the next
chapter: program flow control.
• In the following we investigate some examples, to show how the
instruction set could be studied.
5.5 Examples of instructions
• Data movement instruction
Mnemonic: MOVE
Qualifiers: .B, .W, .L
Operation: destination operand source operand
Permissible Addressing modes:
Source Destination Source Destination
register register or in short <ea> <ea>
register memory ea may be
memory register a register
immediate register a memory location
immediate memory an immediate data
memory memory
• Rather than attempting to memorize a table like this for each
instruction learn the following two general principles about
addressing.
• Principle 1: The immediate mode cannot be used for the
destination operand. Immediate mode creates a constant value
encoded in one of the operand fields of the instruction. It does not
make sense for this to be the place where a result is stored.
• Principle 2: In dual-operand operations both operands cannot be
memory references. This follows from the organization of the
MC68000 CPU. The two data paths to the ALU come from the
bank of data registers and a temporary register (MBR). One
memory operand can be placed in the MBR but the other must
come from a register or be an immediate operand.
• The MOVE instruction looks like an exception to this last principle
(see last line of table) but if you think about it the MOVE
instruction is not really a dual-operand operation. It retrieves one
value from one location and stores it in another. This one value can
be retrieved from memory, placed in the MBR, passed through the
ALU and stored back in a different memory location.
• Example: Moving a byte, word and long word from memory.
Memory
DATA 1 1 2 2
3 3 4 4
E.g. D0 0 0 0 0 0 0 0 0
MOVE.B DATA, D0 0 0 0 0 0 0 1 1
MOVE.W DATA, D0 0 0 0 0 1 1 2 2
MOVE.L DATA, D0 1 1 2 2 3 3 4 4
A1 0 0 0 0 0 0 0 0 A1 0 0 0 0 4 0 0 0
• Note, that the address and not the contents of that address are
loaded into the address register, unlike: MOVE.W DATA, A1.
• Arithmetic Add, Subtract Instructions
Mnemonics: ADD, SUB
Qualifiers: .B, .W, .L
Operation:
ADD: destination operand destination operand + source operand
SUB: destination operand destination operand – source operand
Permissible Addressing modes:
Source Destination
Dn <ea>
<ea> Dn
• The above indicates that: ADD <ea>, <ea> with both ea’s being
memory references is not allowed; (of course the immediate data
#d, d denoting a numeric value, can never be the destination’s ea).
• Several variations, e.g.: ADDA <ea>, An; ADDI #d, <ea>;
ADDQ #d, <ea> – make the ea’s more specific (A – address
register, I – immediate, Q – quick) .
• Example: a sample program to evaluate ([A]+[B])–[C]
A EQU $4000 * assume Mem[$4000] contains $55
B EQU $4002 * assume Mem[$4002] contains $66
C EQU $4004 * assume Mem[$4004] contains $11
ORG $400
MOVE.B A, D1 * D1.B $55
ADD.B B, D1 * D1.B D1.B + $66 = $BB
MOVE.B C, D0 * D0.B $11
SUB.B D0, D1 * D1 D1 – D0 = $BB – $11 = $AA
MOVE.B #3, D0 * print value in D1 on screen in decimal form
TRAP #15 (see Practical Booklet for TRAP instruction)
MOVE.B #9, D0 * exit from program
TRAP #15
• Example: For greater range, use multiple-word arithmetic
– If D0 and D1 contain one 64-bit integer and D2 and D3 contain
another 64-bit integer, they can be added using a pair of
instructions in sequence:
ADD.L D1, D3 * add lower-order 32-bit words
ADDX.L D0, D2 * add higher-order 32-bit words
– The first add operation: D3 D3 + D1, and may produce a
carry into the extend flag X in the CCR (Ch3, S4.2.4).
– ADDX (ADD with extend) includes the flag X into the addition,
operation: D2 D2 + D0 + X.
ADDX.L ADD.L
D0 5 5 5 5 5 5 5 5 D1 8 8 8 8 8 8 8 8
D2 6 6 6 6 9 9 9 9 + D3 9 0 0 0 0 0 0 0
+ 1 X
carry
Result: D2 B B B B D D D F D3 1 8 8 8 8 8 8 8
• Logical AND, OR instructions
Mnemonics: AND, OR
Qualifiers: .B, .W, .L
Operation:
AND: dest. operand dest. operand AND source operand
OR: dest. operand dest. operand OR source operand
Permissible Addressing modes:
Source Destination
Dn <ea>
<ea> Dn
• Variations: ANDI, ORI
Permissible Addressing modes:
Source Destination
#d <ea>
d is a numeric value, may be byte, word or long word, depending
on the specific operation.
• Example (mask): ANDI.W #$000F, D0
31 16 15 0
Pre:
D0 anything 1101 0010 1101 1010
Post: A1 0 0 0 0 4 0 0 0
D3 0 0 0 0 B B B B
• Four variations: address register indirect with auto-increment, auto-
decrement; with offset; and with index. These support variable
addresses or addresses decided at run-time.
6.2.1 Address register indirect with post-increment
• The address held in an address register is incremented
automatically after the operand has been accessed, to point to the
next operand. The increment would be 1 (byte), 2 (bytes) and 4
(bytes), respectively, for byte (.B), word (.W) and long word (.L)
operations.
• This is written as (An)+. For example:
MOVE.W (A3)+, D2
Operation: D2 Mem[A3], A3 A3 + 2
Effect: e.g. Address Memory
Pre: A3 0 0 0 0 4 0 0 0 4000 2 2 2 2
D2 0 0 0 0 0 0 0 0 4002 3 3 3 3
Post: A3 0 0 0 0 4 0 0 2
D2 0 0 0 0 2 2 2 2
• This post-increment facility is similar to that in C/C++/Java, which
is useful when a list of operands are to be accessed in sequence.
• Example: Suppose we have an array holding eight values 1, 2, 3, 4,
5, 6, 7, 8. A Java program which adds all elements of the array
could be written as:
class Array {
short array[ ] = {1, 2, 3, 4, 5, 6, 7, 8};
short sum = 0;
short index = 0;
short count = 8;
for(; ;) {
sum += array[index++]; // post-increment
count – –;
if(count > 0) continue;
else break;
}
}
• The corresponding assembly program:
ORG $4000
ARRAY DC.W 1, 2, 3, 4, 5, 6, 7, 8 * the word array
SUM DS.W 1 * space for the sum
ORG $400
LEA ARRAY, A1 * A1 points to ARRAY
MOVE.B #8, D1 * set up the count
CLR.W D2 * clear D2 for the sum
LOOP ADD.W (A1)+, D2 * add array element to D2
SUB.B #1, D1 * decrement the count
BNE LOOP * back to LOOP if D1>0
MOVE.W D2, SUM * result into memory
MOVE.B #9, D0 * exit from program
TRAP #15
4.2.2 Address register indirect with pre-decrement
• This is identical to the previous post-increment mode, except that
the address held in the address register is decremented before the
operand is accessed. Also, the decrement would be 1, 2 and 4
respectively, for byte, word and long word operations.
• This is written as –(An). For example:
MOVE.L –(A0), D3
Operation: A0 A0 – 4, D3 Mem[A0]
Effect: e.g.
Address Memory
Pre: A0 0 0 0 0 4 0 0 4 4000 2 2 2 2
D3 0 0 0 0 0 0 0 0
4004 5 5 5 5
Post: A0 0 0 0 0 4 0 0 0
D3 0 0 0 0 2 2 2 2
• Example: Combine pre-decrement and post-increment to
manipulate a data structure called a stack – last-in-first-out (LIFO).
ORG $4000
L1 DC.B $55, $00 * i.e. Mem[$4000] = $55
L2 DC.B $77, $00 * i.e. Mem[$4002] = $77
L3 DC.B $99 * i.e. Mem[$4004] = $99
ORG $400
LEA $8000, A0 * set up stack at $8000
MOVE.B L1, –(A0) * A0 = $7FFF, Mem[A0] $55
MOVE.B L2, –(A0) * A0 = $7FFE, Mem[A0] $77
MOVE.B L3, –(A0) * A0 = $7FFD, Mem[A0] $99
MOVE.B (A0)+, D3 * D3 Mem[A0] = $99, A0 = $7FFE
MOVE.B (A0)+, D4 * D4 Mem[A0] = $77, A0 = $7FFF
MOVE.B (A0)+, D5 * D4 Mem[A0] = $55, A0 = $8000
MOVE.B #9, D0 * exit from program
TRAP #15
6.2.3 Address register indirect with 16-bit offset
• The address of an operand is given by the content of the address
register plus an 16-bit signed offset, given as an immediate value.
• Thus ea = (An + d16), written as d16(An), where d16 is a 16-bit
two’s complement value (in the range 32768 to +32767).
• Example: MOVE.W 6(A0), D1 * source ea = (A0 + 6)
or MOVE.W LABEL(A0), D1 * if e.g. LABEL EQU 6
Operation: D1 Mem[A0 + 6]
Effect: e.g. Address Memory
Pre: A0 0 0 0 0 4 0 0 0 4000 2 2 2 2
D1 0 0 0 0 0 0 0 0 6
4006 8 8 8 8
Post: A0 0 0 0 0 4 0 0 0
D1 0 0 0 0 8 8 8 8
• Example: A contiguous storage of student records; each record has
80 bytes, including: name (30 bytes), DoB (8 bytes), level (2 bytes,
in the higher-order byte) and address (40 bytes). Write a program
accessing the levels of all students (assume 500 students).
RECORD EQU $4000 * base address of records
OFFSET EQU 38 * point to level in a record
ORG $400
LEA RECORD, A0 * A0 points to 1st record
MOVE #500, D5 * set count to 500
LOOP MOVE.B OFFSET(A0), D1 * level into D1
MOVE.B #3, D0 * output on screen
TRAP #15
ADDA #80, A0 * A0 points to next record
SUB #1, D5 * decrement the count
BNE LOOP * back to LOOP if D5>0
MOVE.B #9, D0 * exit from program
TRAP #15
6.2.4 Address register indirect with index and 8-bit offset*
• The address of an operand is given by the contents of two registers
– one must be an An and the other may be an An or a Dn – plus an
8-bit immediate value which is represented in two’s complement
and is within the range 128 to +127.
• The address is written as: d8(An, Rm), where d8 is a 8-bit signed
value, and Rm is either Am or Dm, referred to as the index register.
• This represents an ea = An + Rm + d8.
• Example: MOVE.W $10(A0, A1), D1
or MOVE.W LABEL(A0, A1), D1 * LABEL < 8 bits
Operation: D1 Mem[A0 + A1 + $10]
• This can be used to access records with variable lengths: one
register is used to point to the base address of the structure, the
other register is used to select a specific record, and d8 is used for
the offset within this record.
• Example: A typical application of addressing mode d8(An, Rm).
e.g. $10(A0, A1)
A0 holds the base of the A0
complete structure
Record 1
Record 2