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ORDERING INFORMATION
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−16803
DEVICE DESCRIPTION
Architecture
1 Test Row
9
V1
1
V2
4 13 20 1 KAF−16803 1 9 12 6
4096 (H) × 4096 (V)
LOD 9.0 × 9.0 mm Pixels
OG
RD
1
RG 20 Dark
VDD
VOUT 1 6 4 1 3 20 1 4096 1 9 12
VSS
SUB H1 H2
Each line is composed of dummy pixels, internal test different from those in the imaging array and are not counted
pixels, active buffer pixels, and valid photoactive pixels. in the active pixel count.
Dummy Pixels Image Acquisition
Within each horizontal shift register the first pixels are 11 An electronic representation of an image is formed when
dummy pixels and should not be used to determine a dark incident photons falling on the sensor plane create
reference level. electron-hole pairs within the device. These photon-induced
electrons are collected locally by the formation of potential
Internal Test
wells at each pixel site. The number of electrons collected is
The next 4 pixels are introduced into the design to
linearly dependent on light level and exposure time and
facilitate production testing. These behave differently than
non-linearly dependent on wavelength. When the pixel’s
the buffer and dark pixels and should not be used to establish
capacity is reached, excess electrons are discharged into the
a dark reference. The last three pixels in each line are also
lateral overflow drain to prevent crosstalk or ‘blooming’.
internal test pixels and should not be used to establish a dark
During the integration period, the V1 and V2 register clocks
reference.
are held at a constant (low) level.
Dark Reference Pixels
Charge Transport
Surrounding the periphery of the device is a border of light
The integrated charge from each pixel is transported to the
shielded pixels creating a dark region. Within this dark
output using a two-step process. Each line (row) of charge
region, exist light shielded pixels that include 20 leading
is first transported from the vertical CCDs to a horizontal
dark pixels on every line. There are also 20 full dark lines at
CCD register using the V1 and V2 register clocks.
the start and 9 full dark lines at the end of every frame. Under
The horizontal CCD is presented a new line on the falling
normal circumstances, these pixels do not respond to light
edge of V2 while H1 is held high. The horizontal CCDs then
and may be used as a dark reference.
transport each line, pixel by pixel, to the output structure by
Active Buffer Pixels alternately clocking the H1 and H2 pins in a complementary
There is 1 photoactive buffer row and column adjacent to fashion.
the valid photoactive pixels. These may have signals levels
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KAF−16803
Horizontal Register
Output Structure
H2 HCCD
Charge
H1 Transfer
VDD
OG
RG
RD
Floating
Diffusion VOUT
VSS
Source Source Source
Follower Follower Follower
#1 #2 #3
The output consists of a floating diffusion capacitance the reset gate (RG) is clocked to remove the signal and FD
connected to a three-stage source follower. Charge is reset to the potential applied by reset drain (RD).
presented to the floating diffusion (FD) is converted into Increased signal at the floating diffusion reduces the voltage
a voltage and is current amplified in order to drive off-chip seen at the output pin. To activate the output structure, an
loads. The resulting voltage change seen at the output is off-chip current source must be added to the VOUT pin of
linearly related to the amount of charge placed on the FD. the device. See Figure 4.
Once the signal has been sampled by the system electronics,
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KAF−16803
Output Load
VDD = +15 V
VOUT
2N3904 or
Equivalent
Buffered
Video
Output
140 W
1 kW
NOTE: Component values may be revised based on operating conditions and other design considerations.
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KAF−16803
Physical Description
SUB 1 34 V2
V2 2 33 V2
(4096, 4096)
V2 3 32 V1
V1 4 31 V1
V1 5 30 SUB
LOD 6 29 N/C
N/C 7 28 N/C
N/C 8 27 N/C
SUB* 9 26 N/C
SUB* 10 25 SUB*
SUB 11 24 N/C
OG 12 23 N/C
VDD 13 22 N/C
VOUT 14 21 N/C
VSS 15 20 H2
Pixel (1, 1)
RD 16 19 H1
RG 17 18 SUB
Notes:
1. Pins with the same name are to be tied together on the circuit board and have the same timing.
2. Unlike the KAF−16801, pins 9, 10, and, 25 are internally connected to SUB. They may be connected to SUB on the printed circuit board
or otherwise must be left floating.
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KAF−16803
IMAGING PERFORMANCE
Table 5. SPECIFICATIONS
Verification
Description Symbol Min. Nom. Max. Units Notes Plan
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KAF−16803
0.9
0.8
0.7
Quantum Efficiency
0.6
0.5
0.4
0.3
0.2
0.1
0
300 400 500 600 700 800 900 1000 1100
Wavelength (nm)
1.1
0.9
0.8
Normalized Angle Response
0.7
0.6
0.5
0.4
0.3
0.2
Horizontal
0.1
Vertical
0
Degrees
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KAF−16803
1000
100
10
Electrons
−40 −20 0 20 40 60
0.1
Integration
Read out
0.01
Temperature (5C)
Noise Floor
25
20
Noise (electrons)
15
10
−20 −10 0 10 20 30 40
Temperature (5C)
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KAF−16803
DEFECT DEFINITIONS
Point Defects A column that does not meet the CTE specification for all
Dark: A pixel which deviates by more than 6% from exposures less than the specified maximum saturation signal
neighboring pixels when illuminated to 70% of saturation. level and greater than 2 ke−.
Bright: A pixel with a dark current > 3,000 e−/pixel/sec at
A column that contains a pixel which loses more than
25°C.
250 e− under 2 ke− illumination (Trap defect).
Cluster Defect
A grouping of not more than 10 adjacent point defects. Column defects are separated by no less than 4 good
columns. No multiple column defects (double or more) will
Cluster defects are separated by no less than 4 good pixels be permitted.
in any direction.
Column and cluster defects are separated by at least 4
Column Defect good columns in the x direction.
A grouping of more than 10 point defects along a single
column.
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KAF−16803
OPERATION
Table 7. ABSOLUTE MAXIMUM RATINGS
Description Symbol Minimum Maximum Units Notes
Diode Pin Voltages VDIODE −0.5 20 V 1, 2
Power-Up Sequence
The sequence chosen to perform an initial power-up is not 1. Connect the ground pins (SUB).
critical for device reliability. A coordinated sequence may 2. Supply the appropriate biases and clocks to the
minimize noise and the following sequence is remaining pins.
recommended:
AC Operating Conditions
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KAF−16803
LOD
CLOD CLOD_V1 CLOD_V2
CV1_V2
V1 V2
CV1 CV2
CVH
CH1_H2
H2 H1
CH2 CH1
CH1_OG
RG OG
CRG COG
Table 10.
Description Label Value Unit
LOD−Sub Capacitance CLOD 6.5 nF
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KAF−16803
TIMING
Edge Alignment
H1
VHCR
H2
V1 V2
VVCR
V1, V2
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KAF−16803
Frame Timing
V2
H2
H1
90%
V1
10%
tVw
tV1r tV1f
90%
V2
10%
tV2r tV2f
Line Content
tLINE
Ä
ÇÇ Ç
ÇÇ
Ä Ç
4096 Active Pixels/Line
tV 36 37 − 4132 4133
V2 16−35 4134−4142
tHS 12−15 4143−4145
V1 1−11
ÇÇ
H1/H2 Count Values
tV te
ÇÇ
ÄÄ
H2
Internal Test Pixels Active Buffer Pixels
ÄÄ
4145
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KAF−16803
Pixel Timing
te 1 Count
tRG
RG
H1
H2
VOUT
VVRG VOD
VVSUB
VSAT
90%
RG RGAMP tRG
10%
RGLOW
tRGr tRGf
90%
H1, H2 H1,H2AMP
50%
H1LOW 10%
H2LOW
tH1 tH2
te / 2
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KAF−16803
Example Waveforms
NOTE: Video Waveform – The bottom curve was taken at the CCD output. The top curve is bandwidth limited and was measured at the
analog to digital converter.
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KAF−16803
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KAF−16803
For information on ESD and cover glass care and For quality and reliability information, please download
cleanliness, please download the Image Sensor Handling the Quality & Reliability Handbook (HBD851/D) from
and Best Practices Application Note (AN52561/D) from www.onsemi.com.
www.onsemi.com.
For information on device numbering and ordering codes,
For information on soldering recommendations, please please download the Device Nomenclature technical note
download the Soldering and Mounting Techniques (TND310/D) from www.onsemi.com.
Reference Manual (SOLDERRM/D) from
www.onsemi.com. For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
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18
KAF−16803
MECHANICAL INFORMATION
Completed Assembly
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KAF−16803
Table 13.
Wavelength Total Reflectance
420−450 ≤ 2%
450−630 ≤ 1%
630−680 ≤ 2%
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
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20
Mouser Electronics
Authorized Distributor
ON Semiconductor:
KAF-16803-ABA-DD-BA KAF-16803-ABA-DP-BA KAF-16803-ABA-DD-AE