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Abstract: Device scaling is an important part of the very large scale integration (VLSI) design to boost up the
success path of VLSI industry, which results in denser and faster integration of the devices. As technology node
moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both
are increasing with the new technology generation and affecting the performance of the overall logic circuit. The
VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices.
In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of
those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating
the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate
(LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation
results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files.
The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm
technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of
the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that
causes large circuit reliability.
Key words: LPTG buffer; power dissipation; propagation delay; scaling; nanoscale CMOS; figure of merit
DOI: 10.1088/1674-4926/34/9/095001 EEACC: 2570
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Fig. 6. Power dissipation for conventional buffer with voltage scaling. Fig. 7. Propagation delay for convention buffer with voltage scaling.
liable and accurate performance of the circuit. If input voltage It is observed from Fig. 6 that power dissipation is reduced
is uniformly on/off periodic pulse with time period tp then con with the reduction of supply voltage but propagation delay in-
and conbar are given as: creases. For 65 nm technology, where supply voltage range is
0.80 to 1.20 V, % reduction in power dissipation is 86.73%
(
0; 0 < t < tp =2; while propagation delay increases by 112.14%. For 45 nm tech-
Vin .VDD / D (7) nology, where supply voltage range is 0.72 to 1.08 V, % reduc-
VDD ; tp =2 < t < tp ;
tion in power dissipation is 85.28% while propagation delay
( increases by 114.66%. For 32 nm technology, the supply volt-
VDD ; 0 < t < tp =2; age range is 0.64 to 0.96 V, % reduction in power dissipation
Vcon .Vin / D (8)
0; tp =2 < t < tp ; is 91.64% while propagation delay increases by 155.31%. It
( is concluded from the above results that the voltage scaling is
0; 0 < t < tp =2; more efficient when technology scaled in terms of power dissi-
Vconbar .Vin / D (9) pation saving, while it is challenging to reduce the propagation
VDD ; tp =2 < t < tp :
delay.
These control signals also depend on the logic states of in- Figure 7 shows the decrease in propagation delay with cor-
put voltage. Control signals con and conbar are assigned with responding increasing in supply voltage and technology node
appropriate potential based on the logic states of the input volt- of the conventional buffer. As the power dissipation increases
age. in direct proportion with the supply voltage, so a compromise
is to be made between the propagation delay and power dis-
sipation of the conventional buffer depending upon the appli-
4. Results and discussion cation requirements. A figure of merit is utilized to decide the
4.1. Voltage scaling for CMOS conventional buffer acceptable level of propagation delay in low power VLSI cir-
cuit design. Figure of merit is the product of leakage power
HSPICE EDA tool is used for calculating power dissipa- and propagation delay of the logic circuits. The supply voltage
tion and propagation delay for the conventional CMOS buffer scaling improves the figure of merit by 78.70% when scaling
at 65 nm, 45 nm and 32 nm technology nodes. For making from 0.96 to 0.64 V for 32 nm technology node.
a fine comparison, other parameters except supply voltage of
these particular technology nodes are taken the same through- 4.2. Load scaling for CMOS conventional buffer
out the scaling of supply voltage. The supply voltage range
for different technology nodes is precisely defined before an- With the reduction in the load capacitance, both power dis-
alyzing the logic circuit because it is related to reliability of sipation and propagation delay are reduced as shown in Figs. 8
the circuit. The supply voltages for different technologies are and 9 at 65 nm, 45 nm and 32 nm technology nodes. For making
chosen so as to maintain the high noise margin with proper a fine comparison, other parameters, except load capacitance,
output function while keeping the effective work of process of these particular technology nodes are taken as the same for
parameters. According to ITRS the nominal supply voltage for scaling of load capacitance. The load capacitance range for dif-
65 nm is 1.0 V, for 45 nm it is 0.9 V, and for 32 nm node it ferent technology nodes are precisely defined before analyzing
is 0.8 V. The supply voltage range is ˙20% of the nominal the logic circuit because it is related to stability of the circuit.
value and it is 0.80 to 1.20 V for 65 nm technology node, 0.72 The ranges of load capacitances are chosen so as to optimize
to 1.08 V for 45 nm technology node and 0.64 to 0.96 V for the power dissipation and propagation delay, while controlling
32 nm technology node for precise and reliable operation of the good input output characteristics of the logic circuit.
the circuit. Figure 6 depicts the supply voltage scaling at dif- Total power dissipation is the summation of dynamic and
ferent technology nodes. static power dissipation, where dynamic power is directly pro-
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Fig. 9. Propagation delay for conventional buffer with load scaling at 4.4. Transistor width scaling for CMOS conventional
different technologies. buffer
The results for width scaling at 32 nm technology node are
portional to the load capacitance CL . It is concluded that power given in Fig. 11. The nominal supply voltage is 0.8 V at 32 nm
dissipation is reducing as load capacitance is decreased, as node. The nominal width of NMOS device is twice of the cor-
power dissipation directly depends on the load capacitance. responding channel length and it is six times in PMOS device.
Figure 9 shows that reduction in the load capacitance is reduc- The width ratio of PMOS to NMOS device is increasing from 1
ing the propagation delay. As load capacitance is decreased, the to 5. The power dissipation of conventional buffer is increased
output signal is changed rapidly and hence reduces the transi- by 438.47% while propagation delay reduces by 66.28% from
tion times at the output of conventional buffer. At 65 nm tech- width ratio scaling of 1 to 5. It is inferred that with decreasing
nology node the propagation delay is increasing with increase width ratio of the transistors, the power dissipation decreases
in the load capacitance values. with increment in the propagation delay penalty. By taking the
The load capacitance scaling improves the figure of merit appropriate transistor’s sizing, the designer made his design
by 71.54% when scaling from 2.0 to 0.1 fF for 32 nm technol- very valuable. The transistor’s width scaling improves the fig-
ogy node. ure of merit by 44.90% when scaling from 5 to 1 for 32 nm
technology node.
4.3. Technology scaling for CMOS conventional buffer
4.5. LPTG CMOS buffer
The results for technology scaling are presented in Fig. 10
at different technology nodes. It is concluded that power dis- The above discussions for a conventional CMOS buffer
sipation and propagation delay are increased with technology are presented for different scaling methods. Technology scal-
scaling. The incremental change in power dissipation with ing is the prime requirement of the future nanoscale devices
technology is due to leakage current components which are due to scaling of the various device parameters. The limitation
more dominant at lower technology node. Sub-threshold and of technology scaling is its poor figure of merit. We have pro-
gate leakage are the dominant components of leakage current posed a low power transmission gate CMOS buffer circuit for
in the very deep sub-micron regionŒ13 . The energy efficiency improving the figure of merit of the technology scaling method.
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Fig. 14. Power dissipation and propagation delay versus width ratio
for CMOS buffer.
Fig. 12. Schematic of LPTG CMOS buffer.
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5. Conclusion
Low power design is drawing a huge deal of awareness
in VLSI digital design, principally for portable high perfor-
mance systems. The quick switching of billions of transistors
Fig. 16. Power dissipation and propagation delay versus supply volt- dissipates tremendous power and overheats the chip, reducing
age for CMOS buffer.
the reliability of the chip and necessitating expensive and large
cooling systems. In this article, scaling methods like voltage
delay for both circuits are increased with increasing the tem- scaling, load scaling, technology scaling and width scaling for
perature. The increment in power dissipation is due to ther- a nanoscale CMOS buffer circuit have been analyzed. Based
mal voltage dependency of the leakage current. If we calcu- on the analysis of these scaling methods we proposed a reli-
late the % change of these two parameters then % saving of able low power transmission gate approach which effectively
power dissipation is decreasing while propagation delay in- reduces the power dissipation and enhances the reliability. Dif-
creases as temperature increasing. Leakage uncertainty is less ferent scaling variations are used to analyze the power dissi-
in the LPTG approach as compared to the conventional. The pation and propagation delay behavior in the CMOS buffer
LPTG approach is less affected, normally 64.10% figure of circuit. The necessity of future nanoscale circuits is mitiga-
merit with temperature varying from 25 to 125 ıC as compared tion of the energy consumption per cycle. The least value of
to the conventional CMOS buffer. figure of merit provides the energy efficient design at future
The effect of voltage scaling of ˙20% variations from nanoscale nodes. Our proposed approach saves power dissipa-
nominal value is analyzed for LPTG and conventional CMOS tion by 95.16% with 84.20% progress in figure of merit in the
buffer circuit. The output results are illustrated in Fig. 16 at CMOS buffer at 32 nm technology node. The LPTG approach
32 nm technology node. The rising rate of performance para- decreases the leakage current uncertainty from 0.91 to 0.43 in
meters are very slow in the LPTG approach with increasing in the CMOS buffer for reliable operation of the logic circuit in
VDD as compared to conventional circuit. the very deep submicron region.
The ˙20% power supply voltage variations are less influ-
enced, normally 73.20% figure of merit as compared to con- References
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