1.

Explain the architecture of 8086 processor with the help of neat block
diagram
8086 microprocessor Divided into two functional units which work simultaneously to increase
system speed and throughput (inst. exe. per unit time)

 Bus Interface Unit

 Execution Unit
 Bus Interface Unit – Interface to outside world and responsible for all external
operations e.g

–Sends addresses

–Fetches instructions from memory and data from mem./port

–Supports instruction queue and address relocation facility.

–QUEUE – SIX instruction bytes are fetched ahead of time (FIFO)

 Execution Unit – works in parallel to BIU and responsible for

–Execution of Instructions, providing address to BIU for fetching data/instructions

–Manipulating various registers including FLAG register.

Functional unit contains –

–Control circuits and instruction decoders

–ALU, FLAG Register, GPRs, SP, Pointers and Index register

Block diagram of 8086 microprocessor

The QUEUE

 to speedup program execution.

 the pre fetched instruction are held for EU.
 simultaneous work is done i.e. fetching & executing.
 except in case of JUMP & CALL where the queue is dumped and reloaded.
 fetching next instruction while the current instruction is under execution is called
pipelining.

Register Organization of 8086

 General Data Registers (AX, BX, CX, DX), AX is Accumulator

 Segment Registers (CS, SS, DS, ES)
 Pointer & Indexed Registers (SP, BP, SI, DI, IP)

 CS register points to the base or start of the current code segment and the IP contains the
distance or offset from this base address to fetch the next instruction byte.

 The 8086 20-bit physical address is often represented in a segment base: offset form
rather than in single no. form. CS:IP. e.g. 348A:4214.

2. What is an instruction queue? Explain its advantage.

The Instruction Queue:

1. The execution unit (EU) is supposed to decode or execute an instruction.

2. Decoding does not require the use of buses.
3. When EU is busy in decoding and executing an instruction, the BIU fetches up to six
instruction bytes for the next instructions.
4. These bytes are called as the pre-fetched bytes and they are stored in a first in first out
(FIFO) register set, which is called as a queue.

Significance of Queue:

1. As shown in the above figure, while the EU is busy in decoding the instruction
corresponding to memory location 100F0, the BIU fetches the next six instruction bytes
from locations 100F1 to 100F6 numbered as 1 to 6.
2. These instruction bytes are stored in the 6 byte queue on the first in first out (FIFO) basis.
3. When EU completes the execution of the existing instruction and becomes ready for the
next instruction, it simply reads the instruction bytes in the sequence 1, 2…. from the
Queue.
 4. Thus the Queue will always hold the instruction bytes of the next instructions to be
executed by the EU.

Pipelining:

1. The process of fetching the next instruction when the present instruction is being
executed is called as pipelining.
2. Pipelining has become possible due to the use of queue.
3. BIU (Bus Interfacing Unit) fills in the queue until the entire queue is full.
4. BIU restarts filling in the queue when at least two locations of queue are vacant.

Advantages of pipelining:

1. The execution unit always reads the next instruction byte from the queue in BIU. This is
faster than sending out an address to the memory and waiting for the next instruction byte
to come.
2. In short pipelining eliminates the waiting time of EU and speeds up the processing.
3. The 8086 BIU will not initiate a fetch unless and until there are two empty bytes in its
queue. 8086 BIU normally obtains two instruction bytes per fetch.

8086 Queue is only Six Byte long:

1. This is because the longest instruction in the instruction set of 8086 is six byte long.
2. Hence with a six byte long queue it is possible to pre-fetch even the longest instruction in
the main program.

3. What is memory segmentation? Explain its advantage

The need of memory segmentation is explained below:

1. The BIU (Bus Interfacing Unit) contains four special purpose registers called as segment
registers. These are Code Segment (CS) register, Stack Segment (SS) register, Extra
Segment (ES) register and Data Segment (DS) register.
2. All these are 16 bit registers.
3. The number of address lines in 8086 is 20. So the 8086 BIU will send out a 20 bit address
in order to access one of the 1,048,576 or 1MB memory locations.
4. But it is interesting to note that the 8086 does not work the whole 1MB memory at any
given time. However it works with only four 64 KB segments within the whole 1 MB
memory.
5. The four segment registers actually contain the upper 16 bits of the starting addresses of
the four memory segments of 64 KB each with which the 8086 is working at that instant
of time.
6. A segment is a logical unit of memory that may be up to 64 kilo bytes long.
 7. Each segment is made up of memory contiguous memory locations. It is independent,
separately addressable unit.
8. Starting addresses will always be changing. They are not fixed.
9. Figure shows one of the possible ways to position the four 64 KB segments within the 1
MB memory space of 8086.

1. There is no restriction on the locations of these segments in the memory. These segments
can be separate from each other or they can overlap.
2. In the users program there can be many segments but 8086 can deal with only four of
them at any given time because it has only four segment registers.
3. Whenever the segment orientation is to be changed, the base addresses have to be
changed and load the upper 16 bits into the corresponding segment registers.
4. Segment registers are very useful for large programming tasks that require isolation of
program code from the data code or isolation of module data from the stack information
etc.
5. Segmentation builds relocatable and re-entrant programs easily. In many cases the task of
relocating a program simply requires moving the program code and then adjusting the
code segment register to point to the base of the new code area.

Advantages of memory segmentation:

1. Segmentation provides a powerful memory management mechanism.
2. It allows programmers to partition their programs into modules that operate
independently of one another.
3. Segments allow two processes to easily share data.
4. It allows to extend the address ability of a processor i.e. segmentation allows the use of
16 bit registers to give an addressing capability of 1 MB. Without segmentation, it would
require 20 bit registers.
5. Segmentation makes it possible to separate the memory areas for stack, code and data.
6. It is possible to increase the memory size of code data or stack segments beyond 64 KB
by allotting more than one segment for each area.

4. Addressing modes refer to the different methods of addressing the

operands. Addressing modes of 8086 are as follows:

1. Immediate addressing mode-

In this mode, the operand is specified in the instruction itself. Instructions are longer but
the operands are easily identified.

Example:

MOV CL, 12H

This instruction moves 12 immediately into CL register. CL ← 12H

2. Register addressing mode-

In this mode, operands are specified using registers. This addressing mode is normally
preferred because the instructions are compact and fastest executing of all instruction
forms.

Registers may be used as source operands, destination operands or both.

Example:

MOV AX, BX

This instruction copies the contents of BX register into AX register. AX ← BX

3. Direct memory addressing mode-

In this mode, address of the operand is directly specified in the instruction. Here only the
offset address is specified, the segment being indicated by the instruction.
 Example:

MOV CL, [4321H]

This instruction moves data from location 4321H in the data segment into CL.

The physical address is calculated as

DS * 10H + 4321

Assume DS = 5000H

∴PA = 50000 + 4321 = 54321H

∴CL ← [54321H]

4. Register based indirect addressing mode-

In this mode, the effective address of the memory may be taken directly from one of the
base register or index register specified by instruction. If register is SI, DI and BX then
DS is by default segment register.

If BP is used, then SS is by default segment register.

Example:

MOV CX, [BX]

This instruction moves a word from the address pointed by BX and BX + 1 in data
segment into CL and CH respectively.

CL ← DS: [BX] and CH ← DS: [BX + 1]

Physical address can be calculated as DS * 10H + BX.

5. Register relative addressing mode-

In this mode, the operand address is calculated using one of the base registers and an 8 bit
or a 16 bit displacement.

Example:

MOV CL, [BX + 04H]

This instruction moves a byte from the address pointed by BX + 4 in data segment to CL.
 CL ← DS: [BX + 04H]

Physical address can be calculated as DS * 10H + BX + 4H.

6. Base indexed addressing mode-

Here, operand address is calculated as base register plus an index register.

Example:

MOV CL, [BX + SI]

This instruction moves a byte from the address pointed by BX + SI in data segment to
CL.

CL ← DS: [BX + SI]

Physical address can be calculated as DS * 10H + BX + SI.

7. Relative based indexed addressing mode-

In this mode, the address of the operand is calculated as the sum of base register, index
register and 8 bit or 16 bit displacement.

Example:

MOV CL, [BX + DI + 20]

This instruction moves a byte from the address pointed by BX + DI + 20H in data
segment to CL.

CL ← DS: [BX + DI + 20H]

Physical address can be calculated as DS * 10H + BX + DI + 20H.

8. Implied addressing mode-

In this mode, the operands are implied and are hence not specified in the instruction.

Example:

STC

This sets the carry flag

 5. What is the function of an assembler directive, and explain the following
assembler
directives:

An assembler directive is literally an instruction to the assembler itself. Generally there were two
things that you could want to specifically inform the assembler about:

 Which specific segment the code is targeted at. The 8086 and later processors had their
memory carved into segments and memory references always had a base that was stored
in one of the four segment registers (when you changed a context you had to consistently
deal with all four segments).
 At the assembler level itself, you may have needed to inform the assembler which
‘dialect’ you were coding in, either the native Intel or the Unix derivatives.

Note that directives are far broader that this, you should look at the documentation for the
specific assembler you are using.