14.Testing Logic Circuits
Fault Models
o Objectives
This chapter is a brief overview of testing techniques
for logic circuits and will cover the following topics:
n The stuck-at fault model.
n Path sensitizing techniques for testing combinational logic
circuits.
n Adding extra logic to sequential circuits to facilitate their
testing.
o Reading Assignment
n Chapter 11 in Brown & Vranesic.
Elec 326 14.1 Testing Logic Circuits
o The Stuck-At Fault Model
n Assumes that all faults result in a behavior that can be
treated as wires stuck at a valid logic 0 or 1.
u w/0 or s-a-0 denotes that wire w is stuck at 0.
u w/1 or s-a-1 denotes that wire w is stuck at 1.
n Although many faults are not accurately modeled by the
stuck-at model, it is widely used because
u It is easy to use in developing testing algorithms.
u Many faults act if they were stuck-at faults.
u While it may miss some types of faults it detects many.
n The use of the stuck-at model has more limitations when
used to model CMOS faults that with some other circuit
families.
Elec 326 14.3 Testing Logic Circuits
14.1.
o Fault models are models used to represent the way
that circuits can fail.
n Like all models, no one model can represent all possible
types of failure, and it is important for the user to
understand the assumptions behind the model and their
resulting restrictions on its use.
n Different circuit families (e.g., TTL, CMOS, etc.) and
fabrication methods (e.g., PC board, ICs, etc.) can fail in
different ways.
u CMOS faults are especially difficult to model accurately because
CMOS circuits can fail in ways that turn a combinational circuit
into a sequential circuit or produce signal values that are not valid
logic signals.
Elec 326 14.2 Testing Logic Circuits
15.2. Testing Combinational Circuits
o We test circuits by applying a sequence of input
signals and observing the resulting output signals to
determine if they are correct.
n The values applied to the input terminals of a circuit at a
point in time is called a test vector.
n A set of test vectors is called a test set. The vectors in a test
set are applied sequentially to input terminals of a circuit.
n The number of test vectors in a test set is a measure of the
complexity of that test set.
n The effectiveness of a test set, called its fault coverage, is
determined by what percentage of faults it detects.
u For a given test set, its fault coverage is determined by simulating a
circuit with one of the possible faults with all the test vectors to see
if it is detected, and doing this for each possible fault.
Elec 326 14.4 Testing Logic Circuits
1
o Combinational circuit testing
n Since the inputs of a combinational circuit uniquely
determine its outputs, a test set consisting of all possible
input vectors would always work.
u For large circuits, this test set would be too large to be practical (2 k
test vectors for a k-input circuit).
l For a 75 input circuit there are 3.8x10 22 test vectors. At 1ms per test, it would
take over a billion years to test this circuit this way.
u A single test vector will frequently test for more than one fault, and
what we need is a minimal test set that will test for and discover all
possible faults. Such a set is usually much smaller that the set of all
possible inputs.
n We could find a minimal test by list all the faults detected
by each possible input vector and then picking a subset of
those that covers all faults.
u However, this not only requires analyzing a circuit for each input
vector (a complicated step), but also selecting a minimal test set
using the results of this analysis.
Elec 326 14.5
o Path Sensitizing
n This is a technique of activating paths in the circuit that
start at a gate output or network input terminal and end at a
network output terminal.
n Such a path is sensitized (or activated) if a signal change at
the gate output or input terminal results in a signal change
at the output terminal, when there are no faults on the path.
n If a wire on a sensitized path is stuck, then changing the
input will not result in the output signal changing,
indicating a fault somewhere on the path.
u Note that this only detects a fault, it does not locate it, except that it
is on the path.
n A path is sensitized if when
u The path goes through an input of an AND or NAND gate, the
other inputs to that gate are 1.
u The path goes through an input of an OR or NOR gate, the other
inputs are 0.
Testing Logic Circuits Elec 326 14.6 Testing Logic Circuits

n Example n Observations
u This technique will work for simple circuits in which there is no
A w1 fan-out of signals (i.e., the output of every gate and circuit input
w7
w2 terminal is connected to exactly one gate input circuit output
B
terminal).
w3 w10
C w4
w8 l For k input terminals, only 2k test vectors would be needed (considerably less
D than the 2 k needed to apply all possible input vectors, when k is large).
w5 w11 Y
E w6
w9 u The selection of an efficient test set is more difficult if there is fan-
F out from any of the gates or circuit input terminals, especially when
the fanned out paths reconverge.
l In some such cases it may not be possible to test all possible faults.
n The following test vectors will test for any stuck-at faults
along the indicated path.
u (0, 1, 0, x, 0, x) and (1, 1, 0, x, 0, x)
l The order of the test vector components is (A, B, C, D, E, F).
l The symbol x denotes a don't care entry; either 0 or 1 will work.
n Exercise: Construct a complete test set for this circuit.

Elec 326 14.7 Testing Logic Circuits Elec 326 14.8 Testing Logic Circuits

2
o Generating a test vector for a given fault n Example
A a
n There are two steps to construct a test vector to test for a B
d

specific fault (s-a-0 or s-a-1) on a specific wire: c

u Fault Propagation: Pick values of inputs that will sensitize a path
from the wire under test to a circuit output terminal.
u Fault Setup: Pick values for the circuit input terminals that, in a
good circuit, would force the wire under test to take on a value
opposite its stuck at value.
n To test a circuit, a test vector is constructed for each wire
and each fault type for the wire (s-a-0 or s-a-1). From the
set of test vectors obtained this way, pick a minimum
subset.
Y
e
C b
D
u Assume we want a test that will indicate an error if wire a is sa0.
l Fault Propagation: There are three possible paths from a to Y, namely (adY),
(acdY), and (aceY). First try path (adY). Setting C = D = 1 will sensitize it.
l Fault Setup: We need to set wire a to a 1 (in a fault-free circuit). Setting A or
B to 0 will do this.
l Hence the test vector (A, B, C, D) = (0, 1, 1, 1) will detect a sa0 fault at wire a.
The test vectors (1, 0, 1, 1) and (0, 0, 1, 1) will also work.
l Had we picked either of the other paths, we could not have found a test vector
this way.
t Wires b and d would have to be 1 to propagate the fault on the path (aceY). But wire a is being
tested and could be either 0 or 1 depending on whether or not it has a fault.
t To propagate the fault along path (acdY), both wires a and b must be w. But as before, wire a
could be either 0 or 1.
t The problem is due to the reconvergent paths from c to Y.

Elec 326 14.9 Testing Logic Circuits Elec 326 14.10 Testing Logic Circuits

n Now consider checking point c for a s-a-1 fault. n Assume a wire can take on any of the five values 0, 1, X, D,
or ~D.
u 0 and 1 are the standard logic values.
A a
B
d u X is don't care (either 0 or 1)
c

e
Y u D is 1 if the wire is not stuck at 0, and 0 if it is.
C b
D u ~D is 0 if the wire is not stuck at 1, and 1 if it is.
n The behavior of gates is extended to these signals as show
u Fault Propagation through path (cdY): Set a = e = 1. Since c could in the following tables:
be 0 or 1 we need to set b = 0 to force e = 1.
+ 0 1 X D ~D
u Fault Setup: To check for sa1 we need to set c to 0. Hence a and b • 0 1 X D ~D A A'

must both be 1. 0 0 0 0 0 0 0 0 1 X D ~D 0 1

l Fault setup fails because b can not be both 0 and 1. 1 0 1 X D ~D 1 1 1 1 1 1 1 0

X X 1 X X X X X
u We also fail if we try to sensitize the path (ceY). X 0 X X X X

D 0 D X D 0 D D 1 X D 1 D ~D
u Fortunately this fault is detectable; we just have to take a more
~D 0 ~D X 0 ~D ~D ~D 1 X 1 ~D ~D D
general view of path sensitization. A technique called the D-
Algorithm can be used for this.

Elec 326 14.11 Testing Logic Circuits Elec 326 14.12 Testing Logic Circuits

3
 n If we want to check a wire for s-a-0, we label it D, since it o Random Test Vectors
would be 1 if wire is not stuck at 0.
n The idea is to generate the test vectors randomly
u If we were checking for sa1 we would have labeled it ~D.
u To increase your confidence that this works, you will have to
n We now propagate the D to an output terminal using the perform fault simulation to evaluate the coverage of the test set.
five-valued truth tables above.
u It works best on circuits with low fan-in gates.
u Random test vectors can be generated by linear feedback shift
A a
register in real time. For example:
d
B
c
Y
e
C b
D

n To propagate the D to wire d we need a 1 or a D at the other

input of gate d. D turns into a ~D due to the inversion.
n To propagate the ~D to Y (it becomes D), we need a 1 or a l As the circuit is clock the sequence of bits shifted out at Y have the properties
~D on wire e and a 1 or D on wire b. of a random sequence of bits.
t This is verified by applying standard statistical tests for randomness to the generated sequence.
n To setup the fault at c we can set a and b to 1.
Elec 326 14.13 Testing Logic Circuits Elec 326 14.14 Testing Logic Circuits

14.3. Testing Sequential Circuits
o Design for Testability
n The complexity of test sets for sequential circuits is usually
much greater than for combinational circuits of
approximately the same size.
u This is due to the need to set the values of the flip-flops, which are
also inputs to the combinational part of the circuit.
u It is also complicated by the need to observe the flip-flop output
values during operation.
u Flip-flops in a typical sequential circuit are not usually available.
u Controlling and observing the flip-flop and without direct access is
extremely difficult
n To deal with the complexity of testing sequential circuits,
extra logic can be designed into the circuits. The approach
is called design for testability.
n When circuits are designed for testability, logic is usually
added to make the flip-flops accessible, so they can be
loaded and observed.
n This reduces the testing of sequential circuit to the testing
of a combinational circuit. (Remember the canonical form
of a sequential circuit).
n The problem is to build in this access to the flip-flops at a
reasonable cost. The cost is measured in several ways:
u The chip area of the extra logic needed to the access the flip-flops.
u The extra delay added by the extra logic.
u The extra pins needed to enter and observe test data.

Elec 326 14.15 Testing Logic Circuits Elec 326 14.16 Testing Logic Circuits

4
o Scan-Path Techniques n The testing process consists of the following steps to apply
n These techniques use extra logic to configure the flip-flops a test vector:
into a shift register during test. u Select Test mode (i.e., make the flip-flops a shift register).
u Test vectors are shifted in and flip-flop values shifted out, one bit at u Shift part of a test vector into the flip-flops
at time.
u Apply the rest of the test vector to the external circuit inputs.
u Record the external output signals to get part of the test outputs.
u Select normal mode (i.e., connect flip-flops to the logic network).
u Clock the flip-flops once.
u Select test mode.
u Shift the flip-flop values out to get the rest of the test outputs.

Elec 326 14.17 Testing Logic Circuits Elec 326 14.18 Testing Logic Circuits

o Signature Analysis o Bulit-In-Self-Test (BIST)

n General View
n Use a linear feedback shift register (LFSR) to probe a node
of a circuit.
u The LFSR is clocked with the same clock as the system under test.
u On each clock cycle the value of the tested node is shifted into the
LFSR.
n Specific View
u After some predetermined period of time, record the current value
in the LFSG. This value is called a signature of the tested node.
u To test the node later, use the same LFSR to record a signature for
LFSR Signature
the node and compare it with the signature obtained from a known Combinational
Logic
good circuit. If the don't match, there has been a fault. LFSR
Scan Out LFSR Signature
n A significant advantage of this technique is the reduction in
Flip-Flops
the amount of test results that must be saved. (Scan SR)

u The effect is to compress the test data collected to a more Scan In

manageable amount. LFSR

Elec 326 14.19 Testing Logic Circuits Elec 326 14.20 Testing Logic Circuits

5
o Built-In Logic block Observer 14.4. Tips and Tricks
n This is an example of built in self test in which the flip- o Don't even consider functional testing except for very
flops are organized into linear feedback shift registers for small combinational circuits.
testing. o Use automatic test generation programs.
n The circuit under test is usually divided into parts that are o Be sure you understand the limitations of the fault
connected by registers. models.

14.5. Pitfalls
o Not adding logic for built in testing

u To test network 1, make the left LFSR a random signal generator

and the right LFSR a signature analyzer.
u To test network 2, make the right LFSR a random signal generator
and the left LFSR a signature analyzer.
Elec 326 14.21 Testing Logic Circuits Elec 326 14.22 Testing Logic Circuits

14.6. Review
o The stuck-at fault model and its limitations
o The techniques for testing combinational circuits
n Path sensitization to observe interior points in the circuit by
fault propagation.
n Setting up paths to activate fault sites and checking for
consistency.
n Increasing the allowable access paths for fault propagation
using the D algorithm.
o Design for testability techniques for testing sequential
circuits
n Scan-path techniques
n Signature analysis and built-in self-test

Elec 326 14.23 Testing Logic Circuits