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UM0044

User manual

FlashLINK JTAG programming cable for PSD and uPSD

Features
● Allows PC or Notebook parallel port to program uPSD and PSD devices using PSDsoft
Express software development tool.
● Supports IEEE 1149.1 JTAG signals (TCK, TMS, TDI, TDO).
● Supports additional signals (TSTAT and TERR) to reduce programming time.
● Single FlashLINK Cable assembly supports both 3.3V and 5V target devices with no
manual configuration. Target device may operate from 2.7V to 5.5V.
● “Flying Lead” cable included to adapt to any target connector using 0.025” square
posts.
● “LoopTest” cable included to validate PC parallel port operation.

Overview
The family of Flash PSD and uPSD devices offer In-System Programming (ISP) allowing a
completely blank device to be programmed while soldered to a circuit board. This simplifies
manufacturing and provides an effective way to update products after they are in use.
Flash PSD and uPSD devices comply to the core requirements of the IEEE 1149.1 JTAG
specification. However, these devices do not support boundary scan functions. Instead, they
support ISP, and some uPSD devices support emulation through JTAG.
The FlashLINK cable assembly shown in Figure 1 will perform ISP only on uPSD and PSD
devices, not memory or logic devices from other vendors. The software development tool
PSDsoft Express is a Windows based program which operates the FlashLINK cable
assembly (PSDsoft Express may be downloaded at no charge from www.st.com/psm).
PSDsoft Express supports device chaining, meaning more than one uPSD or PSD device
can reside in a single JTAG chain. Also, other devices (memory, logic from other vendors)
may reside in the JTAG chain, but these devices will stay in BYPASS Mode.
PSDsoft Express will generate BSDL, JAM STAPL, and SVF files for use with 3rd party
JTAG programming equipment.
The four basic JTAG pins (TCK, TMS, TDI, TDO) on uPSD devices are dedicated to operate
as JTAG pin at all times. However, the four JTAG pins on PSD devices may also be used for
general I/O functions.
ST has created two optional JTAG signals (TSTAT and TERR) to reduce programming
times. These pins supply programing status on signal pins rather than having to scan out the
status serially for each byte programmed in Flash memory. Program times using this method
(6-pin JTAG) can be as much as 30% less than the standard method (4-pin JTAG).

January 2007 Rev 5 1/15


www.st.com

www.BDTIC.com/ST
UM0044

Figure 1. FlashLINK cable assembly


Flying lead
cable
Mates
with
DB-25 FlashLINK 12 WIRES Target
PC
Cable Adapter device
parallel
6 feet
port 6 inches
DB-25 Cable, M-F
straight-through wiring

AI08862

1. 14-pin ribbon cable may also be used. Not supplied in FL-101 Kit.

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UM0044 Contents

Contents

1 Pin definition on FlashLINK adaptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Connector definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Diagnostic tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1 Loop test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2 Connect Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Circuit examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 4-pin JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 6-pin JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Multiplexed JTAG (PSD only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Chaining JTAG devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Appendix A FlashLINK schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 Contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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Pin definition on FlashLINK adaptor UM0044

1 Pin definition on FlashLINK adaptor

Table 1. Pin description for 14-pin FlashLINK adaptor connector


Signal Type(1 FlashLINK is
Pin # Description )
Name Signal:

1 JEN JTAG Enable - active-low when JTAG traffic is present OC Source


JTAG Reset on target, active-low, optional per IEEE
2 TRST(2) OC Source
1149.1
3 GND(3) Signal Ground
(2)
4 CNTL Generic Control signal OC Source
5 TDI JTAG IEEE 1149.1 Serial Data Input Source
JTAG-ISP Programming Status to speed programming,
6 TSTAT Destination
optional
7 VCC(4) DC source from target, 2.7V to 5.5V
8 RST Target system reset, recommended OC Source
9 TMS JTAG IEEE 1149.1 Mode Select Source
10 GND Signal Ground
11 TCK JTAG IEEE 1149.1 Clock Source
12 GND Signal Ground
13 TDO JTAG IEEE 1149.1 Serial Data Out Destination
JTAG-ISP Programming Error Status to speed
14 TERR Destination
programming, optional

Note: 1 OC = Open Collector, pulled-up to VCC inside FlashLINK Adaptor.


2 Not supported by PSDsoft Express, signals remain inactive.
3 All signal grounds are tied together inside FlashLINK Adaptor.
4 The target must supply VCC to the FlashLINK Adaptor (2.7V to 5.5VDC, 15mA max at 5.5V).
Not all 14 signals are required for all applications. Here is how they are used:
● (6) Core signals that must be connected: TDI, TDO, TMS, TCK, VCC, GND
● (2) Optional signals that reduce programming time as much as 30%: TSTAT and TERR
● (1) Optional signal to control multiplexing of JTAG signals (PSD only) or to indicate
JTAG activity: JEN
● (1) Optional IEEE-1149.1 signal for JTAG chain reset: TRST
● (1) Optional (but recommended) signal to allow FlashLINK to reset target system after
ISP: RST
● (1) Optional generic control signal to target system from FlashLINK: CNTL
● (2) Two additional ground lines to help reduce EMI if a ribbon cable is used. These
ground lines “sandwich” the TCK signal in the ribbon cable. These two ground signals
are not present on the flying lead cable.

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UM0044 Connector definition

2 Connector definition

There is no industry standard JTAG connector. Each device manufacturer differs. ST has a
specific connector and pinout for the FlashLINK Adaptor. The connector scheme on the
FlashLINK connector can accept a standard 14-pin ribbon cable connector (2 rows of 7 pins
on 0.1” centers, standard keying) or any other user specific connector that can slide onto
0.025” square posts. The pinout for the FlashLINK Adaptor connector is shown in Figure 2.
A standard ribbon cable is a good way to quickly connect to the target circuit board. If a
ribbon cable is used, then the receiving connector on the target system should be the same
connector type with the same pinout as the FlashLINK Adaptor shown in Figure 2.
Note: The JTAG signal TDI is sourced from the FlashLINK Adaptor and should be routed on the
target circuit board so that it connects to the TDI input pin of the PSD or uPSD device.
The JTAG signal TDO is an input received by the FlashLINK Adaptor and is sourced by the
PSD or uPSD device on its TDO output pin. See Figure 3 on page 8, Figure 4 on page 9,
and Figure 5 on page 10 for more information.

Figure 2. Pinout for FlashLINK adaptor and target system JTAG connector

14 13
TERR TDO(1)
12 11
GND TCK
10 9
GND TMS
KEY
8 7
WAY
RST VCC
6 5
TSTAT TDI(2)
4 3
CNTL GND
2 1
TRST JEN

AI08867

Note: This diagram perspective is looking into the face of the shrouded male connector on the
FlashLINK Adaptor, 0.025-inch (0.635mm) posts on 0.100-inch (2.54mm) centers.
Connector reference: Molex 70247-1401.
Recommended ribbon cables for quick connection of the FlashLINK Adaptor to the end-
product: Samtec HCSD-07-D-06.00-01-S-N; Digikey M3CCD-14065-ND.
Note: 1 TDO is a signal destination on the FlashLINK and a signal source on the target board.
2 TDI is a signal source on the FlashLINK and a signal destination on the target board.

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Software UM0044

3 Software

The FlashLINK cable assembly is driven by the software development tool PSDsoft Express
(available at no charge from www.st.com/psm). With this tool you define the pin functions,
memory map, and PLD configuration of PSD or uPSD devices, add microcontroller firmware
to be programmed into Flash memory, then generate a single file to program into the device
(an object file with the filename extension *.obj). PSDsoft Express will then use the
FlashLINK cable assembly to program this object file into the PSD or uPSD device. Other
operations include erase, verify, upload, and blank check. See the PSDsoft Express User
Manual for more detail.
Note: Be sure to use the latest version of PSDsoft Express. Updates are available from
www.st.com/psm.

3.1 Diagnostic tests


PSDsoft Express also performs some diagnostic tests for the PC parallel port and
FlashLINK cable assembly.

3.1.1 Loop test


Should be run first to test basic operation of the PC parallel port and the FlashLINK cable
assembly. “LoopTest” will wrap FlashLINK signal outputs back into FlashLINK signal inputs
for signal path verification.

3.1.2 Connect test


Is optional to test system performance and check the JTAG signal path all the way through
the target circuit board including PSD or uPSD device.
To run these tests, install and run PSDsoft Express on your PC or laptop:
1. Connect the six foot long DB-25 cable to your PC parallel port on one side, and to the
FlashLINK Adaptor on the other side.
2. Click mouse on the JTAG ISP programmer box at the bottom-left of the PSDsoft
Express main flow diagram.
3. Select single or multiple JTAG devices depending on your target configuration (single is
most common), then click on the Hardware Setup (“HW Setup”) box at the lower part of
the JTAG Operations window.
For “LoopTest”:
1. Connect the small loop test adaptor cable (not the flying lead cable) to the 14-pin
connector on the FlashLINK Adaptor.
2. Connect the red lead of the loop test connector to a VCC source (5V or 3.3V), and
connect the black lead of the loop test connector to ground.
3. In the “HW Setup” box click the “Loop Test” box to run the test. If it fails, be sure that
your are supplying VCC and ground, and also make sure that the PC’s parallel port is
enabled.
For “Connect Test”:

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UM0044 Software

1. Connect the “Flying Lead” cable, or a ribbon cable to the FlashLINK Adaptor, and also
connect it to your target circuit board just as if you are ready to program the device.
2. Turn on the power on the target device, and then click the “Connect Test” button in the
“HW Setup” box.
This test involves the circuit traces on your circuit board. If there is a failure, it is likely due to
signal routing or signal integrity on the target circuit board, or the PC may have compatibility
problems with the parallel port driver used by PSDsoft Express.
Note: If either test fails, you will see a window pop-up that allows you to email in the problem.
Please do so and we will assist you.

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Circuit examples UM0044

4 Circuit examples

4.1 4-pin JTAG


The first example shown in Figure 3 uses the standard JTAG signals (4-pin JTAG). This is
the default configuration in PSDsoft Express (4-pin JTAG).
Note: The recommended pull-up resistors and decoupling capacitor are near the JTAG connector.

Figure 3. Circuit example for 4-pin JTAG

SIGNAL
DIRECTION 100k 100k 10k
USER PC BOARD
DURING 100k 100k
JTAG JTAG
OPERATION CONN.

TMS - PC0 TMS


TCK - PC1 TCK
VSTBY or I/O - PC2
GENERAL I/O - PC3
GENERAL I/O - PC4
TDI - PC5 TDI JTAG
PROGRAMMING
TDO - PC6 TDO OR TEST
EQUIPMENT
GENERAL I/O - PC7 VCC (1)(2) CONNECTS HERE

0.01
µF
µPSD or PSD Port C
GND
RST

USER I/O
SYSTEM
SIGNALS
RESET
CIRCUITY
(connect
directly to
RESET
Input on
µPSD)

AI08864b

Note: 1 For 5V uPSD3xxx devices, pull-up resistors and VCC pin on the JTAG connector should be
connected to 5V system VDD.
2 For 3.3V uPSD3xxx devices, pull-up resistors and VCC pin on the JTAG connector should be
connected to 3.3V system VCC.

4.2 6-pin JTAG


The second example in Figure 4 uses the two additional (and optional) JTAG signals TSTAT
and TERR to reduce programming time.
To configure this in PSDsoft Express, just click on pin PC3 or pin PC4 and choose
“Dedicated JTAG” function. These two signals must be used as a pair, so choosing either
one for JTAG will assign both to dedicated JTAG function.

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UM0044 Circuit examples

Figure 4. Circuit example for 6-pin JTAG

100k Typ 10k

SIGNAL
DIRECTION
USER PC BOARD
DURING
JTAG JTAG
OPERATION CONN.

TMS - PC0 TMS


TCK - PC1 TCK
VSTBY or I/O - PC2
TSTAT - PC3(3) TSTAT
TERR - PC4(3) TERR JTAG
PROGRAMMING
TDI - PC5 TDI OR TEST
EQUIPMENT
TDO - PC6 TDO CONNECTS HERE

GENERAL I/O - PC7 VCC(1)(2)


0.01
µF
µPSD or PSD Port C
GND
RST

USER I/O
SYSTEM
SIGNALS
RESET
CIRCUITY
(connect
directly to
RESET
Input on
µPSD)

AI08865b

Note: 1 For 5V uPSD3xxx devices, pull-up resistors and VCC pin on the JTAG connector should be
connected to 5V system VDD.
2 For 3.3V uPSD3xxx devices, pull-up resistors and VCC pin on the JTAG connector should be
connected to 3.3V system VCC.
3 TSTAT and TERR are not part of the IEEE 1149.1 Specification.

4.3 Multiplexed JTAG (PSD only)


The third example in Figure 5 illustrates one method to multiplex JTAG signals with general
I/O functions (PSD only, not available on uPSD). In this example, the PLD input pin at PC7
was chosen (this could be any PLD input pin) to control how the JTAG pins operate. The
signal JEN from the FlashLINK Adaptor drives PC7. When JEN is active (logic low), the
JTAG pins operate as JTAG. When JEN is inactive (logic high), the JTAG pins operate as
general I/O. You must configure this in PSDsoft Express by declaring the JTAG pins as
general I/O (not dedicated JTAG pins), then configure one PLD input pin (PC7 in this
example), then you must define an equation which will toggle the JTAG pin operation
between JTAG and general I/O.
To define this equation in PSDsoft Express:
1. Click on the “JTAG Enable Tab” in the Design Assistant window.
2. Write the equation for the internal node “jtagsel”, which controls the function of JTAG
pins (jtagsel logic high is JTAG, logic low is I/O).
For the example in Figure 5, the equation should be jtagsel = !PC7, so you would just have
to type !PC7 in the equations box and PSDsoft Express will do the rest.
Note: You can click on the “Show Eq” button to see the resultant equation.

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Circuit examples UM0044

Note: JEN controls the tri-state buffers on the general I/O pins to avoid signal conflict when
operating in JTAG Mode or General I/O Mode.

Figure 5. Circuit Example for Multiplexed JTAG pins (PSD only, not uPSD)

100k Typ
10k

SIGNAL
DIRECTION
USER PC BOARD
DURING
JTAG JTAG
OPERATION CONN.

TMS - PC0 TMS


TCK - PC1 TCK
VSTBY or I/O - PC2
TSTAT - PC3(3) TSTAT
TERR - PC4(3) TERR JTAG
PROGRAMMING
TDI - PC5 TDI OR TEST
EQUIPMENT
TDO - PC6 TDO CONNECTS HERE
PLD INPUT - PC7 JEN
VCC (1)(2)
0.01
PSD only (not µPSD) Port C µF
JEN GND
RST

SYSTEM
RESET
CIRCUITY
MISC. USER I/O SIGNALS (connect
directly to
RESET
Input on
µPSD)

AI08866b

Note: 1 For 5V uPSD3xxx devices, pull-up resistors and VCC pin on the JTAG connector should be
connected to 5V system VDD.
2 For 3.3V uPSD3xxx devices, pull-up resistors and VCC pin on the JTAG connector should be
connected to 3.3V system VCC.
3 TSTAT and TERR are not part of the IEEE 1149.1 Specification.

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UM0044 Chaining JTAG devices

5 Chaining JTAG devices

The IEEE-1149.1 specification allows chaining more than one device in a JTAG chain. uPSD
and PSD devices may be included in this JTAG chain. However, PSDsoft Express will place
devices from other vendors into BYPASS Mode, keeping them passive in the chain when
programming uPSD and PSD devices. Conversely, when other vendors’ JTAG control
software is operating the JTAG chain, uPSD and PSD devices may be placed into BYPASS
Mode. Figure 6 shows an example of a JTAG chain with three devices, including a device
from another manufacturer. This example also shows how to use 6-pin JTAG in a chaining
situation.
Chaining must be configured in PSDsoft Express:
1. Click on the JTAG ISP box in the lower-left corner of the PSDsoft Express main flow
diagram.
2. A pop-up dialog box will appear and ask how many devices are in the JTAG chain. If
you click “More than one,” you will go to the JTAG Operations window that allows you to
define the number of devices in the chain as well as their position.
Note: If you do not see this dialog box (that asks how many devices are in the JTAG chain), pull
down the “Preferences” menu of the main PSDsoft Express window and re-enable this
option (question).

Figure 6. Example of Chaining JTAG Devices

Target System, 3v or 5v VCC


FlashLink
Adapter VCC 7 7
Connector

1
9 9
TMS TMS
11 11
TCK TCK
TDI 5 5
TDI
TDO
6 optional 6
TSTAT TSTAT
optional 14
!TERR 14 TERR\

TDO 13 13 PSD or uPSD

1 optional 1 TMS 2
!JEN
!TRST 2 optional 2 TCK
(1)3 3
GND
CNTL 4 optional 4 TDI
8 recommended 8 TDO
!RST
GND
(1) 10 10
Any JTAG
GND(1) 12 12
Device in
ByPass Mode

TMS n
TCK

straight-through TDI
ribbon cable TDO
2-row, 7-position
System TSTAT
Reset PSD or
JTAG Chaining for PSD TERR\ uPSD
Circuitry
or uPSD and other JTAG-
compatible devices

AI08863

Note: 1 All Ground pins are connected together inside the FlashLINK assembly.

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12/15
Appendix A

VCC
VCC
Figure 7.
FlashLINK schematic

R3
R9 100K
10K
U1B
J1 19 U1A
G
9 8
R20 Y1 A4 R40
2 PIN2 47 11 7 6 12 TCK
R21 A1 Y2 A3 Y4 R41
3 PIN3 47 13 5 4 14 TMS
R22 A2 Y3 A2 Y3 R
4742
4 PIN4 47 15 3 GND 2 16 47 TDI
R23 A3 Y4 A1 Y2
5 PIN5 47 17 18 47
A4 Y1
6 PIN6 1
G
7 PIN7 74AC240
10 PIN10 C100 C2 C3 C1 74AC240
11 PIN11 100P 100P 100P 100P R10
12 PIN12 10K R43 JEN
14 PIN14 47
15 PIN15
18 GND

3
6
DB25-12P 1 Q2
VCC 9013
4 VCC

2
5
DB25/2 TCK
DB25/3 TMS
DB25/4 TDI R5 R6 R7 R1 R15 R16 R17 R19 R33 R18
DB25/5 JEN 4k7 4k7 4k7 470k 100K 100K 100K 10K 10K 10K
DB25/6 TRSTN VCC
DB25/7 RSTN
DB25/10 TSTAT U2D DM54ALS05A
DB25/11 VCC C7 C8
DB25/12 TDO R25 9 8 R36 TRSTN 104P 104P
47
DB25/14 CNTL 47
DB25/15 TERR
DB25/18 GND
FlashLINK adaptor schematic

U2E DM54ALS05A
R26 11 10 R34 RSTN
47
47
U2F DM54ALS05A
FlashLINK schematic

R27 13 12 R35 CNTL


47
47
U2C DM54ALS05A
R28 6 5 R37 TSTAT
47
47
U2B DM54ALS05A
R38
R29 4 3 TDO
47 47
VCCA

U2A DM54ALS05A
D10
LED R31 2 1 R39 TERR
47
47
C4 C5 C6
100P 100P 100P J2
R32 JEN TRSTN
47 1 2
R30 Q1 GND CNTL
3 4
470 9013 VCC D3 TDI TSTAT

6
3
R14 5 6
R2 1 VCCA RSTN
7 8
470K D1 D2 10 TMS GND
9 10

www.BDTIC.com/ST
4 R8 VCCA 1N5817 TCK GND
11 12

5
2
R4 D4 TDO TERR
6.2V C10 13 14
4K7 1N4148 1N4148 100K
R11 105P HEADER 7X2
10K
UM0044
UM0044 Contact information

6 Contact information

For current information on ST Flash PSD and uPSD products, please consult our pages on
the world wide web at www.st.com/psm
If you have questions or comments concerning the matters raised in this document, please
send them to: the following email address:
apps.psd@st.com

Please include your name, company, location, and phone number.

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Revision history UM0044

7 Revision history

Table 2. Document revision history


Date Revision Changes

1.0 First issue, written in WSI format


Front page, and back two pages, in ST format, added to the PDF file
30-Jan-2002 1.1 Any references to Waferscale, WSI, EasyFLASH and PSDsoft 2000
updated to ST, ST, Flash+PSD and PSDsoft Express
13-Nov-2003 2.0 Reformatted
09-Mar-2004 3.0 Republished
Figure 3, Figure 4, Figure 5 updated by adding clearer JTAG
connection labeling
06-Sep-2005 4.0
Notes associated with the above Figures renumbered
Figure 7 updated, connecting pin 13 to pin 8 for the DB25 connector
Document reformatted
26-Jan-2007 5.0
Figure 7 updated

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UM0044

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