Вы находитесь на странице: 1из 42

EE 598

Digital Design using Verilog


Lecture 5/6: Introduction to Verilog
Prof. Bo Yuan
Electrical Engineering, CCNY
Slides adapted from Mingjie Lin, Arvind, Krste Asanovic, Emil Petriu,
Wikipedia, Hakim Weatherspoon, Peter M. Nyasulu
Why HDL?
• In the beginning designs involved just a few
gates, and thus it was possible to design/verify
these circuits on paper or with breadboards
Why HDL? (ctd.)
• As designs grew larger and more complex,
designers began using gate-level models
described in a Hardware Description
Language (HDL) to help with verification
before fabrication
Why HDL? (ctd.)
• When designers began
working on 100,000 gate
designs, these gate-level
models were too low-
level for the initial
functional specification
and early high-level
design exploration
Why HDL? (ctd.)
• Designers again
turned to HDLs
specification and a
framework for help –
abstract behavioral
models written in an
HDL provided both a
precise for design
exploration
Advantages of HDLs
• Allows designers to talk about what the
hardware should do without actually
designing the hardware itself, or in other
words HDLs allow designers to separate
behavior from implementation at various
levels of abstraction
-- By using modules and interface
Advantages of HDLs (ctd.)
• Designers can develop an executable
functional specification that documents the
exact behavior of all the components and
their interfaces
• Designers can make decisions about cost,
performance, power, and area earlier in the
design process
• Designers can create tools which
automatically manipulate the design for
verification, synthesis, optimization, etc.
Advantages of HDLs (ctd.)
HDLs
• There are many different HDLs
– Verilog HDL
– ABEL
– VHDL
• Verilog is the most common in US industry
• VHDL is the most common in Europe
– Large standard developed by US DoD
– VHDL = VHSIC HDL
– VHSIC = Very High Speed Integrated Circuit
Verilog HDL
Verilog HDL is the most common in IC
industry
– Easier to use in many ways
– C - like syntax
 History
– Developed as propriety language in 1985
– Opened as public domain spec in 1990
– Became IEEE standard in 1995
Verilog vs VHDL
An HDL is NOT a
Software Programming Language
 Software Programming Language
– Language which can be translated into machine
instructions and then executed on a computer
 Hardware Description Language
– Language with syntactic and semantic support for
modeling the temporal behavior and spatial
structure of hardware
Constructs
• Verilog constructs are use defined keywords
– Examples: and, or, wire, input output

•One important construct is the module


– Modules have inputs and outputs
– Modules can be built up of Verilog primitives
or of user defined sub-modules.
A Simple Example
A Simple Example (ctd.)
Space and Comments
• White Space
-- Separate words
-- Contain spaces, tabs, new-lines and form
feeds.
-- A statement can extend over multiple lines.
 Comments are exactly the same as in C/C++:
-- For single line: Begin the comment with
double slashes (//)
-- For multiple lines: Enclose comments
between the characters /* and */.
Space and Comments (ctd.)
Numbers
• Number storage is defined as a number of bits,
Number Syntax
n’Fddd..., where
n - integer representing number of bits
F - one of four possible base formats:
b (binary), o (octal), d (decimal),
h (hexadecimal). Default is d.
dddd - legal digits for the base format
Data Type
 Value Set
-- Verilog consists of only four basic values.
Almost all Verilog data types store all these
values:
0 (logic zero, or false condition)
1 (logic one, or true condition)
x (unknown logic value)
z (high impedance state)
Data Type (ctd.)
 Wire
-- A wire represents a physical wire in a circuit and is
used to connect gates or modules.
-- The value of a wire can be read, but not assigned to,
in a function or block.
-- A wire does not store its value but must be driven
by a continuous assignment statement or by connecting
it to the output of a gate or module
Data Type (ctd.)
 A reg (register) is a data object that holds its
value from one procedural assignment to the
next.
-- They are used only in functions and procedural
blocks.
-- A reg is a Verilog variable type and does not
necessarily imply a physical register.
-- In multi-bit registers, data is stored as unsigned
numbers and no sign extension is done
Data Type (ctd.)
 These keywords declare input, output and
bidirectional ports of a module or task.
-- Input and inout ports are of type wire.
-- An output port can be configured to be of
type wire, reg. The default is wire.
Data Type (ctd.)
 Integers are general-purpose variables. For
synthesis they are used mainly loops-indicies,
parameters, and constants.
-- implicitly type reg, but store data as signed
numbers
-- reg types store as unsigned.
Operators
 Arithmetic Operator
+ (addition)
- (subtraction)
* (multiplication)
/ (division)
% (modulus)
Operators (ctd.)
 Relational Operator
< (less than)
<= (less than or equal to)
> (greater than)
>= (greater than or equal to)
== (equal to)
!= (not equal to)
Operators (ctd.)
 Bit-wise Operators
~ (bitwise NOT)
& (bitwise AND)
| (bitwise OR)
^ (bitwise XOR)
~^ or ^~(bitwise XNOR)
Operators (ctd.)
 Logical Operators
! (logical NOT)
&& (logical AND)
|| (logical OR)
Operators (ctd.)
 Reduction Operators
& (reduction AND)
| (reduction OR)
~& (reduction NAND)
~| (reduction NOR)
^ (reduction XOR)
~^ or ^~(reduction XNOR)
Operators (ctd.)
 Shift Operators
<< (shift left)
>> (shift right)
Operators (ctd.)
 Concatenation Operator
{ }(concatenation)
Operators (ctd.)
 Replication Operator
{n{item}} (n fold replication of an item)
Operators (ctd.)
 Conditional Operator: “?”
(cond) ? (result if cond true): (result if cond false)
Operands
 Reg
 Wire
 Parameters
 Bit-Selects “x[3]” and Part-Selects “x[5:3]”
variable_name[index]
variable_name[msb:lsb]
Module
 A Verilog module includes a module name and
an interface in the form of a port list
– Must specify direction and bit-width for
each port
Module (ctd.)
A module can contain other modules through
module instantiation creating a module hierarchy
– Modules are connected together with nets
– Ports are attached to nets either by position
or by name
Module (ctd.)
A module can contain other modules through
module instantiation creating a module hierarchy
– Modules are connected together with nets
– Ports are attached to nets either by position
or by name
Structural (Gate-level) Model
 Structural model is a text description of the
circuit layout.
 Verilog has all the standard gates
and, nand, or, nor, xor, xnor, not, buf
 Verilog also has the transistor-level model
Structural Model (ctd.)
Structural Model (ctd.)
Structural Model (ctd.)
Structural Model (ctd.)
Structural Model (ctd.)

Вам также может понравиться