... .

- ~-
,"".,' , _ ... "
;;r, _ - ~ ~'''''~ •_ ,
«i. ._ -', ","
"T" " "

'.

• t
Z80-CPU
,... .... Product
. .-
Specification;
-,' ' .

. ----~

~".>;-
,

Z80A-CfU • -..1. ..
, -, ,_.-"
-~. ,
.
••
mUhi~" i~'"'''P'''~n~'imi"d'~b~':Y"'",'
'.

The ZilO1: Z80 produciline is 11 compklt 5(1 of micro- ,,,,1 "d

C\lmputerlcomponenls. development systems and support
S/'flw:lre. The Z80 mil;focompuler component sel in,;ludes
:III of the- circuits nectS!i:;J.ry to build high·perfoimance
microcomputer syslem.. with virtually no other logk ;wd :I
minimum number oi lo\\;Cosl sl3nd~rd
DIlle Z80 and Z80.-\ (I'lTs art third generation single chip
";nicrnpw!!essors with \Illrivaled compul:nionaJ power. This
increased computalklllal Jlower results in higher s~'jlem
throu~h.put llnd more eflkient memory utilization when'
compared to stl'ond generation micropracessou.. In
addition, the ZBO'und Z80A CPU'.s are very c;lsy 10 imple.
ment into a system be~ause of their single volt:l~e requirt'·
ment plus all output sign:l!s are fully del;oded and tim",d 10
conuol standard memory or perillheral ciro.:uilS. The drcllil
is implem~llled usin~ an N.ehannt"l. ion implal1ted. silicUll
pIe MaS prn..:ess.
r'lgure I is:l block diagram of Ihe CPU, Figure ~ del3ils
tho: inTern",1 re!isu:r configuration \,..hieh C'ont:lins ~08 bils
Jl' R"'OId, Wn Ie memory llin .afe aCl;e.>.i-lble 10 I h~ prvgr31ll'
me~.\fh~ registers include two selS of six general purpose
registers lh:u m:lY be ~d indi'dduaUy as 80bil regislers l)f
as l6-bit regiSler pairs. There aK also IWO $tIS uf accumu·
lator and flag reglsfers. The programmer has access to eilher
stl of main ur ahemate registers Ihrough a group ot ex·
change illS( ruclhlns. This alternate set allows foreground
)ekground mode of operation or may be reserved for \'cry
last I",enupt respons.... ElI.eh CPU also contains 1I l6-biI
sl~ck pOllHer which permits simple implementalion of
-,
simplifk3tiot\ of many types of dalJ h3ndilng.
The I,WO 16-bil index rtgislers .::lilow Jdbul::tr. d31;l m:lnipu·
lalion and easy impl~menution of reloc:ll:ible .:ode. The
Reofresh regisler pro\'ides (OT :1U1On1uic. lotally H;lnsparent
memllry eler~enl s.
refresh oi external dynamic memories. The I register is used
in a powerful interrupt response mode 10 form th~ upper 8
bils of a p6illler H':.l interrupt servia address tabk. while
{he interrupting d<'\'ke supplies the lower 8 bits or the
pointer. An indirect call is then m::lde 10 this service address.
FEATURES
• Single chip. \'·,:h3nnel Silicon Gale CPU.
• 158 instructions-includes all 78 oj Ine 8080'" instruc-
tions with 101:11 witware comp:ltibility. New instruc·
lions include 4-. 8· :Illd l6-bil operations with more
useful addressin~ modes such as indrxed. bit and relative.
• 17 internal r~i:iters.
• Th~e~ mvd~:i vi '4:i1 liJleW.• !'l ro;o.l""':O;Y.e ph.:;:. no;:-
mukable mlerrupt.·
• Direclly interfa~s standard speed SUtk or dYMmi~
memories with \irlually no extem:lllugic.
• I.o./.IS instruCIJOll exeeution speed.
• Sm'glc 5 \lDC supply and single.phase 5 vult Clod...
• <>til-performs :any other single chIp microcOtnp'.Jlo." i.,
4,,8-, or 16-bit applications.
• All pins TTL Comp:ltible
, • B~ilt·in dynamic RAM refresh circl,loitry. '\

'. '-
.r .... ' •
,, D.......

.
,.
~
. ""··r
~.
• ... ~'

•
.......G.,
... .-
•
• I ~'-I
..............0. ....

' •.
,,-
"
,

._-
~

" _.
_,_,_
_. ... -'. ,.,:;~... ~ ··
•
•
,
•
•
• •
•
•
,. ¥,=:..'
_. -
. ,
-.
.......
~-
_._~ ~

.. -- I=?lg;:,-
~ J • •
.......- ... .......
" , "

~~
• . _.~

,.

•
· _ ......v

.."',_..
..
~...:..~~.~.-~~
~~
"
.• --
~,-

,,1;<1""
.
"

I rr
.. ¥~o +
--
~
.
. ,
~~..
_ ..."""'fl.
--~_ .. ,
..
• -•
_.- "

zao, Z80A CPU BLOCK DIAGRAM

".,
•
ZBO. Z80A CPU REGISTE S
•
t{' .
.. .
~

,
.... :..
,.. '*' •. ··•..-... ,.... c. , '-"".'
 ZSO, ZSOA·CPU Pin Description
.I '
.1 .. •. .. RFSH O]Jtput. active low. RFSH indicates that

-
- •• 14-" " •
,
-
•
• "
.• ..... (Refresh) th~:J"ower J bilS of me addreu bus con-
tain a refresh address for dvnamic
,
-- . •
, • ..
•
•
••,
.... - memories and the cum:nt MREQ slgnal.
should be used to do a refresh read to all

" -
-- -• . -
- - ,,
, '.
~
~

~
HALT
dynamic memories.'

Output, active low. HALT indicates that

- - , ~
~
(Halt state) the CPU has executed a HALT software
.
-- .
~ {- • -
.•
.,
instruction and is awaiting either a non·
m:t.skable or a m~ble intelTUpt ("'ith

.~~ }-...
,
--
,
•
•
,,
the mask enabled) before operation can
resume. While halted, the CPU executes
NQP's to maintain memory refresh
, ,} • actiVity.
,
WAIT Input, active low, WAIT indicates to the
Z80, Z80A CPU PIN CONFIGURATION (Wait) Z-80 CPU that the addressed memory or
Tri-state output, active high; AO-AI 5 I/O devices afe not ready for a data
"a-All
(Address Bus) constitute a J6-bil addres's bus. The , transfer. The CPU continues to enter wait
address bw provides the address for states for as long IS this lignal is active.
memory (up to 64K bytes) data
exchanges and for I/O device data exchanges. INT Input, active low. The Interrupt Request
(Interrupt slanal is generated by I/O devices. A
Request) request will be honored at t.h~ end of the
Do-o, Tri-slate input/output, active high.
CUtrent insuuetion if th~ internal soft-
(Dau Bus) Do· OJ constitute an &-bit bidirectional ware conuolled int~rrupi enab~ flip-flop
data bus. The d:lla bus is used for d.llla
,
"I Output, active low. MI indicates thai the -Nlltl InpuL active low. The non·mOLSkable
(Machine current machine cycle is the OP code (NOR interruPT request line has a higher priority
Cycle one) fetch cycle of an instruction execution. Mas~able than IN and is always recogniu-1 at th~
Interrupt) end of the current instruction. indeprn·
')iREQ dent of the status of the interrupt enable
Tri-slale OUtput, active low. The memory
(Memory flip·flop. NMI automatically forces the
request signal indicates thai the address
Request) bw holds a valid address for a memory • UO CPU to restan to location 0066~ .
read or memory write operation.
RES!:;, Input, active low. RESET inidaliz.es the
CPU as foUows: reset interrupt enable
IORQ Tri-s.late output, active low. The IORQ flip-flop, clear PC and regisl~rs I and R
(lnputl signal indicates that tnc lower naif of tne and set interrupt to 8080A mode. During
Output addressbtis
, holds a valid I/O address for reset time, the address and data bus go to
Request) a I/O read or write operation. An IORQ a high impedance state and all control'
signal is also generaled when an interrupt output signals go to the inactive state.
is being acknowledged to indicale that an
. interrupt response vector can be placed .BUSRQ Input. active low. The bus' r~qutSt signal has
on the da ta bus. (Bus a higher priority than mIT and Is always rec·
Request) ognized .at the end of the"'surrent machine
-RD
(Memory
-
Trktate output, actiWi 10"'. RD indicates
that the. CPU wants to read data from
cycle and is used to request the CPU address
bus. data bus and tri·state OUtput conuol
Read) signals to go to a high impt'danc:e state 10
Dl(mory or an I/O device. The addressed that other devices can control these bimes.
I/O device or memory should usc this
signal to gate data OIIto the CPU data bw.
BUSAK Output, active low. BllS acknowledge is
(Bus wed to indicate to the requesting device
WR Tri-stale output, active lOW'. WR indicates Acknowledge) that the CPU address bus, data bus and
, (Memory that the CPU data bus holds valid data to tri-state control bus signals have been set
Write) be stored in the addressed memory or I/O to their high impedanC'll slate and the
device. external device can now conuolthese signals.
 Timing "a~'eforms
••...... . ' .INSTRUCTION Op'CODE FETCH
Th.: progrJm ~·nilllt.:r ~"'llll~'ll! (Pt·)·I'; p(~..:~d \In lh~ _____ ~~.~'-."<H_~_
. --i•
;tddr~s.~ bus imm..-di:ll e1v :11. the Slarl 01 Ih..- ... \'d~. On(' half
dock urn\' I:H~r ~)~.~ a..:ljv.... 1h~· falJi~y. ~d!:!\' nf '. I, " '. '.
MREQ c:ln be u~d dinxE\y as:l chip enable to dynamic
memoncs. RD when a..:th·... -.indkates ,flat the memory • ....,... ..,.,. I
d:lm should be en3bled omo the CPU data bus. Th.: CPU' II 1..1"'\ J ~:
S3lTIples d313 Wilh th~ rising edge of lhe cloc~ S13le T~ ..
Clock staIn T3 and T.t of a fetch cycle are used to refresh " . \:;,
1...
L l.
_______ J
--------,............----- -- - - T · - - - - ':...-
-
d~'nami": memones \vh~the CPt) is int-ernally decoding •••
..., " !L
....,
• -!._
;lnd exe.:lIling the inSirUCllun. nle refresh cunlrol signal
RFSH indic3Ies th:u:I refresh read of 311 dynamic memories
,.
•
should be 3.::eomphshtd. . \ 'I
,
,
MEMORY READ OR'WRITE CYCLES /
, _--,._..._ •.• "'_" _~ c,..~ _
Illuslraled h<'f<' i~ th... liming flfmemory rcad O! wrile ... ~_·_· ..._ ..... c.... ·
I
~·y,I!!.2lher lh:lll an OP ~'od~ f(,lch (1\I, cycle). II.le- ~l REQ !. "
j t.
" " "
and RD si~l1als ar~ us~d ...",aclly as in ,tilt' fetch cyde. In
lhe case or a' nl<'llIory write cyck. the 10.1 REQ alsfl bt"ollltS •
.. ''', .! M'''','' ."""
ll"ive- whc,~ the :addrt'ss bus is 'slab~e io thtl! it can be u~d
M ...... ' . " " .

....a \ I I
directly as a ..:hip enablt' for dynamic ffit'ffiorks. The WR
.line is active when dala on ,h... dala bus is stable so lhal it
call be use~ dHectly :1.$ a RiW pulse to virtually any type of .. p I

semiconduClor memory. -.. ., -r-----'

,
...)
.-+-----~--
I..._ ---------~-----~--
J
.S
\

1....-----;--
I

•
- .
\ INPUT OR OUTPlfT CYCLES
•
; lIlustraled here is Ihe liming for an I/O re-ad or 110 write
')pC'f3linn. Notio;e- lhat during I/O operalions a single wait
.' •
'. ., ',' '. I '.

Siale is aUlOm:IliC'Jlly in~r1ed (Tw·). The reasoll for this is _ L I

th:;! during I/O operations this exlta state allows surticienl .\ I

--.
~.
time for an I/O pon 10 decode its address and 3cti\'a Ie- the I
WAif line if a wail is required.. .
, i - .
..... -----~-----rL---------

-:-------1' -~--~T---} •.

• .
••
"y, .'J--
I
-
" INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
.,
>

•
The inlCErUpl signal is sampled by the CPU Wilh the
;'ising edge of the- last clock al lhe end of Iny instruction.
- .. _-
' ..'M< +-'- •. _
;oVhen an interrupt is accepted. :) special MI cycle is
: ~e-ne-ntt'd. During Ihis ~i I cycle-. th... IORQ signal becomes
•
active Iinstead oi MREQ) 10 indicale that the interrupting
device can place an 8-bil vector on lhc data bus. Two wail ......
•~tatt's (T.....·) are automatically added to this cycle so that a
:ippk priority jnrerrupt sehe-m.... such u the one- used in the
•
:l80 peripheral controllers. c::m be easily implemented.
,,
•

,.
 I Mnemonic Symbolic Oper.uion Commellts Mnemonic Symbolic Operalion Comments
tD r. s • .
,-,
~
•

s':f.n.(Ht). LDI 10EI .... (HL). DE - oE"-1

--- - . -
\ {IX+el.(IY-te) · • HL -HL+i. Be - 8C-1
· tD d. I d-, d=(Hll.r LDIR (DE) - (Hll, DE - oE"-1
• (IX+el.(JY+tJ • • HL-Hl+I.BC-8C-1
•
•
lD d. n d-n d::f.Hll. -
-
~
." 1'1 Repe:u until BC " a I
,• to
•
•• •

A, 5 A ~, •
(IX+el. (IV+e)"
5 E IBC).(OE),
(nnl, L R ,
.=
-
~
o
:;·
~
LDD

LobR
(DE) --IHl). DE - DE-l
liL - HL-I, Be - 8(-1
(QE) -(HL), DE "DE-I
•

,
·
to d. A d-A d:: (BCI. (DEI. HL ..... HL-I.HC-BC-l •
(nn), I. R Repeal unlil Be '" 0

to dd. nl1 dd -nn dd :: IK. DE, (PI A-OILI, HL .... HL+I ,,

HL.SP.IX,/Y BC.-BC-l I
tD dd, (lin) dd ~(ini dd:: BC. DE.- (PIR A-Oil). HL - HL+I A-fHl) s;ts
HL. SP, IX.IY . BC .... OC-I. Repeal the flags only .
• to (nn), ~ (nn)-ss ss::~C.DE, - · uillil BC '" ,0 or A = (Ill) A is not affected j

- LDSP,55 HL;SP.IX.IY CPO A-(H:"l. Hl .... HL-l

.
•
•
I
SP "'ss . ss z HL.·'X. IV OC-8(-1
PUSH 55 (51'-1) - ssH; (SP-2) -'SSt ss '" Be. DE, f; ~ _
•
. (POR A..(HL). Hl - HL-I
HL. AF. IX. IV BC-OC-I,Rcpeat • .
POPdd ddL .... (SP); dd H -(SP+l) dd.: Be. DE. ·
. unlil Bf= 0 or A s (HI;)
. HL. ."F, IX, IV
ADDs A -A +s •
•"
•
- •
E.'<. DE. HL DE - Ht ADC, A ... A+s+CY :i
CY is the
.
EX AF.AF' AF •• AF' SUBs
•
A -A-5 •
.~
.carry _n_~!~ ._ I
•
· [XX • ,
•
.
. -~~ ",'.

(~i)--(~)
sue , A-A-s-CY
. s=:r,n,{HLJ
· ·
•
, •
~

lit HL'
• ANDs
OR,
A-A"s
A-A Vs
{IX+e).IIY't-e)
~.

.....
':-'~
,.--.
.. '""--.'.
--,{'.
..•
",-.

EX (SPI, 55 (51').- SSt' (SP+l) - SSH ss a 1iL. IX. IV •

...-;.-... ..
'-'=";.. "
XOR S A-AQIs
-_. •• .~
.
.;rr~
",:~--

,
~
 Mnemonic Sym~olic Openu,ion Comments Mnemonk: Symbolic O~ralion ,Comment,
• ,

, CP, A-, " S'" r, n (HL) BIT b. s Z-'b Z is zero flag

... - . (IX+e),{IY+e)
,
SET b, S 'b - s=r.(HL)
lNCd , \i-d+l
, I ,
I
,
, , :. \. ,•
d-r,(HL)
. (IX +e). (fY+e)
RES b, s 'b -0 ~
(IX'k:).(fY+e)
, DEC d a-a - V'
•
, i , IN A, (n) A .... (n)
i r .... (C) - Set flags

,
ADD HL, is
. AOC HL, ss.
HL-HL+-u-:
HL -HL+u+tY
. >. .'
,
.. '
,

-
IN " (C)
INI
,

-
, (HL) -(C),Hl -Ill"
B +- B-"; I ,- , -- - , , '
,
~
.
._-_.' ,

-~, lNIR (IiL) .... (C).Hl .... HL + I

soc HL, 55 Hl-Hl-ss-CY
8 .... B-1 -
ADOIX.ss IX-IX+ss SS E. Be, DE, , Repeat until B • 0
IX,.sP .
IND (HL) -(C).Hl_ HL _ I
-ADDIY,ss IY"':'IY+ss =
ss BC, DE,
~ B-B-1
fY, SP
• "5
~
INOR (Hl) -(C). HL - HL - I
INC dd dd .... dd+ 1 dd E. Be, DE.
B-B-l , '

DEC dd dd-dd-I
HL,.SP, IX, IY
aa"Be,DE,
"
Q
Z
Repeal until 8 ... 0
< OUT(n), A (n) .- A
HL.SP. IX. IY
5 OUT(C), , (C)- r ,

DAA \
Converts A contents into Operands must
packed BCD foll~ing add', be in packed
- OUTI
z (C)- (HL),HL - HL + I
B.... B-1
or subtract. BCD format ,
OTIR (C).... (BL). HL" HL + I
,
8-8-1
: CPt A-A Repeat.until B:O
,
: NEG A-OO-.A
_. , . aUTO (C)~ (HL), HL - HL - 1
, CCF CY -Cy· B+-B-l ,

: Sl:'F ... (Y - I "

.. __ .__ . - OTDR
,

(C)-(HL): HL -Hl ... I ,

-
;-NOP \ No oper:ltion . , B - B-1
Repeal unlil B : 0 ,
. HALT Halt CPU
01 Dinble Interrupts ( .... JP nn I'C-~ NZ 'PO
•
EI Enable lnterrut'u JP cc, nn
, If condition cc is lrue , - Z PE
1M 0 Set inlerrupt mode 0 8080A mode
JR.
PC - nn. else continue ,
·PC+-PC+e
,-
"' NC P
C~, M
v', .
1M I ,
Set interrupt mode I C.Uto 003811.
JR kk, e
1M Z Set interrupt mooe 2 _ Indirect Call , - ,
If condition kk is true
PC .... PC"+ e. else conlinut
kk{NZNC'
Z . Co.
,

JP (u)" I'C ~M ss - HL, IX;IY'

DJNZe O.... B-J.ifB:O ,

RL, continue. else pc .. PC + e

CALL lin (SP-I)-PC H
NZ PO
RRCs (SP-2) .... , Pel' PC +- nn
~ CALL cc,nn If condition cc Is false
Z PE ,
'RRs
~
~ continue, e!Se same as " NC
C ,
P
M
- ,

.
,
' CAll mi
"
SLAs &-l1_.~.
, s=r.(HL) _
<\X'k:),(IY+e) ~
RST L (SP-I)~I'CH
(SI'-Z) -l'Cl.,I'C H - 0 - ,

SRAs r--V_l~
, Pel .... L ,

•
--
<~- •

L.:J , RET PeL ..- (SP).

SRLs ."'J_.~
, RET cc
I'C H - (SP+ I) ,

If condition cc is false. NZ PO
-
W~I~1
~
z continue. else same as RET Z FE
RLD ~

"
~
~
RETI Return from interrupt, " Nt' P
(' M
~ same as RET
RRD 9¢ ~U1U RETN , Return from non-
nuskable interrupt
A.C. Characteristics ,Z80-CPU
.3e' .
TA'" oOe LO 70°(. Vee· +5V:l: S%. Unless Otherwise Noted. • •

No .,,;,
•

... "
.'
"lo.l.m" 'r 15
", '.a" L.,...e:t

>',-.-1
'OlD!
'" ""'.U
'... ·1wl~1

'" ,_.... .
If IDI

,-...
. . . . ..0
'Wo(D) 'at"
'sitD} ,lI \
1)o‫ס‬i. SuWlI'l.- ... q
DItta S<aWt f _ '1/1
1110 ('y;to I
,., I... • . .~I 't,.-11O
''''
'. •• -- .',_50
'" . . .. . . -..
'(M" 'wtt.l

i ---
, , ,
'MUUl .
'OH<t(lltll
'~flil") Ct " 50pf , , ,

=::;: - III ..... 'NRl)· •• ·'OO

'Ol.OIlI . ---, ~l 'wjWlH) .. '-!oMfl· If·)O

,
,
-
'OC.CIIt) Ct .. ~"
'OtMoOIl)
'~~R!
• • . . ..
'Dl./lU:l1
:tIL"
'Dfi.
.II.D j
(RP)

..
'DHi"{RDJ
. --
-- CL" SOpf

III 'Dl/NI,
'llH (Nil
1ii 0.10)1 F...... 1I,Id,. Ed. 0( ('lock. NI Lo.'
Iii Dolly F_ ~ Ell.. oto.. t, ilIl¥ -
- cL • XlpF
POI '-fIl'R)···~· ~

'DlIRF) iiffi 0.1or F_ I'loIo>t U. <II Clod. mil Low ,..

-- Ct· .IOpf

" - •

.. ""
..,
Ct· SOpF
,

"/101 . -.- ,
'DLtBl\)
'DH(1A1

"fIl5)
I~O

", -- C .. SOpF
t '.
,
'flC)
". ..,
'- 1111
- ,
1111 ''''1.'' :!Ic" ......n.. 'I" 10

,
. ,,_. -..... ,...
,",A •

_....
--~

'1 -}~

", .-
1 .....
-.'
A.CTiming Diagram
,
·1
Timing measurements ar-e m<l.de :n the following
vohages, ur1eJS oth~rwlse spe'ciJicd: ..... •

..
-I"
•
ClOCK 'V« ~6V .~5"
oumrr \'
• ,. "
~.o

•
• -
~ ....;~W'
•
.
,
••
'''"'
FLOAT
.
., .
JV
10"' V

.
• '- - .
, ~H.. .,--.
.", l+lJ
Ao-A15

~'_J'=*H'alllilll
"

"",
w.
,~"". ~.!-
,,I
! '• - I, I
I
I
, 11'"
I .

•
I
'liIWT) 'II

.. 1'0 (HI, '0 Iliff

~ ..
~~~;~~.!:~~ , 1'11.. ~
"00;<15."'0 >(----}<'.'.~_-_I
'Oll14'

'IIRS ~
....... /

RESET
..----·IX~--
--~-, ,--------
 Absolute Maximum Ratings
...".
T=perl''''t Undo. Il~> ~...~r...,J .,!"""M,,, r ...~.
St"..f·l ..... ~ral .... ~~\ h" ISO·t"
Vol",,_ 0.. A.. y Pt• 003V " •• ,\"
.."" II """"'" h. L ''''''''''
Pow., U....I'''iun

. <• .
S"_,,. PlI._n . ~ ... T~,. Mn.
""', Tn.I CoHiIfiuol
.
Sy.. lIool h . -... ·
"". ,... •

, "IU'
('~ ...-.. brU! l~",' '" ,~,,.,,.. • ~.' , ." ,
.
C., '·l.,.,k 1"''''''''0'''' .:~ p'

"" 11K I l'I ....·~ Inp'" Il,~h \·"h.~,·, . \'.,' ~.:

'" '"
,""
,.
('r', 1i1'I;U'I"'r...''''''',-' ,< • pl'

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