1 MOSFET's

EEET 2404 Electronic Circuits
Lecture 1
Introduction to Microelectronics &

MOSFET’s
Assoc. Prof. James Scott
James.Scott@rmit.edu.au
EEET2404: Electronic Circuits Page 1–1

Lecture Outline
•  Course introduction
•  Review of semiconductor materials
•  MOSFET’s
–  Structure
–  Fabrication
–  I/V characteristics
–  Biasing
–  Small signal model

Course Materials
The material for EEET 2404 is presented in 8 modules:
1- Semiconductors (MOSFET’s, diodes and BJT’s)

2- Current sources, current mirrors and cascades
3- Amplifier configurations
4- Differential amplifiers
5- Power amplifiers
6- Linear regulators
7- High frequency transistor models
8- High frequency circuits and novel devices
5 modules contain laboratory exercises
1- MOSFET’s
2- Current sources and mirrors
3- Differential amplifiers
4- Power amplifiers
5- Linear regulators

Teaching Schedule
Lecture Tutorial Lab

Introduc1on to Microelectronics and
MOSFETs No tutorial No Lab
Diodes and BJT's MOSFET biasing and circuits Expt.1 -‐ MOSFETs
Current sources, mirrors and cascades Diode and BJT biasing and circuits Expt.1 -‐ MOSFETs
Amplifier configura1ons Current sources, mirrors and cascades Expt.2 -‐ Current sources and mirrors
Differen1al amplifiers (I) Amplifier configura1ons Expt.2 -‐ Current sources and mirrors
Differen1al amplifiers (II) Nonlinear differen1al amplifier opera1on Expt.3 -‐ Differen1al amplifiers
Power amplifier classes and single-‐ended Linear differen1al amplifier opera1on,
class A offsets and imbalance Expt.3 -‐ Differen1al amplifiers
Class AB and B power amplifiers Class A power amplifiers Expt.4 -‐ Power amplifiers
Linear regulators Class AB and B power amplifiers Expt.4 -‐ Power amplifiers
High frequency transistor models Linear regulators Expt.5 -‐ Linear regulators
High frequency circuits and novel devices High frequency transistor models Expt.5 -‐ Linear regulators
Review High frequency circuits No Lab

Course Resources
Prescribed textbook:
Microelectronic Circuits, Sixth edition, Authors: Sedra/Smith,

Oxford University Press, 2011.
Student resources:
http://www.oup.com/us/companion.websites/0195142519/
studentresources/?view=usa
CD-ROM Appendix B: P-Spice device models and simulation examples
Simulation software:
PSpice v 9.1 (available for download under learning resources)

Assessment Tasks and Value
Written final exam - 2 hours, open book
– Value : 50%
5 Labs – Total Value : 30% (5 x 6%)

Assignments – Value : 20% (10% + 10%)
The overall aggregate must be 50% or greater to pass

the course.

Semiconductor Materials
•  Reading:
–  Sedra/Smith, sections 1.7 to 1.12
•  Problems:
–  Sedra/Smith, 1.64, 1.66, 1.69,1.72, 1.76, 1.78

Defining the Metric Units of Resistivity
R =ρ l/A (resistance Ω)
ρ = resistivity (Ω-cm)
l = length (cm)
A = area (cm2)
ρ =RA/l

Typical Resistivities
•  Insulators > ~ 106 (Ω-cm)
•  Semiconductors (intrinsic) ~ 100 (Ω-cm)
•  Conductors < ~ 10-6 (Ω-cm)

Energy Levels: conduction and valence bands
of an insulator; semiconductor; and conductor.

Ge and Si single-crystal
structure.
covalent bond
Atomic structure:
(a) germanium; (b) silicon.

Antimony Impurity in n-type material (Si).
Boron Impurity in p-type material (Si).

Effect of Donor Impurities on the Energy Band Structure
Reduced energy gap

increases the number of
electrons in the conduction
band

Field Effect Transistors
•  Reading:
–  Sedra/Smith, sections 5.1, 5.2 and 5.3
•  Prior Knowledge:
–  DC, AC power calculations
–  BJT characteristics, common-emitter and
common collector configurations
•  Problems:
–  5.2, 5.11, 5.13, 5.15

Field Effect Transistor (FET)
•  A very important type of transistor
developed after the bipolar junction
transistor (BJT) is the field-effect transistor
(FET).
•  It draws almost no power from an input
signal, overcoming a major disadvantage of
the junction transistors.
–  Excellent for low power electronics

Metal-Oxide Semiconductor Field-Effect
Transistor (MOSFET)
•  In MOSFETs the gate (just one) is separated from the channel by a
layer of metal oxide (insulator and dielectric).
•  The electric field of the gate controls the resistance of the channel. The
input voltage at the gate can alter the current through the channel.

MOSFET Technology
•  Initially only analogue ICs and digital TTL
circuits based on bipolar transistors were used in
IC circuits.
•  The rise of the MOSFET technology, during the

last two decades, has almost completely
eliminated the bipolar transistors’ market. Now
almost all of the analogue ICs, logic circuits, and
memory chips contain exclusively MOSFETs.

The MOSFET
Fabrication
Process

MOSFET Advantages
Compared to BJTs, MOSFETs:
–  Require much less space on the silicon IC chip
–  Manufacturing process is cheaper
–  They consume less power
–  They exclusively use transistors and no
resistors in their circuits due to smart
engineering designs

Desirable Features
•  In a single VLSI (very large scale
integrated) circuit chip up to 2 billion (2010
technology) MOSFETs can be fit!
•  Both analogue and digital circuits can be
designed and implemented on the same chip
(mixed signal design)

Physical structure of the enhancement-type NMOS transistor: perspective view:
Typically L = 0.03 to 1 µm, W = 0.1 to 100 µm, and the thickness of the oxide layer
(tox) is in the range of 1 to 10 nm (2010 technology).

Picture of an
N-channel MOSFET
or NMOS
Defines the
There are four terminals: technology, e.g.
Gate (G)
45nm CMOS
Source (S)
Oxide relative
Drain (D)
permittivity is εox
Body (B).

Enhancement MOSFET Symbol
(a)  Circuit symbol for the n-channel enhancement-type MOSFET.

(b)  Modified circuit symbol with an arrowhead on the source terminal to distinguish it from
the drain and to indicate device polarity (i.e., n channel).
(c)  Simplified circuit symbol to be used when the source is connected to the body or when
the effect of the body on device operation is unimportant.

vGS must exceed a threshold
voltage Vt to form the induced
n-type conducting channel
The enhancement-type NMOS transistor with a positive voltage applied to

the gate. An n channel is induced at the top of the substrate beneath the
gate. Note: vDS = 0 so the channel depth is uniform.

Small vDS
An NMOS
transistor with
vGS > Vt and
with a small vDS
applied.
(for example
50mV)
The device acts as a resistance whose value is determined by vGS.

The channel conductance is proportional to vGS – Vt’ and thus iD is
proportional to (vGS – Vt) vDS.
vOV = (vGS – Vt) is called the excess gate voltage, or “overdrive voltage”
( "W % +
iD = *(µn Cox )$ 'vOV -v DS
) #L& ,
( "W % +
= *(µn Cox )$ '(vGS − Vt )-v DS
) #L& ,
"W %
gDS = (µn Cox )$ 'vOV
#L&
"W %
= (µn Cox )$ '(vGS − Vt )
#L&
The iD–vDS characteristics of the MOSFET when the voltage applied

between drain and source, vDS, is kept small. The device operates as a
linear resistor whose value is controlled by vGS.
iD is proportional to (vGS – Vt)

µnCox is a constant which is determined by the
technology. It is called the “process
transconductance constant”, its unit is A/V2 and it is
denoted by:
k'n=µnCox
where
Cox = εox/tox
Definitions
Increasing vGS above the threshold voltage,
Vt , enhances the channel, hence the name
enhancement-mode operation or
enhancement type MOSFET.

Large vDS
Operation of the enhancement NMOS transistor as vDS is increased.

The induced channel acquires a tapered shape, and its resistance
increases as vDS is increased. Here, vGS is kept constant at a value > Vt.
vDS appears as a voltage drop across the length of the channel. As we travel along the channel
from source to drain the voltage increases from 0 to vDS. Thus the voltage between the gate
and points along the channel decreases from vGS at the source end to vGS-vDS at the drain end.

Increasing vDS causes the channel to acquire a tapered shape.
Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the
drain end. Increasing vDS above vGS – Vt has little effect
(theoretically, no effect) on the channel’s shape (additional voltage
appears as a voltage drop across the depletion region at the drain
end of the channel).

The drain current iD versus the drain-to-source voltage vDS for an
enhancement-type NMOS transistor operated with vGS > Vt.

# W &* 1 2-
iD = k n" % (,(vGS − Vt )v DS − v DS / for Triode Mode
$ L '+ 2 .
1 #W & 2
iD = kn" % ((vGS − Vt ) for Saturation Mode
2 $L'
Summary: The iD-vDS characteristics
1) Cut-off region
Device is in the cut-off region when vGS < Vt
2) Triode region
Device is in the triode region when vGS >Vt and vDS is small
(it means vDS < vGS-Vt or vD < vG -Vt)
' W $/ 1 2,
iD = k n( % " -(vGS − Vt )vDS − vDS * for Triode Mode
& L #. 2 +
'W $
iD ≈ k n( % "[(vGS − Vt )vDS ] for Triode Mode (if v DS is small)
&L#
3) Saturation region
Device is in the saturation region when vGS >Vt and vDS is not small
(it means vDS >vGS-Vt or vD >vG -Vt)
1 #W & 2
iD = k n" % ((vGS − Vt ) for Saturation Mode
2 $L'
I/V Summary
Cut off region:

Condition: vGS ≤ Vt
iD = 0
Triode region:
Conditions: 1: vGS ≥ Vt
2: vDS ≤ vGS- Vt
iD = µnCox(W/L) [(vGS - Vt)vDS - (1/2)vDS2]
I/V Summary (2)
Saturation region:
Conditions: 1: vGS ≥ Vt
2: vDS ≥ vGS - Vt
iD = (1/2) µnCox(W/L) (vGS - Vt)2

Finite Output Resistance
•  Increasing vDS beyond vDSsat causes a slight
reduction in channel length.
1 ' "W % 2
iD = k n $ '(vGS − Vt ) (1+ λv DS )
2 #L&
Finite Output Resistance (2)
•  So, the output resistance is:
-1
$ ∂iD '
ro ≡ & )
%∂v DS (v GS constant
−1
$ k n' + W . 2'
ro = &λ - 0(vGS − Vt ) )
% 2,L/ (
€
Finite Output Resistance (3)

Input characteristic
The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation

(Vt = 1 V, k’n W/L = 1.0 mA/V2).

Output characteristic
(a) An n-channel enhancement-type MOSFET with vGS and vDS

applied and with the normal directions of current flow indicated. (b)
The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2.

CMOS
•  CMOS stands for Complimentary MOS
–  Employs both PMOS and NMOS devices
Figure 5.10 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n
well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the
connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

MOSFET Biasing and Circuits
•  Reading:
–  Sedra/Smith, sections 5.7, 5.5, 7.1 and 7.2
•  Prior Knowledge:
–  DC, AC power calculations
–  BJT characteristics, common-emitter and
common collector configurations
•  Problems:
–  5.68, 5.70, 5.48, 5.49, 7.5, 7.13

MOSFET Biasing
•  An essential step in the design of a
MOSFET amplifier is the establishment of
an appropriate dc operating point for the
transistor.
•  Biasing sets the DC current ID and dc drain-
to-source voltage VDS
–  Biasing schemes need to address the variability
in Vt from device to device

Biasing by fixing VGS
•  The most straightforward approach is to fix the
gate to source voltage
–  either derived from VDD, using a voltage divider, or
–  use of a separate voltage source
•  Disadvantage: This is not the best approach for
obtaining a transistor parameter independent
circuit
•  We know for saturation:
–  ID=(1/2)µnCox(W/L)(VGS-Vt)2
–  Vt and µnCox vary widely among devices with the same
fabrication process. It is even large on integrated
circuits. They also depend on temperature.
The use of fixed bias (constant VGS) can result in a large
variability in the value of ID. Devices 1 and 2 represent
extremes among units of the same type.
Biasing by Fixing VG and Connecting a
Resistance to the Source
Reduces
variation in ID
Biasing for discrete MOSFET circuits: fixing the dc

voltage at the gate, and connecting a resistance at
the source

Possible Discrete Implementations

First method:
The gate voltage (set by the voltage
divider RG1-RG2):
VG = VGS + RSID
If VG is much greater than VGS then ID is

mainly determined by this voltage.
Still, if VG is not much greater than VGS

resistor RS provides negative feedback,
which stabilizes ID.
It should be checked whether the

MOSFET is in the triode or saturation
mode.
Page 1–51
EEET2404: Electronic Circuits
Example

Biasing using a Drain to Gate
feedback resistor
Simple and effective discrete biasing
arrangement.
A feedback resistor is connected
between the drain and gate. Transistor
is always in the Saturation mode as VDS
> VGS - Vt.
RG is large and it does not draw any
current. As a result VG = VD. It can be
written:
VGS = VDS = VDD - RDID
Re-arranging:
VDD = VGS + RDID
How does the feedback work: if ID

increases, VGS decreases as VDD is
constant.
As ID = (1/2)µnCox(W/L)(VGS - Vt)2 , ID
decreases.
This stabilizes the bias.
Page 1–57
Biasing using a constant current
source
In integrated circuits – a current

source can be established using
other transistors
ID is known:
ID = (1/2)µnCox(W/L)(VGS - Vt)2
VGS adjusts to give the correct ID

Biasing using a constant current
source
•  The most effective scheme for
biasing a MOSFET in integrated
circuits
•  RG establishes a dc ground in this
example. Generally it represents
the loading by the previous
amplifier stage
•  RD provides the output DC swing
when current passes through
Page 7–59
Small Signal Operation
•  From a small signal point of view the
MOSFET behaves in a similar manner to a
voltage controlled current source.
–  It accepts vgs between gate and source and

provides a current gmvgs at the drain terminal.
–  Ideally, the input resistance is very high

(generally assumed to be an open circuit).

Small signal equivalent circuit
Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS
in saturation (the channel-length modulation effect); and (b) including the effect of
channel-length modulation, modeled by output resistance ro = |VA| / ID.

Small signal equivalent circuit
•  After the calculation of the DC bias, the DC
voltage sources will be shorted and current
sources will become open circuit and then
the MOSFET will be replaced by its
equivalent small signal circuit model.
•  ro is typically in the range of 10kΩ to
1000kΩ
•  Both gm and ro depend on the dc bias point
of the MOSFET
Transconductance (gm)
Transistor is in saturation region – Bias voltage is VGS
If we apply a small vgs , the total gate to source voltage vGS
will be: vGS=VGS+vgs (we define kn’=µnCox ) then:
iD=(1/2)kn’(W/L)(VGS+vgs- Vt)2
=(1/2) kn’(VGS-Vt)2 + kn’(W/L)(VGS-Vt)vgs +(1/2) kn’(W/L)vgs2
1 2 3
The first term is the DC bias current
The second term is directly proportional
to the input small signal voltage
vgs VGS
The third term is the non linear
distortion (it is generally small and
can be neglected)
iD≈(1/2) kn’(W/L)(VGS-Vt)2 +kn’(W/L)(VGS-Vt)vgs
iD=ID + id, where ID is the DC bias current and id is the AC

component (small signal) of the total current iD. As a result:
id =kn’(W/L)(VGS-Vt)vgs

•  The parameter that relates id and vgs is the
MOSFET transconductance gm:
gm=id/vgs= kn’(W/L)(VGS-Vt)
= µnCox(W/L)(VGS-Vt)
•  Note:
–  It is set by the DC bias conditions (VGS)
–  It also depends on the transistor parameters
•  Vt and µnCox(W/L)

For a
given VDS
Small-signal operation of the enhancement MOSFET amplifier.

The Voltage Gain
vd
Av =
v gs
€ v D = VD + v d

Voltage gain
The total drain voltage vD can be
expressed as follows:
vD=VDD-RDiD= VDD-RD (ID+id) which
can be rewritten as (with the bias
voltage VD=VDD-RD ID):
vD=VD-RDid
Thus the small signal component of
the drain voltage is:
vd= -idRD= -gmvgsRD =>
Av= vd/vgs= -gmRD
Example

Page 1–70
Page 7–71
Summary
•  Review of semiconductor theory
–  Holes and electrons, doping (donors and acceptors)
•  MOSFET’s
–  Structure of MOSFET’s
–  Channel enhancement
–  I/V characteristics
•  Cut-off, triode and saturation regions of operation
•  MOSFET biasing
–  Must confirm the mode of operation
•  MOSFET small signal model
–  Transconductance
–  Amplifier configurations compared

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EEET 2404 Electronic Circuits

Introduction to Microelectronics &

EEET2404: Electronic Circuits Page 1–1

EEET2404: Electronic Circuits Page 1–2

1- Semiconductors (MOSFET’s, diodes and BJT’s)

5 modules contain laboratory exercises

EEET2404: Electronic Circuits Page 1–3

Lecture Tutorial Lab

EEET2404: Electronic Circuits Page 1–4

Microelectronic Circuits, Sixth edition, Authors: Sedra/Smith,

CD-ROM Appendix B: P-Spice device models and simulation examples

PSpice v 9.1 (available for download under learning resources)

EEET2404: Electronic Circuits Page 1–5

5 Labs – Total Value : 30% (5 x 6%)

The overall aggregate must be 50% or greater to pass

EEET2404: Electronic Circuits Page 1–6

EEET2404: Electronic Circuits Page 1–7

EEET2404: Electronic Circuits Page 1–8

• Semiconductors (intrinsic) ~ 100 (Ω-cm)

• Conductors < ~ 10-6 (Ω-cm)

EEET2404: Electronic Circuits Page 1–9

EEET2404: Electronic Circuits Page 1–10

EEET2404: Electronic Circuits Page 1–11

EEET2404: Electronic Circuits Page 1–12

Reduced energy gap

EEET2404: Electronic Circuits Page 1–13

EEET2404: Electronic Circuits Page 1–14

EEET2404: Electronic Circuits Page 1–15

EEET2404: Electronic Circuits Page 1–16

• The rise of the MOSFET technology, during the

EEET2404: Electronic Circuits Page 1–17

EEET2404: Electronic Circuits Page 1–18

EEET2404: Electronic Circuits Page 1–19

EEET2404: Electronic Circuits Page 1–20

EEET2404: Electronic Circuits Page 1–21

EEET2404: Electronic Circuits Page 1–22

(a) Circuit symbol for the n-channel enhancement-type MOSFET.

EEET2404: Electronic Circuits Page 1–23

The enhancement-type NMOS transistor with a positive voltage applied to

EEET2404: Electronic Circuits Page 1–24

The device acts as a resistance whose value is determined by vGS.

The iD–vDS characteristics of the MOSFET when the voltage applied

EEET2404: Electronic Circuits Page 1–26

EEET2404: Electronic Circuits Page 1–28

Operation of the enhancement NMOS transistor as vDS is increased.

EEET2404: Electronic Circuits Page 1–29

EEET2404: Electronic Circuits Page 1–30

EEET2404: Electronic Circuits Page 1–31

Cut off region:

iD = (1/2) µnCox(W/L) (vGS - Vt)2

EEET2404: Electronic Circuits Page 1–38

EEET2404: Electronic Circuits Page 1–41

The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation

EEET2404: Electronic Circuits Page 1–42

(a) An n-channel enhancement-type MOSFET with vGS and vDS

EEET2404: Electronic Circuits Page 1–43

EEET2404: Electronic Circuits Page 1–44

EEET2404: Electronic Circuits Page 1–45

EEET2404: Electronic Circuits Page 1–46

Biasing for discrete MOSFET circuits: fixing the dc

EEET2404: Electronic Circuits Page 1–49

EEET2404: Electronic Circuits Page 1–50

If VG is much greater than VGS then ID is

Still, if VG is not much greater than VGS

1 MOSFET's

1 MOSFET's

•  Semiconductors (intrinsic) ~ 100 (Ω-cm)

•  Conductors < ~ 10-6 (Ω-cm)

•  The rise of the MOSFET technology, during the

(a)  Circuit symbol for the n-channel enhancement-type MOSFET.

–  It accepts vgs between gate and source and

–  Ideally, the input resistance is very high