Tutorial 2-

Submitted by : Md Shahazad Uddin

Roll no :CSE-35/15
Subject : Microcontroller and Microprocessor
Date : 11th September, 2017

1. What is meant by minimum mode operation of the 8086?

Ans: In minimum mode operation of 8086, all the control signals for the
memory and I/O are generated by the 8086.

2. What is mean by maximum mode operation of the 8086?

Ans: In maximum mode , some control signals must be externally generated

.This requires the addition of an external bus controller such as the 8288 to
the 8086.

3. How are the control signals MEMR and MEMW generated using M/IO,
RD and WR signals in the minimum mode of the 8086?

Ans: In minimum mode of 8086, the

a. M/IO: pin indicates whether the 8086 is performing memory
read/write operation (M/IO= 1) or I/O read/write operation(M/IO=0)
b. WR : The write signal indicates the 8086 is sending data to a memory
or I/O device . When WR is at logic 0, the data bus contains valid data
for the memory or I/O.

4. How are control signals IOR and IOW generated in 8086?

Ans: INTA pin used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device. IORC, IOWC are I/O read command and
I/O write command signals respectively . These signals enable an IO interface
to read or write the data from or to the address port.
 5. What is meant by memory read and memory write cycle?

Ans: Memory read cycle is the sum of the access time and read recovery
time is the memory read cycle time. This is the time needed between the
start of a read operation and the start of the next memory cycle.
Memory write defines the writing of data into memory.

6. Explain the minimum mode configuration of the 8086 base system with
the necessay block diagram?

Ans. BASIC 8086 Minimum mode System

8282 I/O ports are used to latch the addresses from the 8086 Microprocessor
Data/Address bus. By using three 8282, A0-A15, BHE , A16-A19 lines are
latched during T1state. OE (Output Enable) input of the 8288 I/O ports are
grounded; the bus will therefore,never be floated. ALE signal from 8286 is used
to strobe the addresses into the 8282 I/O latches.

Since the Data Bus is bi-directional, 8286 bi-directional bus transceivers are
used, inorder to create a separate Data Bus from the 8086 Address/data Bus.
The DT/ R andDEN outputs from 8086 are used for 8286 "T" signal and OE
inputs respectively.
 7. Describe the maximum mode configuration of the 8086 with the
necessary block diagram?

Ans : Maximum Mode Configuration

When MN/MX pin is strapped to GND, the 8086 treats pin 24 through 31 to be
in maximum mode. An 8288 bus controller interprets status information coded
into S0, S1 and S2 to generate bus timing and control signals compatible. DEN,
DT/R and ALE control outputs, are now generated by the 8288 bus controller.
The DEN from 8288 is inverted and given to 8286transceiver to enable the
output. The output enable of 8282 latch is grounded.

As in minimum mode the address-data lines are latched through 8282 latch. The
ALE signal from the 8288 bus controller latches the address during the T1 state
of the microprocessor. The DEN signal is used to enable the transceiver either
to transmit or receive data from I/O devices and memory. The DT/ R signal is
used to transmit or receive the data as the need may be.
10.Explain the bus timing for bus request and bus grant in minimum and
maximum mode?

Ans: Bus Read Machine Cycle

Fig- 12 shows the timing diagram of 8086 read machine cycle with WAIT state.
The
clock (CLK) signal is obtained from the clock-generator 8284. Each cycle of the
clock is referredto as a state. Minimum number of states to access a data is four.
They are T1, T2, T3, and T4states.

During T1 state of a read machine cycle an 8086 first asserts the M/ IO signal. It
will
assert this signal high if it is going to read from memory during memory read
cycle and it will
assert M/ IO low if it is going to do a read from an Input port during its read
cycle. The timingdiagram in fig shows two lines for the M/ IO signal, because
the signal may be going LOW or going HIGH for a read cycle. The point where
the two lines cross indicate the time at which the signal becomes valid for this
machine cycle.

After asserting M/ IO , the 8086 sends out a high on the address latch enable
signal, ALE.
The microprocessor sends out on AD0-AD15, A16 through A19 and BHE lines,
the address of 4the memory location that it wants to read. Since the latches are
enabled by ALE being high, this address information passes through the latches
to their outputs. The 8086 then makes the ALE output low. This disables the
latches (8282) and holds the address information latched on the latch outputs.
The address information latched on the latch outputs can now be used to select
thedesired memory or port location.

In the timing diagram, the first point at which the two (AD 0 – AD 15 ) cross
represents thetime at which the 8086 has put a valid address on these lines. Two
lines DO NOT indicate that all 16 lines are going high or going low at this
point. The crossed lines indicate the time at whicha valid address is on the bus.