Dummy design rules for HP18

Document name : Dummy-D Version : 0.5 Page : 1 / 27 Date : Apr. 27.
2017
Dummy design rule
Including the following process technology Issued by
Tech : HP18, HM18 Jongyeul Jeong (SPD team)
Checked by
Kangsub Shin (SPD team)
Approved by
DCRB reviewers
The information of this document is the exclusive property of MagnaChip Semiconductor Ltd. and shall be kept confidential.
Do not disclose, reproduce, or distribute this information without prior written permission of MagnaChip Semiconductor Ltd.
Document name : Dummy-D Version : 0.5 Page : 2 / 27 Date : Apr. 27. 2017
DCRB reviewer
Approval number DCRB17-052 Date Apr 27, 2017
Area Result
AMS/HV Pass
BCD Pass
Device & PI
NVM Pass
RF/SOI Pass
SPICE modeling Pass
Library Pass
IP Pass
PDK Pass
Mask tooling Pass
BEOL & option Pass
Champion Pass
Coordinator Pass
Contents
Contents Page
0. Revision history 4
1. GDS layer information 6
2. Terminology definition 10
3. Dummy active drawing rules 14
4. Dummy poly drawing rules 18
5. Dummy metal drawing rules 21
6. Dummy metal drawing rules for thick top metal 24
Disclaimer 27
Revision history
Date Version Descriptions Issued by
Nov 4, 2015 0.1 - Initial release JY Jeong
Dec 9, 2015 0.1a - Add the rule DMP.S.8 for POLYbl JY Jeong
- Add POLYbl(#63)
Feb 24, 2016 0.1b - Changing the rule of DMA.S.5, DMP.S.8, DMM.S.10~12 and DMTM.S.4 as JY Jeong
the space rule between dummy blocking layers
- Adding the rule of DMA.EN.4, DMP.EN.1, DMM.EN.1~3 and DMTM.EN.1
- Adding the rule of DMA.OT.7,8,9.N, DMP.OT.4,5.N, DMM.OT.6,7.N and
DMTM.OT.5,6.N
- Delete the rule of DMA.OT.6, DMP.OT.3, DMM.OT.5, DMTM.OT.4 and
related notes
- Changing the description of DMM.OT.2, DMTM.OT.2
Apr 6, 2016 0.2 - Add the gds layer information for HM18EH30 tech JY Jeong
- Add the dummy rule for HM18EH30 tech
- Change the description of DMA.S.3 in dummy active drawing rule
Oct 13, 2016 0.3 - Add a page for “available tech” JY Jeong
- Change the supporting tech name from “HP18E80, HM18EH30” to “HP18,
HM18”
Jan 19, 2017 0.4 - Add DTI(#185,0) on 1-1) Layer for HP18 tech JY Jeong
- Add rule DMA.S.10, DMP.S.9, DMP.EN.2, DMP.OT.4.1 and DMP.OT.5.1
for HP18tech
- Add rule DMP.EN.2, DMP.OT.4.1 and DMP.OT.5.1 for HM18tech
Apr 27, 2017 0.5 - Add VOP* (#24,*) layer for HP18 tech JY Jeong
- Add rule DMA.S.11 and DMP.S.10 for VOP layer in HP18 tech
- Delete a rule DMA.S.5
- Available tech -
Please check the main tech document whether this design rule is
available or not.
1. GDS layer information

1-1) Layer for HP18 tech
Layer Layer Data
Description Remarks
name number type
NACT 1 0 N+ active
NW 2 0 N-well
POLY 3 0 Poly
NPSD 4 0 N+ implantation
PPSD 5 0 P+ implantation
CONT 7 0 Contact
MET1 9 0 1st metal
VIA1 10 0 Via 1
MET2 11 0 2nd metal
VIA2 12 0 Via 2
MET3 13 0 3rd metal
VIA3 14 0 Via 3
MET4 15 0 4th metal
VIA4 16 0 Via 4
MET5 17 0 5th metal
VIA5 18 0 Via 5
MET6 19 0 6th metal
PACT 30 0 P+ active
M1BL 48 0 Dummy metal blocking for metal1
POLYbl 63 0 Dummy poly blocking
PBODY 85 0 nLDMOS body
R 87 0 Dummy active blocking

MIMBOT 110 0 MIM bottom metal area for DRC / LVS
HDNW 173 0 High voltage deep N-well
DTI 185 0 Deep trench isolation
DPW 192 0 High voltage deep P-well

VOP* 24 * High voltage area for multi voltage option * Refer to the tech. docu.
MCAP 119 0 MOM capacitor for DRC/LVS

1-2) Layer for HM18 tech
Layer Layer Data
Description Remarks
name number type
NACT 1 0 N+ active
NW 2 0 N-well
POLY 3 0 Poly
NPSD 4 0 N+ implantation
PPSD 5 0 P+ implantation
CONT 7 0 Contact
MET1 9 0 1st metal
VIA1 10 0 Via 1
MET2 11 0 2nd metal
VIA2 12 0 Via 2
MET3 13 0 3rd metal
VIA3 14 0 Via 3
MET4 15 0 4th metal
VIA4 16 0 Via 4
MET5 17 0 5th metal
VIA5 18 0 Via 5
MET6 19 0 6th metal
PACT 30 0 P+ active
TKM 58 0 Thick top metal
POLYbl 63 0 Dummy poly blocking
R 87 0 Dummy active blocking
MIMBOT 110 0 MIM bottom metal area for DRC / LVS
MCAP 119 0 MOM capacitor for DRC/LVS

1-2) Layer for HM18 tech
Layer Layer Data
Description Remarks
name number type
HNW 138 0 N-well of high voltage PMOS
HPW 139 0 P-well of high voltage NMOS and EEPROM cell
HNW30 138 30 N-well for high voltage PMOS for 30V
HPW30 139 30 P-well for high voltage NMOS for 30V
HNACT 142 0 N+ active and NMOS channel area for 30V
HPACT 143 0 P+ active and PMOS channel area for 30V
HNI 144 0 N+ implantation area for 30V
HPI 145 0 P+ implantation area for 30V
FGPOLY 164 0 EEPROM floating gate
NVMA 166 0 EEPROM cell region
HDNW 173 0 EEPROM high voltage deep N-well
PSUB 189 0 High voltage native area

2) Drawn layer for dummy
Layer Layer Data

Description Remarks
name number type
ACTDUD 40 1 Dummy active layer (drawing layer)
POLYDUD 62 1 Dummy poly layer (drawing layer)
M1DUD 64 1 Dummy metal1 layer (drawing layer)
2. Terminology definition
The terminology used in this document is defined as below.
1) Abutting (or Butted)
- A abutting B: The condition whereby the shape A shares part of an edge with shape B such that the
shapes do not have any area in common, and they only touch along the common edge.
The shapes abut even if they only share one common vertex.
A B Abutting B (min and max space= 0)

Butted B or Butted A
2) Area
- The area (length × width) of each individual shape
Length
Area Width
3) CONT
- Contact
4) Cut
- B cut A: A part of shape A overlapped or intersected by shape B is to be removed.
A A
B
B
B A
Case 1 Case 2 Case 3

5) Density
- The ratio of the area of all shapes on layer A within a window divided by the area of the window
6) Enclosed area
- The space between the outside edges of one or more individual shapes
Layer A
Enclosed area
Enclosed
Layer A area
7) Enclosure of B by A
- All vertices of shape B are completely contained within the inside edges of shape A; coinciding is
permitted
A
A
A B A
B
B a A
a
Min. and Max. enclosure Enclosure of B by A (Cross section)
of B by A (a= 0um) (a >= 0um)
8) Extension of A from B
- The spacing of all inside edges of shape A to outside edges of shape B when A intersects B.
Equivalence definition is A extension beyond B.
b
B
A
a: Extension of A from B
b: Extension of B from A
9) Gate length
- The width of polysilicon over the active area
10) Gate width

- The width of the active area under polysilicon
Poly
c Gate poly
a: Gate width
a Active b: Gate length
b
c: Poly end cap
c
11) Interact with

- It means the butted, overlap, extension, and enclosure
butted
extension enclosure
A A
B A B
B
overlap
12) Length
- The distance between the inside edges of an individual shape
- Length is the longer side of the shape measured between parallel edges or edges that form an angle of
less than 90°
13) Mt
- Top metal
14) Orthogonal
- All edges of shapes should be parallel to the x and y axes
15) Orthogonal rectangle

- Shape is a rectangle with all edges parallel to the x and y axes
16) Overlap of A over B

- The distance from all inside edges of shape A to the inside edges of B when A intersects B
A
A
a
B
a
B
Overlap of B over A or Overlap of A over B
17) Parallel run length

- The distance that two shapes run parallel. This applies even if the shapes turn as long as the Minimum
space between them does not effectively change.
A
B A
Case 2)
Parallel run length Case 1)
Case 1) Min. space between A and B when the parallel run length is greater than or equal to xx.xx um
Case 2) Min. parallel run length of A with B when extension of B from A is less than xx.xx um
18) A sized by x
- Expanding or Shrinking A by x per edge, where x is positive (expanding) or negative
(shrinking). @ is the symbol of sizing. (@x: Expanding by x, @-x: Shrinking by x )
x A x
A
x x x x
x x
A sized by x (A@x) A sized by -x (A@-x)
19) Space & notch

- The distance between all outside edges of all shapes; abutting is prohibited.
A B
Space between A and B

Space between two As, for same layer
20) B surrounded by A
- Shape A abut on and is encircled by Shape B. But Shape is not enclosed by Shape B
A
B
A B A
a
B surrounded by A (Cross section)
21) Touching
- C touching D: all shapes on level C that are abutting or intersecting shapes on level D.
- C not touching D: all shapes on level C that do not have a common area with any shapes on level D.
Shapes on level C that have common edges with shapes on level D are not included
in the result.
22) Width
- The distance between the inside edges of an individual shape. Width is the shorter side of the shape
measured between parallel edges or edges that form an angle of less than 90°
3. Dummy active drawing rules
3-1. Dummy active drawing rules for HP18 tech

Rule No. Symbol Note Description Value (um)
DMA.W.1 A Min. and Max. width of ACTDUD 0.5
DMA.L.1 L Min. ~ Max. length of ACTDUD 0.5 ~ 10.0
DMA.S.1 B Min. space between two ACTDUDs 0.7
DMA.S.2 C Min. space between ACTDUD and active (NACT,PACT) (overlap is not allowed) 1.2
DMA.S.3 E Min. space between ACTDUD and NW 0.6
DMA.S.4 F Min. space between ACTDUD and POLY (overlap is not allowed) 1.2
DMA.S.6 J Min. space between ACTDUD and HDNW (overlap is not allowed) 5.0
DMA.S.7 K Min. space between ACTDUD and DPW (overlap is not allowed) 5.0
DMA.S.8 M Min. space between ACTDUD and PBODY (overlap is not allowed) 5.0
DMA.S.10 O 1 Min. space between ACTDUD and DTI (overlap is not allowed) 5.0
DMA.S.11 P 1 Min. space between ACTDUD and VOP (overlap is not allowed) 0.0
DMA.EN.1 D Min. enclosure of ACTDUD by NW 0.6
Min. enclosure of ACTDUD on NW by NPSD
DMA.EN.2 G 0.2
- ACTDUD on NW should be enclosed by NPSD
Min. enclosure of ACTDUD on PW by PPSD
DMA.EN.3 H 0.2
- ACTDUD on PW should be enclosed by PPSD
DMA.EN.4 N Min. enclosure of ACTDUD by R 0.0
It is not allowed to draw ACTDUD using diagonal line.
DMA.OT.1
Only rectangular or square types are allowed.
To improve the process window, customer should fill the dummy uniformly even if
DMA.OT.3.N
originally drawn layer has already met the density rule
ACTDUD should be drawn with maximum length. ACTDUD can be drawn with smaller
DMA.OT.4.N
length only in the area which is not sufficient for maximum length.
DMA.OT.5 Contact on ACTDUD is not allowed.
DMA.OT.7 Pattern density rule and wide field rule should be met in the R area
DMA.OT.8 ACTDUD should be enclosed by R
Dummy pattern will be generated automatically during mask tooling. Please draw the
DMA.OT.9.N
R at the area where customer does not want dummy generation.
Note 1. This rule is for the tech using DTI layer or VOP layer
R
POLY
G
H
N
L A D F
H
E B
C C J
ACTDUD
HDNW
PACT NACT
K DPW
P
VOP
PACT
O M
NW PW (generated layer) DTI PBODY
: NW : POLY : NACT : PACT : ACTDUD : NPSD : PPSD
:R : HDNW : DPW : PBODY : DTI : VOP
3-2. Dummy active drawing rules for HM18 tech

Rule No. Symbol Description Value (um)
DMA.W.1 A Min. and Max. width of ACTDUD 0.5
DMA.L.1 L Min. ~ Max. length of ACTDUD 0.5 ~ 10.0
DMA.S.1 B Min. space between two ACTDUDs 0.7
DMA.S.2 C Min. space between ACTDUD and active (NACT,PACT) (overlap is not allowed) 1.2
DMA.S.2.1 C1 Min. space between ACTDUD and active (HNACT,HPACT) (overlap is not allowed) 3.0
DMA.S.3 E Min. space between ACTDUD and NW 0.6
Min. space between ACTDUD and well (HNW, HPW, HDNW, PSUB,
DMA.S.3.1 E1 2.0
NVMA,HNW30,HPW30)
DMA.S.4 F Min. space between ACTDUD and POLY (overlap is not allowed) 1.2
DMA.S.9 P Min. space between ACTDUD and FGPOLY (overlap is not allowed) 1.2
DMA.EN.1 D Min. enclosure of ACTDUD by NW 0.6
DMA.EN.1.1 D1 Min. enclosure of ACTDUD by well (HNW, HPW, HDNW, PSUB, NVMA, HNW30, HPW30) 2.0
DMA.EN.4 N Min. enclosure of ACTDUD by R 0.0
It is not allowed to draw ACTDUD using diagonal line.

DMA.OT.1
To improve the process window, customer should fill the dummy uniformly even if originally
DMA.OT.3.N
drawn layer has already met the density rule
ACTDUD should be drawn with maximum length. ACTDUD can be drawn with smaller
DMA.OT.4.N
length only in the area which is not sufficient for maximum length.
DMA.OT.5 Contact on ACTDUD is not allowed.

DMA.OT.7 Pattern density rule and wide field rule should be met in the R area
DMA.OT.8 ACTDUD should be enclosed by R
Dummy pattern will be generated automatically during mask tooling. Please draw the R at
DMA.OT.9.N
the area where customer does not want dummy generation.
3-2. Dummy active drawing rules for HM18 tech
R
POLY
N ACTDUD
L A D F
ACTDUD
E B
C ACTDUD
active C
(NACT or
PACT) active
(NACT or
NW PACT)
PW (generated layer) P
well FGPOLY
(HNW, HPW, D1 E1
HDNW, PSUB, : ACTDUD : ACTDUD
well
NVMA,HNW30,H (HNW, HPW,HDNW,
PW30) PSUB, NVMA,)
C C1
active active
(NACT or (HNACT or
PACT) HPACT)
: NW : POLY : active : active : ACTDUD

(HNACT or (NACT or
HPACT) PACT)
: FGPOLY : well (HNW, HPW, HDNW, :R

PSUB, VMA,HNW30,HPW30)
4. Dummy poly drawing rules
4-1. Dummy poly drawing rules for HP18 tech

Rule No. Symbol Note Description Value (um)
DMP.W.1 A Min. width of POLYDUD 0.6
DMP.S.1 B Min. space between two POLYDUDs 0.3
DMP.S.2 C Min. space between POLYDUD and active (NACT,PACT) (overlap is not allowed) 1.2
DMP.S.3 D Min. space between POLYDUD and ACTDUD (overlap is not allowed) 0.3
DMP.S.4 E Min. space between POLYDUD and POLY (overlap is not allowed) 1.2
DMP.S.5 F Min. space between POLYDUD and SEALRING (inside edge) (overlap is not allowed) 2.5
DMP.S.6 H Min. space between POLYDUD and HDNW (overlap is not allowed) 5.0
DMP.S.7 I Min. space between POLYDUD and DPW (overlap is not allowed) 5.0
DMP.S.8 J Min. space between two POLYbls 1.2
DMP.S.9 K 1 Min. space between POLYDUD and DTI (overlap is not allowed) 5.0
DMP.S.10 M 1 Min. space between POLYDUD and VOP (overlap is not allowed) 0.0
2
DMP.A.1 G Min. area of POLYDUD 1.2um
DMP.EN.1 N Min. enclosure of POLYDUD by POLYbl 0.0
DMP.EN.2 L Min. enclosure of POLYDUD by R 0.3
It is not allowed to draw POLYDUD using diagonal line.
DMP.OT.1
DMP.OT.2 Contact on POLYDUD is not allowed.
DMP.OT.4 POLYDUD should be enclosed by POLYbl
DMP.OT.4.1 Both POLYDUD and ACTDUD should be enclosed by R
Dummy pattern will be generated automatically during mask tooling. Please draw the POLYbl
DMP.OT.5.N at the area where customer does not want dummy generation.
(It depends on the mask tooling of each tech. Please refer the mask tooling spec)
ACTDUD and R should be used where the area of POLYDUD was used to prevent the
DMP.OT.5.1 overlap of POLYDUD and dummy active pattern generated automatically during mask tooling.
(refer to the “3. Dummy active drawing rules” in this document for ACTDUD and R)
Note 1. This rule is for the tech using DTI layer or VOP layer
L
POLYbl
F POLYbl
POLYDUD
H POLY
A
E
D
C
POLYDUD
B N
M G
I K J
active
(NACT,PACT) ACTDUD
: POLY : POLYDUD : active (NACT, PACT) : ACTDUD : DTI : VOP
: HDNW : DPW : POLYbl : SEALRING :R
4-2. Dummy poly drawing rules for HM18 tech

DMP.W.1 A Min. width of POLYDUD 0.6
DMP.S.1 B Min. space between two POLYDUDs 0.3
DMP.S.2 C Min. space between POLYDUD and active (NACT,PACT) (overlap is not allowed) 1.2
DMP.S.2.1 C1 Min. space between POLYDUD and active (HNACT,HPACT) (overlap is not allowed) 3.0
DMP.S.3 D Min. space between POLYDUD and ACTDUD (overlap is not allowed) 0.3
DMP.S.4 E Min. space between POLYDUD and POLY (overlap is not allowed) 1.2
DMP.S.4.1 E1 Min. space between POLYDUD and FGPOLY (overlap is not allowed) 1.2
DMP.S.5 F Min. space between POLYDUD and SEALRING (inside edge) (overlap is not allowed) 2.5
DMP.S.8 J Min. space between two POLYbls 1.2
2
DMP.A.1 G Min. area of POLYDUD 1.2um
DMP.EN.1 N Min. enclosure of POLYDUD by POLYbl 0.0
DMP.EN.2 L Min. enclosure of POLYDUD by R 0.3
It is not allowed to draw POLYDUD using diagonal line.
DMP.OT.1
DMP.OT.2 Contact on POLYDUD is not allowed.
DMP.OT.4 POLYDUD should be enclosed by POLYbl
DMP.OT.4.1 Both POLYDUD and ACTDUD should be enclosed by R
ACTDUD and R should be used where the area of POLYDUD was used to prevent the overlap of
DMP.OT.5.1 POLYDUD and dummy active pattern generated automatically during mask tooling.
(refer to the “3. Dummy active drawing rules” in this document for ACTDUD and R)
L
POLYbl
F POLYbl
POLYDUD
A POLY
E
D
C C1
POLYDUD
B N
E1 G
J
active active
(NACT (HNACT ACTDUD
FGPOLY
,PACT) ,HPACT)
: POLY : active (NACT, PACT) : active (HNACT, : ACTDUD

HPACT)
: POLYDUD : POLYbl : FGPOLY : SEALRING :R
5. Dummy metal drawing rules

DMM.W.1 A Min. and Max. width of M1DUD 0.5
DMM.W.2 A Min. and Max. width of MxDUD 0.5
DMM.W.3 A Min. and Max. width of MtDUD 1.0
DMM.L.1 L Min. ~ Max. length of M1DUD 0.5~10.0
DMM.L.2 L Min. ~ Max. length of MxDUD 0.5~10.0
DMM.L.3 L Min. ~ Max. length of MtDUD 1.0~10.0
DMM.S.1 B Min. space between two M1DUDs 0.7
DMM.S.2 B Min. space between two MxDUDs 0.7
DMM.S.3 B Min. space between two MtDUDs 1.2
DMM.S.4 C Min. space between M1DUD and M1 (overlap is not allowed) 5.0
DMM.S.5 C Min. space between MxDUD and Mx (overlap is not allowed) 5.0
DMM.S.6 C Min. space between MtDUD and Mt (overlap is not allowed) 5.0
DMM.S.7 D Min. space between M1DUD and Mn+1 in MIMBOT (overlap is not allowed) 0.0
DMM.S.8 D Min. space between MxDUD and Mn+1 in MIMBOT (overlap is not allowed) 0.0
DMM.S.9 D Min. space between MtDUD and Mn+1 in MIMBOT (overlap is not allowed) 0.0
DMM.S.10 E Min. space between two M1BLs 5.0
DMM.S.11 E Min. space between two MxBLs 5.0
DMM.S.12 E Min. space between two MtBLs 5.0
DMM.S.13 F Min. space between M1DUD and MCAP (overlap is not allowed) 0.0
DMM.S.14 F Min. space between MxDUD and MCAP (overlap is not allowed) 0.0
DMM.S.15 F Min. space between MtDUD and MCAP (overlap is not allowed) 0.0
DMM.EN.1 N Min. enclosure of M1DUD by M1BL 0.0
DMM.EN.2 N Min. enclosure of MxDUD by MxBL 0.0
DMM.EN.3 N Min. enclosure of MtDUD by MtBL 0.0
It is not allowed to draw M1DUD, MxDUD and MtDUD using diagonal line.
DMM.OT.1
Contact or via in dummy metal is not allowed.
DMM.OT.2
(Ex. contact and via1 in M1DUD, via1 and via2 in M2DUD are not allowed)
DMM.OT.3.N
M1DUD (and MxDUD, MtDUD) should be drawn with maximum length. M1DUD (and
DMM.OT.4.N MxDUD, MtDUD) can be drawn with smaller length only in the area which is not sufficient
for maximum length.
DMM.OT.6 M1DUD (and MxDUD, MtDUD) should be enclosed by M1BL (and MxBL, MtBL)
Dummy pattern will be generated automatically during mask tooling.
DMM.OT.7.N Please draw the M1BL(and MxBL, MtBL) at the area where customer does not want
dummy generation.
Note 1. M1 means metal1 layer, Mx means intermediate metal layer, Mt means top metal layer.
Note 2. M1DUD means dummy metal1 layer, MxDUD means dummy intermediate metal layer, MtDUD means dummy top metal layer.
Note 3. M1BL means dummy metal1 blocking layer, MxBL means dummy intermediate metal blocking layer,
MtBL means dummy top metal blocking layer.
Note 4: Mn+1 means MIM bottom metal
L B C
B
M1BL D Mn+1
N A M1DUD (MxDUD, MtDUD)
(MxBL,
MtBL) E F MIMBOT
MCAP
M1 M1
(Mx, Mt) (Mx, Mt)
M1BL
(MxBL, MtBL)
: M1 or Mx, Mt : Mn+1
: MIMBOT
: MCAP
: M1DUD or MxDUD, MtDUD
: M1BL or MxBL, MtBL
6. Dummy metal drawing rules for

thick top metal
6-1. Dummy metal drawing rules for thick top metal for HP18 tech
DMTM.W.1 A Min. and Max. width of MtDUD 5.0
DMTM.L.1 L Min. and Max. length of MtDUD 5.0
DMTM.S.1 B Min. space between two MtDUDs 5.0
DMTM.S.2 C Min. space between MtDUD and Mt (overlap is not allowed) 5.0
DMTM.S.3 D Min. space between MtDUD and Mn+1 in MIMBOT (overlap is not allowed) 0.0
DMTM.S.4 E Min. space between two MtBLs 5.0
DMTM.S.5 F Min. space between MtDUD and MCAP (overlap is not allowed) 0.0
DMTM.EN.1 N Min. enclosure of MtDUD by MtBL 0.0
It is not allowed to draw MtDUD using diagonal line.

DMTM.OT.1
DMTM.OT.2 Top via in dummy top metal is not allowed
DMTM.OT.3.N
DMTM.OT.5 MtDUD should be enclosed by MtBL

DMTM.OT.6.N
Please draw the MtBL at the area where customer does not want dummy generation.
Note 1. This rule should be used when using the Mt as thick top metal.
Note 2. MtDUD means dummy top metal layer.
Note 3. MtBL means dummy top metal blocking layer.
L
B
A
MtDUD MtDUD
Mn+1
B
N D
MIMBOT
MtBL MtDUD MtDUD
E
F C
C
MtDUD Mt
MCAP
Mt
MtBL
: Mt : MIMBOT : MCAP : MtDUD : MtBL
: Mn+1
6-2. Dummy metal drawing rules for thick top metal for HM18 tech
DMTM.W.1 A Min. and Max. width of MtDUD 5.0
DMTM.L.1 L Min. and Max. length of MtDUD 5.0
DMTM.S.1 B Min. space between two MtDUDs 5.0
DMTM.S.2 C Min. space between MtDUD and TKM (overlap is not allowed) 5.0
DMTM.S.3 D Min. space between MtDUD and Mn+1 in MIMBOT (overlap is not allowed) 0.0
DMTM.S.4 E Min. space between two MtBLs 5.0
DMTM.S.5 F Min. space between MtDUD and MCAP (overlap is not allowed) 0.0
DMTM.EN.1 N Min. enclosure of MtDUD by MtBL 0.0
It is not allowed to draw MtDUD using diagonal line.

DMTM.OT.1
DMTM.OT.2 Top via in dummy top metal is not allowed
DMTM.OT.3.N
DMTM.OT.5 MtDUD should be enclosed by MtBL

DMTM.OT.6.N
Please draw the MtBL at the area where customer does not want dummy generation.
Note 1. TKM is thick top metal layer.

Note 2. MtDUD means dummy top metal layer.
Note 3. MtBL means dummy top metal blocking layer.
L
B
A
MtDUD MtDUD
Mn+1
B
N D
MIMBOT
MtBL MtDUD MtDUD
E
F C
C
MtDUD TKM
MCAP
TKM
MtBL
: TKM : MIMBOT : MCAP : MtDUD : MtBL
: Mn+1
Disclaimer
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Dummy design rules for HP18

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Dummy design rules for HP18

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Document name : Dummy-D Version : 0.5 Page : 1 / 27 Date : Apr. 27.

Dummy design rule

Including the following process technology Issued by

Tech : HP18, HM18 Jongyeul Jeong (SPD team)

Kangsub Shin (SPD team)

SPICE modeling Pass

Mask tooling Pass

BEOL & option Pass

1. GDS layer information 6

3. Dummy active drawing rules 14

4. Dummy poly drawing rules 18

5. Dummy metal drawing rules 21

6. Dummy metal drawing rules for thick top metal 24

Date Version Descriptions Issued by

Nov 4, 2015 0.1 - Initial release JY Jeong

1. GDS layer information

M2BL 49 0 Dummy metal blocking for metal2

M3BL 50 0 Dummy metal blocking for metal3

M4BL 51 0 Dummy metal blocking for metal4

M5BL 52 0 Dummy metal blocking for metal5

M6BL 53 0 Dummy metal blocking for metal6

POLYbl 63 0 Dummy poly blocking

PBODY 85 0 nLDMOS body

R 87 0 Dummy active blocking

DTI 185 0 Deep trench isolation

DPW 192 0 High voltage deep P-well

1. GDS layer information

M1BL 48 0 Dummy metal blocking for metal1

M2BL 49 0 Dummy metal blocking for metal2

M3BL 50 0 Dummy metal blocking for metal3

M4BL 51 0 Dummy metal blocking for metal4

M5BL 52 0 Dummy metal blocking for metal5

M6BL 53 0 Dummy metal blocking for metal6

TKM 58 0 Thick top metal

POLYbl 63 0 Dummy poly blocking

R 87 0 Dummy active blocking

MIMBOT 110 0 MIM bottom metal area for DRC / LVS

MCAP 119 0 MOM capacitor for DRC/LVS

1. GDS layer information

HNW 138 0 N-well of high voltage PMOS

HPW 139 0 P-well of high voltage NMOS and EEPROM cell

HNW30 138 30 N-well for high voltage PMOS for 30V

HPW30 139 30 P-well for high voltage NMOS for 30V

HNACT 142 0 N+ active and NMOS channel area for 30V

HPACT 143 0 P+ active and PMOS channel area for 30V

HNI 144 0 N+ implantation area for 30V

HPI 145 0 P+ implantation area for 30V

FGPOLY 164 0 EEPROM floating gate

NVMA 166 0 EEPROM cell region

HDNW 173 0 EEPROM high voltage deep N-well

PSUB 189 0 High voltage native area

1. GDS layer information

Layer Layer Data

ACTDUD 40 1 Dummy active layer (drawing layer)

POLYDUD 62 1 Dummy poly layer (drawing layer)

M1DUD 64 1 Dummy metal1 layer (drawing layer)

M2DUD 66 1 Dummy metal2 layer (drawing layer)

M3DUD 67 1 Dummy metal3 layer (drawing layer)

M4DUD 68 1 Dummy metal4 layer (drawing layer)

M5DUD 69 1 Dummy metal5 layer (drawing layer)

M6DUD 70 1 Dummy metal6 layer (drawing layer)

A B Abutting B (min and max space= 0)

Case 1 Case 2 Case 3