Downloaded From www.rejinpaul.com Reg. No. |_| [ Question Paper Code: 77123 B.E/B.Tech. DEGREE EXAMINATION, APRIL/MAY 2015. a ‘Third Semester ax ? BN Eleetrical and Electronics Engineering EE 6301 — DIGITAL LOGIC CIRCUITS, we (Common to Electronics and Instrumentation Engineering and I euffentation and Control Engineering) (Regulation 2013) ‘Time : Three hours PART AS aol Aes my Y ® 1. Convert A Y (a) (475.20), to its pene ) (649.B4),, to if bi ‘equivalent. 2, Define propagation d ay. 3. Convextiihe given expression in canonical SOP form Y=AC+AB+BC. Aon \ ‘Simplify the expression Z = AB+ AB.(4.C]) “B. ‘State the rules for state assignment. 7. State the difference between static 0 and static | hazard. 8. What is a PROM? 9. Whatis a package in VHDL? inpaul.com S59), re (Grow With Us 10. Write the behavioral modeling ende for a D Flip eSDownloaded From www.rejinpaul.com — PART B— x 16 = 80 marks) 11. (@) @ Perform the following addition using BCD and Bxcess-8 addition (205 +569). ® Gi) Encode the binary word TOU siip avon bit sven parity Hamming) code. @ ‘ f Q ) @ With circuit schematic, explain thé operation of a cc FTL NAND gate with totem-pole output 4 ao (i) ‘Compare totem pole and open collector utpats\, e © y 12. (a) (@ Reduce the following function using kath } AABCD)=2M(0.2,8,8,8,12.18,18) (~ » @ Gi) Design a full edder using two hy aad and an OR gate. 8) my &) @) Design a BCD capone de 5 ae ®) (i) Implemont the satdrige Botsan function using 8:1 Mux: F(A,B,C,D): 1,3,4,8,9,15). ® 13, @ @ Explain Si ofa master slave JK flip flop. ® y 8) pedgn islual niece yea ateer iss ® Ann, _ Or (fts@, Design a MOD-5 synchronous counter using JK flip-flops. ®) eae i) Design a sequence detector to detect the sequence 101 using JK flip an flop. ®) 14. (@) Design an asynchronous sequential circuit that has two inputs X, and X, and one output Z. When X,=0, the output Z is 0. The first change in X, that occurs while X, is 1 will cause output Z to be 1. The output Z, will remain 1 until X, reams to 0. Or ul.com Geel ith usDownloaded From www.rejinpaul.com (b) .@) Implement the following function using PLA + m(1,2,4,6) F(ey,2) (i) For the given boolean function, obtain the hazard-free circuit (A,B,C, D)=2m(1,3,6,7,13,15). 18. (a) Write the VHDL code to realize a full adder using @ Behavioral medeling (3) Structural modeling. Or ie (®) Write the VHDL code to realize a 3-bit Gray ae using case statement. (16) } : 4 SSprtinnant.com (Grow With Us