CMOS Device Optimization for Mixed-Signal Technologies

P.A. Stok', H.P. Tuinhout', R. Duffy', E. Augendre3,L.P. Bellefioid4, M.J.B.Bolt', J. Croon:,

C.J.J.Dachs', F.R.J.Huisman', A.J. Moonen , Y .V. Ponomarev', R.F.M. Roes lM. Da Rold ,
E. S e e ~ i n c k ~K.N.
. ~ , Sreerambhatla4,R. Surdeanu', R.M.D.A. Velghe', M. Vertregt ,M.N. Webste?,
N.K.J. van Winkelhop, A.T.A. Zegers-Van Duijnhoven2
'Philips Research Leuven, Kapeldreef 75, B-3001 huven, Belgium; 2PhilipsResearch Laboratories, Eindhoven, The
Netherlands; 31MEc,Leuven, Belgium; QMDC, Philips Semiconductors, Eindhoven, The Netherlands; 'Philips
Semiconductors, Mjmegen, The Netherlands; 'Circuit Research International, firsel, The Netherlands.

Abstract
20
This paper studies the suitability of CMOS device technology
for mixed-signal applications. The currently proposed scaling
scenario's for CMOS technologies lead to strong degradation
of analog transistor performance. As a result, the combined
optimization of digital and analog devices for system-on-a- AAn=3 mVum 5 0

chip applications will require increasingly elaborate process

modifications. New device solutions such as metal gate
integration and asymmetric (source-side-only) workfunction
modification offer process options for future mixed-signal
'0 6
!
1
CMOS applications. 0 ---r-----i
0.00 1.00 2.00 3.00 4.00 6.00
Introduction l/sqrt(WL) [Ilum]
Figure 1. Standard deviation of the threshold voltage difference of
The increasing demand for integrating mixed-signal functions matched transistor pairs BS a function of the device area for 0.18 pm
on a single chip calls for dedicated optimization of device NMOS technology (oxide thickness T 6 3 . 2 nm).
technology aimed at both digital and analog applications [ 11.
Since logic devices are generally not optimized for analog
functionality, process modifications or extensions are often
needed to meet mixed-signal requirements. In order to
maximize the efficiency and minimize the cost at which
mixed-signal CMOS functionality can be accomplished a
good understanding of the intrinsic trade-off between digital
and analog performance of CMOS technology is required.
This paper investigates how the proposed scaling
scenario's for digital CMOS technology affect analog
performance. To this end, the limits of some of the key
process performance indicators for mixed-signal CMOS 0 ' A 0.1 urnanaiytcal
applications are explored: threshold voltage matching, l/f
0.1 pl -0.1 urntrend
noise, and voltage gain. Alternative device architectures such -20 1
as those based on metal gate electrodes and lateral work 0 2 4 6 8 1 0 1 2
function engineering are also evaluated in terms of possible
%vt (mVum)
analog performance improvements.
Figure 2. Analytical calculations (points) of static noise margin average
Matching (p)and spreading ( 0 )as a function of the mismatch coefficient for S R A M
cells in 0.18 and 0.1 pm CMOS. To ensure SFL4M stability, the plotted
Threshold voltage fluctuations of several mV determine the value of p - 4 should
~ exceed -4% of Vdd (dashed lines: p50 >72 mV for
0.18 and >40 mV for 0.1 pm). The 0.18 p n analytical results were
performance and yield of analog circuit blocks, such as confinned by statistical circuit simulations (solid line).
current mirrors, A/D and D/A converters, etc. [2]. As
illustrated by Fig. 1, the standard deviation of the threshold
voltage mismatch (AVt) among pairs of MOS transistors disproportionately large due to junction underfision [5]
(GAVJ is related to the device area according to [2]: and pocket implants dominating the channel doping level
OAvt'AAvtX (WL)-"'. The matching coefficient AAvtrepresents i6.71.
stochastic sources of transistor spread, including channel The A A v t coefficient should be minimized not only to
dopant fluctuations [3], poly grain effects [4], etc. Note that enhance analog performance but also for reaching acceptable
for small gate lengths, cAvtin Fig. 1 becomes (embedded) SRAM yield [SI.An analytical model, based on

0-7803-7050-3/01/$10.00 02001 IEEE 10.2.1 IEDM 01-215

[9], can be used to assess the impact of transistor mismatch
on the static noise margin (SNM) of SRAM cells by
estimating the average (p) and standard deviation (0)of
SNM. Figure 2 shows the calculated p40 of SNM for typical
SRAM cells in 0.18 and 0.1 pm CMOS technologies. As
apparent from Fig. 2, inferior transistor matching (i.e.,
increased AAvt)leads to a reduction in p40, which implies
that an increasingly large fraction of the SRAM cells
becomes unstable. As a gudeline, p 4 o is required to exceed
4%of the supply voltage to reach a 90% yield on 1 Mbit
S W ’ S . This @allShteSh 0 A~vt<6and A~vtc2.5m V w for
0.18 and 0.1 pm, respectively. Such severe burdens on AAvt
can be alleviated by an additional Vt implant for the NMOS
devices (Fig. 3), at the expense however, of an additional
maslung step.
I80
140
-20
404 , I
-120 40 0 60 120
Vt-Vtref (rnv)
Figore 3. Calculated response of SNM (p4do) to changing the NMOS
threshold voltage in the 0.1 pm SRAM cell. Increasing Vt above the
nominal voltage (Vtref) increases cell stability by shifting m,and allows
for less stringent requirementson matching parameter &v,.
nmt iot
pocket energy
RTOfor pory oxidation
fiwniwpoc
mod9 poly thickress
optimized process
0 2 4 6 a io
Matching coefficient b,,~(rnVum)
Figure 4. Evolution of NMOS and PMOS matching coefficients in
response to various sequential process improvements (0.18 pm CMOS).
& y ~ 3mVpm is reached in the final development phase for both N- and
PMOS,well belowthe SRAM requirements(Fig. 2).
During process development, dedicated experiments are
usually required to bring AAvtto an acceptable level. This is
illustrated by the example for a 0.18 pm technology in Fig. 4
(see also Ref. 10). By employing process refinements
specifically aimed at reducing microscopic transistor property
fluctuations, the mismatch performance can sipficantly be
improved Figure 5 Summarizes the scaling of AAvt with
technology. In line with older generations [2], AAvt drops
with decreasing oxide thickness, reaching -2.7 m V w for
2 16-IEDM 0 1
ID
-ty--iii
0 1 2 3 4 5
EquivalentTox [nm]
F i p e 5. &,vt vs. oxide thickness for NMOS transistors. Values Gom
recent measurements (triangles) on 0.18 (Figs. 1, 4) and 0.13 pn CMOS
(0.13 pn fiom IMEC 1191 and Philips Research) are compared with AaM-
estimates based on dopant fluctuations for measured devices (squares) and
roadmap guidelines (circles). Similartrends are found for PMOS.
Figure 6. NMOS transistor with -3.5 nm pure gate oxide and TiN/AI metal
gate, fabricated in a 0.15 pn replacement gate process. The channel doping
was defined by well and pocket implants (no Vt-adjust), yielding a
threshold voltage of -0.4 V.
nitrided oxides of 2 nm. The circles in Fig. 5 represent
predictions [5] of AAvt for future “conventional” CMOS
devices architectures, under the bestcase assumption of
statistical dopant fluctuations being the only mismatch
source. Since additional fluctuation effects usually further
degrade mismatch, it will become virtually impossible to
push AAV~ below -2 mVpn in future technology generations
if they are to be based on conventional transistor
architectures.
This limit calls for alternative device architectures such
as retrograde channels (ground plane devices) [5,11,12] or
undoped thin-filmSO1 to minimize the impact of channel
dopant fluctuations, or metal gates to avoid mismatch
associated with poly grain effects [4]. As an illustration,
NMOS transistors with an oxideRiN1Al gate stack (Fig. 6)
and lowly doped channels exhibit good matching behavior at
T,,,-3.5 nm (Fig. 7). This is demonstrated by the fairly low
intrinsic AAvtof 3.6 mVpm, which is a very promising result
in view of the immature processing technology employed to
fabricate the metal gate transistors. In addition, the strong
sensitivity of AAvtto counterdoping As implants confirms
that the matching is dominated by channel dopant variations
rather than gate electrode effects.
10.2.2
 10.00 -
F p z e r d o p e /
8.00

6.00

4.00

2.00
00 02 04 06 08 10
0.00 Gate Length [urn]
0.00 0.50 1.oo 1.so 2.00 Figure 9. NMOS threshold voltage as a function of channel length in 0.15
pm technology. Short channel effects were controlled by conventional B
1/sq rt(W L) [I/U m] counterdoping implants (solid symbols) and lateral workfunction
Figure 7. Matching behavior of NMOS transistors with -3.5 nm pure gate engineering (open symbols; see Fig. 12).
oxide and TiN!A1 metal gate. The good matching for lowly doped channels
(Vt-0.4 V, % ~ = 3 . 6 mVpm) is significantly worsened when As .- I

counterdoping is applied (Vt-0 V; A , ~ ~ = 5 m

. 6V p ) , showing that the
channel doping is the dominant factor in the Vt matching of these metal + Pocket Implants
gate devices.
C. Lateral workfunctan
llf noise 10 engineering

Low-frequency (or l/f noise) is very important for analog and 3 1.E-
RF applications in advanced CMOS technologies. In Fig. 8, I

some trends of l/f noise with gate oxide thickness are shown.
The transition from pure to nitrided furnace oxides for 0.18
pn CMOS and beyond, results in a sigruficant increase in the
Ilf noise level due to nitrogen-induced oxide traps. The 0 60 100 1#) 200 260 300
PMOS noise level is af€ected by the specific nitridation gm(gdsat L=l m
process, suggesting that the exact nitrogen distribution and
concentration wittun the oxide is controlling the noise Fignre 10. Trade-off between digital (IJLfr) and analog (gdrdgd.) in 0.15 pm
NMOS devices for different variants in pocket dose and lateral
behavior. Alternative processing schemes to localize the w o r k h a i o n engineering. Strong short-channel control (i.e., high is
nitrogen at the gate/gatemide interface [I31 (e.g., plasma detrimental for the voltage gain (i.e., low &riar), whereas weak short-
nitridation) may prove beneficial for noise performance. channel control yields the opposite effect.
1 OE-07 Gain
N
A key analog transistor performance indicator that needs to
I,
iOE-08
be maximized, is the so-called voltage gain, defined as the
ratio of the transconductance and outputconductance (U&)
$
=
,>
[l]. It has been shown [14,15] that the pocket implants,
commonly used to control short channel effects (Fig. 9), are
( 1 OE43 detrimental for t h i s voltage gain. This is illustrated for a 0.15
d pm CMOS implementation in Fig. 10 by the trade-off
between digital (IO&*) and analog device performance
1 OE-10
(gdgdg). The degradation of voltage gain arises from the
0 10 20 30 40 50
dram-bias-induced modulation of the barrier created by the
Tox'(nR26 .
pocket on the drain side [14]. Device simulations (Fig. 11)
Figure 8. Input voltage I/f noise spectral ens* at 1Hz as normalized to show that the trade-off between digital and analog degrades
the transistor area. This has been measured at V,=V,=V, on PMOS and for each technology generation, due to the fact that both LE
NMOS devices in IMEC's 0.35 to 0.13 pm process generations (0.35&0.25
pm -pure oxides, 0.18M.13 - nitrided furnace oxides). Predicted noise and g& increase with device down scaling. l l u s puts ever
stronger limits on the maximum voltage gain that can be
~

levels for NMOS devices with pure oxides [ZO] are shown as a reference.
For the post-nitrided oxides used in 0.18 and 0.13 p (circles), a strong
increase in lif noise is observed compared to pure oxides, mainly for
PMOS.
reached in digital technologies, exemp-ng the need for
independent extasiodpocket optimization for analog
devices.
As a possible alternative to pockets, lateral workfunction
engineering of the gate has been proposed for controlling

10.2.3 IEDM 01-217

 Figure 12. Process sequence for fabrication of an NMOS with a laterally
graded workfunction in the gate. After dummy gate removal in replacement
Figure 11. Simulated trade-off between digital (I.&,*) and analog (voltage gate processing, a thin undoped poly layer is deposited (a) upon which As is
gain &ga) for NMOS devices in future CMOS technologies. The device implanted ( 5 keV. 0" tiit) and annealed (b). The trench is filled with poly,
parameters (junction depth, oxide thickness, etc.) and supply voltages used doped with P (c) and planarized (4, followed by contact + 1 metal layer.
in the device simulations were obtained fiom the ITRS roadmap. The shadowed As implant in the fust poly layer (b) leaves lowly doped
regions in the bottom comers of the gate, thereby establishing the desired
short channel effects [16,17]. As an example of a varying lateral grading in the workfunction.
lateral workfunction, we have realized a lateral gradmg of the
doping level in the polysilicon gate using replacement gate References
processing on 0.15 pm NMOS devices (Fig. 12). This novel
D. Buss,IEDM Tech. Digest. 423 (1999).
approach yields a gradual change in the worldimction from nf
M.J.M. Pelgrom eral., IEDM Tech. Digest, 915 (1998).
in the gate center towards mid-gap at the gate edge, thereby
H.P. Tuinhout et al., VLSI Tech. Symp., 134 (2000).
introducing potential baniers at the sourcddrains (similar to
H.P. Tuinhout et al., IEDM Tech. Digest, 631 (1997).
the effect of pockets). Indeed, a strong roll-up in Vt is
P.A Stolk et al.. IEEE Trans. El. Dev. 45, 1960 (1998). The definition
observed (Fig. 9), indicating an efficient compensation of
of & in this paper should be: &=(kBT/q)ln(N/nz).
short channel effects.The digital vs. analog trade-off of these
T. Tanaka et al., IEDM Tech. Digest, 271 (2000).
devices, however, follows the same general trend as the one
R. Dikenza er aI., ESSDERC-OO. 584 (2000).
for pocket implants (Fig. IO). Apparently, the bamer
AJ. Bhavnaganvala er al., IEEE J. Solid-St. Circ. 36,658 (2001).
modulation at the dram is not altered in the case of
E. Seevinck et aL,IEEE J. Solid-St. Circ. 22,748 (1987).
workfunction engineering. Consequently, asymmetric
R. Difienza et OZ., ESSDERC-OI, 299 (2001).
(source-side-only) workfunction modifcation is expected to
K. Takeuchi er OZ., IEDM Tech. Digest. 841 (1997).
sigruficantly improve the voltage gain, comparable to
E. Morihji et al., IEDM Tech. Digest, 459 (2000).
asymmetric pocket implants [ 14,181.
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A Chatlerjeeet al., VLSI Tech. Symp.. 147 (1999).
Conclusion
R.F.M. Roes er aL,ESSDERC-99. 176 (1999).
W. Long and K.K. Chin, IEDM Tech. Digest, 549 (1997).
Conventional scallng scemio's for CMOS technologes lead
S. Tiwari et aL,IEDM Tech. Digest, 737 (1998).
to strong degradation of analog transistor performance. As a
Y.V. Ponomarev er al., ESSDERC-99, 180 (1999).
result, the combined optimization of digital and analog
S. Kubicek et OZ., IEDM Tech. Digest. 823 (1999).
devices will require increasingly elaborate process
M. Knitel et aL,IEDM Tech. Digest 463 (2000).
modifications, making system-on-a-chip applications more
W c u l t and costly to realize on silicon. New device solutions
such as gate engineering provide promising performance for
the development of future mixed-signal CMOS technology.

218-IEDM 01 10.2.4