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Source: Intel
Issue Queue
Prof. Kaushik Roy
@ Purdue Univ.
Implementation of VSV
Variable VDD
VDDH or VDDL
Fixed VDDH
transition energy
overhead
Source: Intel
VDDH VDDL
Time (ns)
High-power mode
L2-miss detected
4 control signal & clock
Half clock-speed
12 VDDH →VDDL
transition
Reach VDDL
Low-power mode
Time (ns)
VDDH VDDL
High-power mode
L2-miss detected
≤10 Down-FSM: Low ILP?
Low ILP? Yes
4 control signal & clock
Half clock-speed
12 VDDH →VDDL
transition
Reach VDDL
Low-power mode
20
MR>4.0 >0.4 ≥0.0
15
10
5
0
-5
MR: L2 misses per 1,000 instructions
perlbmk
ammp
gzip
mgrid
applu
bzip2
galgel
fma3d
equake
mcf
gap
mesa
wupwise
swim
lucas
sixtrack
vpr
parser
twolf
eon
apsi
gcc
vortex
art
crafty
facerec
50
40
30
20
10
0
-10
perlbmk
ammp
mgrid
gzip
applu
bzip2
galgel
fma3d
equake
mcf
gap
mesa
wupwise
swim
lucas
sixtrack
vpr
parser
twolf
eon
apsi
gcc
vortex
art
crafty
facerec