Serial : LS2_W_EE_Analog Electronics_280917

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CLASS TEST ELECTRICAL

2017-18 ENGINEERING

Subject : Analog Electronics

Date of test : 28/09/2017

Answer Key

1. (b) 7. (a) 13. (b) 19. (b) 25. (d)

2. (d) 8. (b) 14. (c) 20. (d) 26. (d)

3. (a) 9. (d) 15. (c) 21. (b) 27. (a)

4. (c) 10. (a) 16. (a) 22. (b) 28. (c)

5. (b) 11. (c) 17. (a) 23. (d) 29. (d)

6. (b) 12. (c) 18. (a) 24. (a) 30. (d)

 CTEE17 • Analog Electronics 7

Detailed Explanations

1. (b)
0 – 0.7 – Ib(β + 1) × 6.3 = –10 V

10 − 0.7
Ib = mA = 18.452 µA
81 × 6.3

2. (d)
∵ Due to given connection D1 will be in forward biased and D2 will be in reverse biased.
Since, 40 V < 50 V (reverse break down voltage of D2)
So it will be in reverse biase condition so allows to flow only reverse saturation (not in breakdown condition)
current i.e. 50 µA and it flows in clockwise direction as source supports it.

3. (a)

–
V0
VS +

φ = 0°
⇒ Phase shift provided by voltage follower.

4. (c)
When both the junctions of transistor are in reverse biased condition then the transistor works in cutoff
region.

5. (b)

f u′ = fu 21/ n − 1
Here, n = 2 (for two amplifiers.)

6. (b)

ηVT 25mV
Diode resistance of the diode, rd = =
ID 1 mA

rd = 25 Ω

7. (a)
More the base doping, more the recombination of the electrons diffusing from emitter to collector smaller is
the common emitter current gain.

8. (b)
Width of depletion region in a PN junction diode decreases with rise in temperature.

9. (d)
Since the amplifier senses current at input therefore it need low input impedance and it produce voltage at
output therefore it need low output impedance.

10. (a)
Clamper circuit do not change shape of the input signal and do not amplifies the input signal, it only
changes the dc level of input signal.

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 8 Electrical Engineering

11. (c)
The circuit is voltage doubler circuit.
Vm
= 120 volts
2
∴ Vm = 120 2
V0 = 2 Vm = 240 2 = 339.41 volts

12. (c)
2 kΩ
i

2 kΩ
–
V0
+ 4V +
– 3mA

4
i = 3mA + mA = 5mA
2
∴ V0 = – (2 kΩ) (5 mA) = –10 volts

13. (b)
Due to cascading voltage gain
AV = AV1 . AV2
AV1 – Voltage gain of 1st stage
AV2 – Voltage gain of 2nd stage
So it increases.
While upper cutoff frequency

fH∗ = fh (21/n − 1) decreases

While lower cutoff frequency

fl
fI∗ = increases compare to single state
1/ n
(2 − 1)
So, B.W. = (fH* − fI∗ ) decreases
as fH* decreases and fI∗ increases.
14. (c)
 20 
V0 =  1 +  6.3 = 18.9 volts
10
15. (c)
Gain-Bandwidth product is always constant for an amplifier.
A1B1 = A2B2
AB = (A + 0.1 A) B2
1
∴ B2 = B
1. 1
1
B− B
∴ % fall = 1.1 × 100 = 0.1 × 100 = 9 .1%
B 1. 1

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 CTEE17 • Analog Electronics 9

16. (a)
3. 6
VTh = × 20 = 4 . 93 volts > Vz
11 + 3. 6
So, voltage point is Vz = 4 volt
11 × 3. 6
RTh = = 2 . 71 kΩ
11 + 13.6
4.93 − 4
∴ Iz = = 0.34 mA
2.71 × 103

17. (a)
V0 = – (2 × 103)(2 × 10–3) = –4 V
Applying KCL at node V0, we get

( )  –4 
– 2 × 10 –3 – I + 
 2 × 10 3 
= 0

( –3
I = – 2 × 10 –  )
 4 
 2 × 10 3 
= –4 mA

18. (a)
Let the device is in forward active region:
Applying KVL in base emitter loop, we get
15 – (300 kΩ)IB – 0.7 – (1 kΩ) (β + 1) IB = 0
So IB = 0.0356 mA
So IC = 3.566 mA, IE = 3.601 mA
Now applying KVL in collection-emitter loop, we get
15 – IC(5 kΩ) – VCE – IE (1 kΩ) = 0
15 – 3.56 × 5 – VCE – 3.60 × 1 = 0
VCE = –6.401 V
Since device cannot be in active region with VCE = –6.401 V, So device is in saturation region.

19. (b)
From the given figure
VG = 0 V, VS = 1 V, VD = 0.3 V
For the PMOS to work in saturation the condition is
V SD ≥ VSG –  VTH
1 – 0.3 ≥ 1 – 0 – –0.4
0.7 ≥ 1 – 0 – –0.4
Since the condition holds true, so the device is in saturation region.

20. (d)
The upper cut off frequency increases with negative feedback so
fH = 40 kHz (1 + Aβ) = 40 (1 + (100 × 0.1)) kHz
= 440 kHz

21. (b)
The voltage at node A and B is 100 mV and 50 mV respectively (applying virtual short concept).

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 10 Electrical Engineering

+
100 mV
– I0
A
50 kΩ
10 kΩ

B
–
50 mV
+

100mV − 50mV 50mV

So, I0 = =
10kΩ 10kΩ
I0 = 5 µA

22. (b)
For dc input (2V) the capacitor acts as open circuit and thus dc input is disconnected from the circuit and
do not affect the output. For ac input (5 sin ωt) the capacitor act as short circuit and thus, output is –5 sin ωt
with zero average value.

23. (d)
Only diode ‘D1’ will be ‘ON’.
So, current through 1 kΩ will be

5
I = = 5 mA
1 × 103
and V = 5 Volt

24. (a)
VP
The ripple voltage Vr =
fCR
VP 100
C = =
fVr R 2 × 60 × 10 × 103
= 83.3 × 10–6 F

25. (d)
The average value of output voltage
Vm
V0 =
π
Vm
According to question, V0 = I 0 (R + 50) =
π

Vm 10
R + 50 = =
π × I 0 π × 1 × 10 −3
R = 3.133 kΩ

26. (d)
Rin = 2 (β + 1)re

= 2 × 101×
25 mV = 2 × 101 × 25 Ω
1mA
= 5050 Ω

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 CTEE17 • Analog Electronics 11

27. (a)
 1+ β
Time period of oscillation is T = 2RC ln 
 1 − β
R 1
Here, β = feedback factor = =
R+R 2
 1
 1 + 
2
⇒ T = 2 × 103 × 10−3 ln
 1
1− 
 2
= 2ln 3
T = 2.19 sec

28. (c)
Applying KCL at inverting terminal of op-amp,
V0 dVc
3
= C
1 × 10 dt
V dt Vt
⇒ Vc = ∫ C ×01000 = C × 1000
0

From the given data we get,

V0 × 10−3
9=
1 × 10−6 × 103
V0 = 9 V
29. (d) 10 kΩ
AC model Vo

vi h fe IB 10 kΩ
Zi = 10 kΩ

AI RL
Mid band voltage gain, Av =
Zi Zi = 10 kΩ

−hfe RL −100 × 10 kΩ
Av = = = –100
Zi 10 kΩ
Av = 100

30. (d)

R V1 R V2 R

R R
R
V0
Vs

V1 = –Vs ...(i)
KCL at node-1:
V1 V1 V1 − V2
+ + =0
R R R

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12 Electrical Engineering

3 V1 = V2
So, V2 = –3Vs ...(ii)
Now, KCL at node-2:
V2 − V1 V2 V2 − Vo
+ + =0 ...(iii)
R R R
By putting the values of V1 and V2 from equations (i) and (ii) in equation (iii) we get,
Vo
= –8
Vs

„„„„

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