CARRY LOOK-AHEAD ADDER

N-bit adders take inputs {AN, …, A1}, {BN, …, B1}, and carry-in Cin, and compute the sum
{SN, …, S1} and the carry-out of the most significant bit Cout, as shown in Figure.

(Ordinarily, this text calls the least significant bit A0 rather than A1. However, for adders, the notation
developed on subsequent pages is more graceful if column 0 is reserved to handle the carry.) They are
called carry-propagate adders (CPAs) because the carry into ach bit can influence the carry into all
subsequent bits. For example, Figure shows the addition 11112 + 00002 + 0/1, in which each of the sum and
carry bits is influenced by Cin. The simplest design is the carry-ripple adder in which the carry-out of one
bit is simply connected as the carry-in to the next. Faster adders look ahead to predict the carry-out of a
multibit group. This is usually done by computing group PG signals to indicate whether the multibit
group will propagate a carry-in or will generate a carry-out. Long adders use multiple levels of lookahead
structures for even more speed.

Fig: Example of Carry Propagation

Carry Generation and Propagation

This section introduces notation commonly used in describing faster adders. Recall that the P (propagate)
and G ( generate) signals were defined. We can generalize these signals to describe whether a group
spanning bits i…j, inclusive, generate a carry or propagate a carry. A group of bits generates a carry if its
carry-out is true independent of the carryin; it propagates a carry if its carry-out is true when there is a
carry-in. These signals can be defined recursively for i ≥ k > j as

With the base case

In other words, a group generates a carry if the upper (more significant) or the lower portion
generates and the upper portion propagates that carry. The group propagates a carry if both the upper
and lower portions propagate the carry.
 The carry-in must be treated specially. Let us define C0 = Cin and CN = Cout. Then we can define
generate and propagate signals for bit 0 as

Observe that the carry into bit i is the carry-out of bit i–1 and is Ci–1 = Gi–1:0. This is an important
relationship; group generate signals and carries will be used synonymously in the subsequent sections. We
can thus compute the sum for bit i using Equation as

Hence, addition can be reduced to a three-step process:

1. Computing bitwise generate and propagate signals
2. Combining PG signals to determine group generates Gi–1:0 for all N ≥ i ≥ 1
3. Calculating the sums using above Equation.

These steps are illustrated in Figure. The first and third steps are routine, so most of the attention
in the remainder of this section is devoted to alternatives for the group PG logic with different trade-offs
between speed, area, and complexity. Some of the hardware can be shared in the bitwise PG logic, as
shown in Figure.
CARRY-SKIP ADDER

The critical path of CPAs considered so far involves a gate or transistor for each bit of the adder, which
can be slow for large adders. The carry-skip (also called carry-bypass) adder, first proposed by Charles
Babbage in the nineteenth century and used for many years in mechanical calculators, shortens the critical
path by computing the group propagate signals for each carry chain and using this to skip over long carry
ripples. Figure shows a carry skip adder built from 4-bit groups. The rectangles compute the bitwise
propagate and generate signals, and also contain a 4-input AND gate for the propagate signal of the 4-bit
group. The skip multiplexer selects the group carry-in if the group propagate is true or the ripple adder
carry-out otherwise.

The critical path through Figure 11.17 begins with generating a carry from bit 1, and then
propagating it through the remainder of the adder. The carry must ripple through the next three bits, but
then may skip across the next two 4-bit blocks. Finally, it must ripple through the final 4-bit block to
produce the sums.

CARRY-SELECT ADDER

The critical path of the carry-skip and carry-lookahead adders involves calculating the carry into each n-
bit group, and then calculating the sums for each bit within the group based on the carry-in. A standard
logic design technique to accelerate the critical path is to precompute the outputs for both possible inputs,
and then use a multiplexer to select between the two output choices.
The carry-select adder [Bedrij62] shown in Figure does this with a pair of n-bit adders in each group. One
adder calculates the sums assuming a carry-in of 0 while the other calculates the sums assuming a carry-
in of 1. The actual carry triggers a multiplexer that chooses the appropriate sum. The critical path delay is

CARRY SAVE ADDER

The most obvious method of adding k N-bit words is with k – 1 cascaded CPAs as illustrated in Figure for
0001 + 0111 + 1101 + 0010. This approach consumes a large amount of hardware and is slow.

A better technique is to note that a full adder sums three inputs of unit weight and produces a sum output
of unit weight and a carry output of double weight. If N full adders are used in parallel, they can accept
three N-bit input words XN…1, YN…1, and ZN…1, and produce two N-bit output words SN…1 and
CN…1, satisfying X + Y + Z = S + 2C, as shown in Figure. The results correspond to the sums and carries-
out of each adder. This is called carry-save redundant format because the carry outputs are preserved rather
than propagated along the adder. The full adders in this application are sometimes called carry-save adder
(CSA) because they accept three inputs and produce two outputs in carry-save form.

When the carry word C is shifted left by one position (because it has double weight) and added to
the sum word S with an ordinary CPA, the result is X + Y + Z. Alternatively, a fourth input word can be
added to the carrysave redundant result with another row of CSAs, again resulting in a carry-save
redundant result. Such carry-save addition of four numbers is illustrated in Figure, where the underscores
in the carry outputs serve as reminders that the carries must be shifted left one column on account of their
greater weight.
DIVIDER

Manual Division Process

Basic Unit of a Combinational Divider Circuit

The basic unit of a divider circuit has to provide a subtract, a quotient-bit dependent restore and a shift
function for the divisor bit.

The quotient-bit-dependent restore can be realized with a multiplexer and the shift function can be
realized by interconnecting the divisor bit to the next column.

Combinational Array-Divider Circuit

ARITHMETIC LOGIC UNIT (ALU)

An arithmetic logic unit (ALU) is a combinational digital electronic circuit that performs arithmetic and
bitwise operations on integer binary numbers. An ALU is a fundamental building block of many types of
computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics
processing units (GPUs). A single CPU, FPU or GPU may contain multiple ALUs.

Functions
A number of basic arithmetic and bitwise logic functions are commonly supported by ALUs. Basic, general
purpose ALUs typically include these operations in their repertoires:

Arithmetic operations

 Add: A and B are summed and the sum appears at Y and carry-out.
 Add with carry: A, B and carry-in are summed and the sum appears at Y and carry-out.
 Subtract: B is subtracted from A (or vice versa) and the difference appears at Y and carry-out. For this
function, carry-out is effectively a "borrow" indicator. This operation may also be used to compare the
magnitudes of A and B; in such cases the Y output may be ignored by the processor, which is only
interested in the status bits (particularly zero and negative) that result from the operation.
 Subtract with borrow: B is subtracted from A (or vice versa) with borrow (carry-in) and the difference
appears at Y and carry-out (borrow out).
 Two's complement (negate): A (or B) is subtracted from zero and the difference appears at Y.
 Increment: A (or B) is increased by one and the resulting value appears at Y.
 Decrement: A (or B) is decreased by one and the resulting value appears at Y.
 Pass through: all bits of A (or B) appear unmodified at Y. This operation is typically used to determine
the parity of the operand or whether it is zero or negative, or to load the operand into a processor
register.

Bitwise logical operations

 AND: the bitwise AND of A and B appears at Y.
 OR: the bitwise OR of A and B appears at Y.
 Exclusive-OR: the bitwise XOR of A and B appears at Y.
 Ones' complement: all bits of A (or B) are inverted and appear at Y.

Bit shift operations

ALU shift operations cause operand A (or B) to shift left or right (depending on the opcode) and the shifted
operand appears at Y. Simple ALUs typically can shift the operand by only one bit position, whereas more
complex ALUs employ barrel shifters that allow them to shift the operand by an arbitrary number of bits
in one operation. In all single-bit shift operations, the bit shifted out of the operand appears on carry-out;
the value of the bit shifted into the operand depends on the type of shift.

 Arithmetic shift: the operand is treated as a two's complement integer, meaning that the most
significant bit is a "sign" bit and is preserved.
 Logical shift: a logic zero is shifted into the operand. This is used to shift unsigned integers.
 Rotate: the operand is treated as a circular buffer of bits so its least and most significant bits are
effectively adjacent.
 Rotate through carry: the carry bit and operand are collectively treated as a circular buffer of bits.
Example for operation of ALU

Consider an ALU having 4 arithmetic operations and 4 logical operation.

To identify any one of these four logical operations or four arithmetic operations, two control lines are
needed. Also to identify the any one of these two groups- arithmetic or logical, another control line is
needed. So, with the help of three control lines, any one of these eight operations can be identified.

Consider an ALU is having four arithmetic operations. Addition, subtraction, multiplication and division.
Also consider that the ALU is having four logical operations: OR,AND,NOT & EX-OR.
We need three control lines to identify any one of these operations. The input combination of these control
lines are shown below:

Control line S 2 is used to identify the group: logical or arithmetic, ie

S2  0 : arithmetic operation S2  1 : logical operation.

Control lines S 0 and S1 are used to identify any one of the four operations in a group. One possible
combination is given here.

S1 S0 Arithmetic ( S2  0 ) Logical ( S2  1 )

0 0 Addition OR

0 1 Subtraction AND

1 0 Multiplication NOT

1 1 Division EX-OR

Arithmetic Operation data Logical Operation data

I1 = Addition I5 = OR
I2 = Subtraction I6 = AND
I3 = Multiplication I7 = NOT
I4 = Division I8 = EX-OR
As for example, if the contents of controls lines are, 000, then the operation decoder enables the addition
operation and in terms it activates the adder circuit and the addition operation is performed on the data
that are available in storage register A and B. After the completion of the operation, the result is stored in
register C.

BOOTH’S ALGORITHM – MULTIPLIER

The algorithm was invented by Andrew Donald Booth in 1950 while doing research on crystallography at
Birkbeck College in Bloomsbury, London. Traditional hardware multiplication is performed in the same
way multiplication is done by hand:
 Partial products are computed,
 Shifted appropriately, and
 Summed.

This algorithm can be slow if there are many partial products (i.e. many bits) because the output must
wait until each sum is performed. Booth’s algorithm cuts the number of required partial products in half.
This increases the speed by reducing the total number of partial product sums that must take place.

A. Algorithm

The multiplicand and multiplier are placed in the m and Q registers respectively.
A 1 bit register is placed logically to the right of the LSB (least significant bit) Q0 of Q register. This is
denoted by Q-1.

A and Q-1 are initially set to 0.

Control logic checks the two bits Q0 and Q- 1.
 If the two bits are same (00 or 11) then all of the bits of A, Q, Q-1 are shifted 1 bit to the right.
 If they are not the same and if the combination is 10 then the multiplicand is subtracted from A
and
 if the combination is 01 then the multiplicand is added with A.
In both the cases results are stored in A, and after the addition or subtraction operation, A, Q, Q-1 are right
shifted.

The shifting is the arithmetic right shift operation where the leftmost bit namely; An-1 is not only shifted
into An-2 but also remains in An-1. This is to preserve the sign of the number in A and Q. The result of
the multiplication will appear in the A and Q.

Design Of Booth Multiplier

Booth's algorithm can be implemented in many ways. This experiment is designed using a controller and
a data path. The operations on the data in the data path are controlled by the control signal received from
the controller. The data path contains registers to hold multiplier, multiplicand, intermediate results, and
data processing units like ALU, adder/subtractor etc., counter and other combinational units.

Following is the schematic diagram of the Booth's multiplier which multiplies two 4-bit numbers in 2's
complement of this experiment.

Here the adder/subtractor unit is used as data processing unit M, Q, A are 4-bit and Q-1 is a 1- bit register.
 M holds the multiplicand,
 Q holds the multiplier,
 A holds the results of adder/subtractor unit.

The counter is a down counter which counts the number of operations needed for the multiplication. The
data flow in the data path is controlled by the five control signals generated from the controller. These
signals are load (to load data in registers), add (to initiate addition operation), sub (to initiate subtraction
operation), shift (to initiate arithmetic right shift operation), dc (this is to decrement counter).

The controller generates the control signals according to the input received from the data path. Here the
inputs are the least significant Q0 bit of Q register, Q-1 bit and count bit from the down counter.