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Introduction:
Every Op-Amp/OTA has its own DC, transient and AC characteristics e.g.
finite gain, settling time or slew rate and bandwidth. For designs, which are
expected to exhibit stable operation (meet design specifications) over long time
intervals and wide variations in temperature, an OP-Amp/OTA must be tested to
ensure adequate DC and AC characteristics to ensure desired behavior. It is for
these reasons the engineer must understand the limitations these parameters
inflict on actual circuits. This write-up will introduce the Test Engineer to testing
the non ideal properties of op-amps/OTAs.
Laboratory Testing
Objective:
Equipment:
Approach:
PreLab:
Make a table of the expected values and significance of each parameter from
amp simulation.
Your measured op amp/OTA may not achieve the CMRR stated by the
designer due to imbalance in the impedance paths between ac ground and each
input. Assuming 0.1% resistors and ignoring parasitic capacitors what is the
highest possible CMRR achievable? ONLY 54dB!!
A) DC Characteristics
1
Avol .
1 Slope
(1.1)
In the circuits above when measuring the single sided circuit peak-to-
peak the output is limited by either the input common mode range or
by the C. As a result the circuit in Fig. 1.2 must be used to determine
amplifier peak-to- peak output. Avol may also be reconfirmed as along
as Avol is not too large. For example when using the hp4155 gains
greater than 1000 can not be accurately determined.
Fig. 1.2 Input (CMR) and Vout peak-to-peak determination.
Fig. 1.3 Circuit for measurement of input bias currents and input offset voltage.
The design engineer can minimize the effects of output offsets due to
current mismatch by insuring that the effective DC resistance looking back
from both the inverting and noninverting pins is identical. This sets up an
equivalent circuit identical to the IOS measurement set up. Also, keeping R1
and R2 small can be beneficial. The Rs are selected based on the
expected values of I and easily measured values for V o.
B) Large signal (> VBE) transient parameters full Power Response (f p)
the Square Wave used to drive the circuit of Figure 1.4 into slew rate
limiting.
SR
fp ; V pp rated output voltage
2V pp
(1.6)
A( s )
KV
1 A( s ) B
1.7
where A( s ) Avol 1 s show that the circuit of Figure 1.5 can be used to
find fu for large A.
CMRR is the ratio of the differential voltage gain to the common mode
voltage gain. In other words, CMRR is a “figure of merit” comparing the
gain for the differential signals with gain achieved by undesired common–
mode signals. CMMR decreases as a function of frequency due to the
mismatch e.g. capacitive effects, specifically capacitive mismatch in the op
amp as well as desired or parasitic path ways unbalance the impedances
seen looking back from the op amp inputs. Due to the nonlinearity of the
common-mode gain as well as the low amplitude nature, of A cm, the full
common-mode voltage swing must be used to measure CMRR. See Fig.
1.1 to ensure that you do not exceed the VCMR when measuring Acm. A
CMRR test circuit is given in Fig. 1.7. During the test of A cm it is desirable
that an identical; signal be present on both positive and negative inputs of
the op amp.
In this circuit:
R1 R1
R2 R2
and R 2 R 1 so that e cm e s
*The Unity – Gain point is not significantly affected by the feedback if the
close loop gain is much greater than unity. (e.g. Choose R 2 > 100 R1 )
For well-balanced resistors (R1 = R1, R2 = R2), the signal at the two inputs
is essentially a common-mode signal. However, the imbalance of the OP-
AMP produces an output error voltage eo.
From Fig. 1.7:
eo ' R2
Adiff
ei R1
(1.8)
eo
A cm (1.9)
e cm
Adiff eo ' / ei
CMRR
Acm eo / e cm
(1.10)
From (2.8)
R1
ei eo
R2
(1.11)
R2 e s
CMRR (2.12)
R1 eo
or, in dB (decibels)
Where xx is SS and DD respectively for the two power supplies CMRR and
PSRR or YYRR can be measured as shown in Fig. 1.8. DC values for all YYRR
values can be determined using the hp415x parameter analyzer by clamping the
output and measuring the input as each input is swept. For bandwidth
measurements at the critical frequencies of 60 and 120 Hz a small valued
resistor << rout may be used to clamp the output and the resulting voltage
measured. In this case YYRR is defined as follows: