ISSCC2018-27 Visuals PDF

ISSCC
2018
SESSION 27
Power-‐‑Converter Techniques
A 0.22-to-2.4V-Input Fine-Grained Fully Integrated
Rational Buck-Boost SC DC-DC Converter Using
Algorithmic Voltage-Feed-In (AVFI) Topology
Achieving 84.1% Peak Efficiency at 13.2mW/mm2
Yang Jiang1, Man-Kay Law1, Pui-In Mak1 and Rui P. Martins1,2
1State-Key
Laboratory of Analog and Mixed-Signal VLSI
University of Macau, Macao, China
2Instituto Superior Técnico, Universidade de Lisboa, Portugal
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 1 of 52
Outline
• Motivation
• Algorithmic Voltage-Feed-In (AVFI) Topology
 Power Cell Characterization
 Topology Determination
• SC Converter Implementation
 Converter architecture
 Reference-Selective Bootstrapping Driver
• Measurement Results
• Conclusion
Motivation
Wireless Energy VH IoE SoC/SiP
RF Sensor
Harvesters DC Power VDD Processor
Conversion A/D Digital
VL
Requirements: Fully integrated SC converters in bulk CMOS
• Wide conversion range
95
• High efficiency Few-VCR
ηpeak (%)
• Small form factor 85
Multiple-VCR
(≥4)
Fully integrated SC 75
power converter (SCPC) Current S-o-t-A
65
with multiple voltage 10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
conversion ratios (VCRs) Power density (mW/mm2)
Fully Integrated Multiple-VCR SCPCs in bulk CMOS
Fine-grained VCR (FVCR)

95 ISSCC’16 (79) Binary / hybrid topologies
(14) ISSCC’15 High ηpeak, low p-density (≤1mW/mm2)
ηpeak (%)
85 ISSCC’14 (15) (45) MIM / MOM Cfly for low parasitic

ISSCC’16 (17)
(8) JSSC’15 (4)
75
(117) (8)
(6)
(Number of VCR in bracket )
65
-3 -2 -1 0 1 2 3 4
10 10 10 10 10 10 10 10
Power density (mW/mm2)
95 ISSCC’16 (79)
(14) ISSCC’15
ηpeak (%)
85 ISSCC’14 (15) (45) Dickson Topology

ISSCC’16 (17)
Optimal parasitic loss
(8) JSSC’15 (4)
75 Limited realizable VCRs
(117) (8)
(6)
65
-3 -2 -1 0 1 2 3 4
10 10 10 10 10 10 10 10
Target:
95 ISSCC’16 (79) • Rational FVCR
(14) ISSCC’15 • Optimal losses:
ηpeak (%)
85 ISSCC’14 (15) (45) Q-conduction (RSSL)

ISSCC’16 (17) Parasitic
(8) JSSC’15 (4)
75
(117) (8)
(6)
65
-3 -2 -1 0 1 2 3 4
10 10 10 10 10 10 10 10
Outline
• Motivation
 Power Cell Characterization
 Topology Determination
• Conclusion
Conventional Topology Based Rational FVCR Design
 Hybrid topology: suboptimal parasitic loss & RSSL
Integer VCR Fractional VCR Rational VCR
Hybrid
1:N Y:X X
N+
(Dickson)
Y
(S-P)
(Series-Parallel) (Dickson-SP)
 Binary Recursive and Negator topologies: suboptimal parasitic loss
Cell Extraction from Existing Dickson Topologies
• ∆VCB: VIN or VOUT − VIN

• Q-conduction path:
 Optimal bottom plate switching (∆VCB)
Top-in-Top-out (TT)
 Limited VCR of 1:N, (N-1):N Bottom-in-Bottom-out (BB)
Dickson Cell (DC) → Charge-path Folding Cell (QFC)
Dickson Cell (DC) (boost) Q-path Folding Cell (QFC) (boost)

Si,I Si,O VIN VOUT VIN Si,O Si,I VOUT
QC,O QC,I
+ + Terminal + +
− − swapping − −
QC,I QC,O
VIN VSS Si,I Si,O Si,I VSS VIN Si,O
TT BB BT TB
 Weak flexibility of • ∆VCB: Internal-node dep.
voltage conversion • Q-path: folded
Bottom-in-Top-out (BT)
Top-in-Bottom-out (TB)
Proposed Cell Based Topology Design Concept
TT BB  Cell by cell loss optimization
Si,I Si,O VIN VOUT
QC,I QC,O
 w/o constraint from existing topo.
DC + +
− −
QC,I QC,O Proposed topology
VIN VSS Si,I Si,O
Algorithmic
DC S1,O DC S2,O Sn-1,O DC
combination …
BT TB QFC QFC QFC
VIN Si,O Si,I VOUT
QC,O QC,I
QFC + + • Rational FVCR implement
− −
QC,I QC,O • Optimal RSSL and ∆VCB
Si,I VSS VIN Si,O
System Parameters (boost): bi & mi
Q-path folding bi = 0 bi = 1 VOUT feed-in
coeff.: mi (VOUTFI) coeff.: bi
Si,O = Si,I + VIN − biVOUT

DC: mi = 0
bi = 0: Si,O = Si,I + VIN

bi = 1: Si,O = Si,I + VIN − VOUT
Unique cell
QFC: mi = 1 configuration
by bi & mi
Topology Model for AVOUTFI (boost)
Si,O = Si,I + VIN – biVOUT Algorithmic VOUT feed-in (AVOUTFI) Topology Model
VOUT
bi
-
Si,I Si,O
VIN
Algorithmic Model
VOUT 1+n
=
VIN 1 + Σb1~(n-1)
Algorithmic VOUT feed-in (AVOUTFI) Topology Model
Shortcut to
verify min. RSSL
VOUT 1+n
=
Optimal RSSL for VIN 1 + Σb1~(n-1)
AVFI topology
DC QFC
TT BB BT TB
Algorithm for coefficient bi & mi
C1 C2 Cn-1 Cn Topology
VOUT
b1 b2 bn-1 implementation
- - - with optimal
… parasitic loss?
VIN
DC/QFC DC/QFC DC/QFC DC/QFC
(m1) (m2) (mn-1) (mn)
n-stage AVOUTFI Topology Model
Coefficient Algorithm for bi
Level Bounded Rule (LBR) (boost): S1~(n-1),O (VSS, VOUT).
Applying the LBR.

0 < Si,O < VOUT
bi algorithm
Derivation for mi
(Boost)
C1 implementation C2~n implementation depends

solely depends on b1. on both b2~n-1 & m2~n.
(identical for m1 = 0 or 1) → Explore mi algorithm by
greedy selection.
Derivation for mi
Coefficient Algorithm for mi
mi algorithm
• Cell-to-cell Q-transfer of
CTOP-CTOP / CBOT-CBOT
Summary: Proposed AVOUTFI Topology (Boost)
Summary: Proposed AVINFI Topology (Buck)
Summary: Proposed AVFI Topology (Buck-Boost)
Q-Conduction Loss Comparison
(Proposed) (Existed) (Existed)
Parasitic Loss Comparison
(Proposed) (Existed) (Existed)
Specific Topology Comparison
3:5 4:3
Liu ISSCC’15 (Hybrid) AVFI Lu ISSCC’15 (SP) AVFI
Q 2Q C1 C2 C3 C4 Q C1 C2 C3 C4 Q C1 C2 C3 Q C1 C2 C3
VOUT VOUT VIN VIN
Φ1 V
Φ1 VIN Φ1 VIN OUT Φ1 VOUT
VSS VSS VSS
VOUT
VOUT VOUT Φ2 VIN
Φ2 VIN Φ2 VIN Φ2 VOUT
VSS VSS VSS
MPAR = 0.63 MPAR ≈ 0.37 MPAR ≈ 0.219 MPAR ≈ 0.047
Le Q C1 C2 C3 C4 Teh Q 2Q C1 C2 C3
AVFI Q C1 C2 C3 C4
VIN VIN VIN
ISSCC’13 Φ1 ISSCC’16 Φ1 VOUT Φ1 VOUT
5:2 (Hybrid) VOUT (Custom.) VSS VSS
VOUT VIN
Φ2 Φ2 VOUT Φ2 VOUT
VSS VSS VSS
MPAR = 0.176 MPAR = 0.104 MPAR = 0.08
Simulation Results & Comparison
η (%)
(Proposed)
(Existed)
0.2V < VIN < 2.3V, VOUT = 1V, Iload = 20mA RSSL: AVFI = NSC = RSC < S-P
CBot-par = 8%, Acap = 1mm2 RPAR: AVFI < NSC ≤ RSC < S-P
Outline
• Motivation
 Topology Generation
 Coefficients Selection
• Conclusion
Converter Overview
• 10 main + 10 auxiliary cells • Dual-branch interleaved

• VCRs: 11 buck + 13 boost • 25MHz clock pulse-skipping modulation
Cells Partitioning Mode Summary
2:1 1:2 1:1 3:2 2:3 1:3 4:3 3:4 1:4 5:3 5:4 4:5
1C 2C 3C 3:5 2:5 1:5
MC<1> MC<1~2> MC<1~3>
4C
MC<3~4> MC<1~4>
MC<10> MC<4~6>
VIN VOUT
AC<1> MC<5~8>
MC<9~10> MC<7~9>
AC<10> AC<1~10> MC<10> MC<9~10>
AC<1~10> AC<1~10>
5C 6C
• 7 partition modes for MC<1~5> 10C
MC<1~6>
24 VCRs
• Full cap. utilization MC<6~10> MC<1~10>
MC<7~10>
• Reduction of required AC<1~5> AC<1~10>
no. of cell 60 → 20 AC<6~10> AC<1~10>
7:4 7:5
6:5 5:6 1:6 7:6 1:7 11:10 10:11
Power Cell Implementation
• Top plate P/N switches are enabled in buck/boost, respectively.

• Low voltage switches ensured by bounded top/bottom voltage domains.
Power Switch Driving Issue
• ST3 driving challenge ― no fixed high/low reference terminal
Adaptive Driving Behaviors for ST3 (Buck)
Reference-Selective Bootstrapping Driver (RSBD) Oprt.
RSBD Three-state Dual Phase Operations for ST3
States Buck  VIN > VOUT (VDD) Boost  VIN < VOUT (VDD) Disable
(for T3) (en = 1, lv = 0) (en = 1, lv = 1) (en = 0)
SP VGP,on = Vpass − VDD VGP,off = VDD (buck)
Φ1 VGP,dis = VIN
SN VGN,off = VDD VGN,on = Vpass + VDD
VGN,dis = VDD
 Vn if Vn > Vn+1
SP VGP,off =  VGP,off = VDD
 Vn+1 if Vn+1 > Vn (boost)
Φ2
 Vn if Vn < Vn+1 VGP,dis = VDD
SN VGN,off = VDD VGN,off = 
 Vn+1 if Vn+1 < Vn VGN,dis = VSS
Vpass VDD < Vpass < VIN_MAX VIN_MIN < Vpass < VDD --
• 2 enables states (buck/boost) + 1 disable state.
• Dual phase (Ф1,2) ST3 on/off in enable states.
Proposed RSBD Circuit (for ST3)
RSBD for ST3 (Buck): Ref. Selection for ΦOFF Ctrl.
RSBD for ST3 (Buck): ФOFF Ctrl.
RSBD for ST3 (Buck): Int. Driving for Vpass Sensing
RSBD for ST3 (Buck): ΦON Ctrl.
RSBD for ST3 (Buck): Φdis Ctrl.
enP enP
Buck Φdis
enN enN V VIN
VGP,dis
enP enP
Vi+1 Vi
VGP0 enN enN VOUT
0°
Vi_0 Vi+1_0 clk0 clk180
enP enP VGP180

Ci_0 Ci+1_0
Vi_180 Vi_0
Φdis ctrl. VGN0 VGN180
VGN VGP clk0 clk180 = VDD
en VDDH
lv
en enN enN
lv lv
VDD VIN
Outline
• Motivation
• Conclusion
Chip Implementation
Measured Conversion Efficiency over VIN (VOUT = 1V)
• Similar performance for VIN = 0.26 ~ 2.4V @ VOUT = 1.2V,

and VIN = 0.22 ~ 2.15V @ VOUT = 0.85V.
Measured Efficiency over Output Power Range
Buck Boost
90
11:10 7:6 5:4
3:2 80
80
60 3:5 1:2 4:5
η (%)
10:11 2:3 5:6
η (%)
70
6:5 7:5 4:3 80 2:5 1:3
5:3 2:1 40 3:4
5:3 1:1 75 1:4
60 1:5
7:4 70 1:6
50 60 70 80 20
2:1 1:7
50
0 10 20 30 40 0 10 20 30
POUT (mW) POUT (mW)
• Max. POUT > 80mW with buck 2:1
Measured Load Transient Waveforms
Performance Summary and Comparison
D. Lutz C. K. Teh M. Saadat X. Hua J. Jiang
This work
ISSCC'16 ISSCC'16 ASSCC'15 CICC'15 JSSC'17
Technology 65nm CMOS 0.35μm HVCMOS 65nm CMOS 0.25μm CMOS 65nm CMOS 130nm CMOS
Conv. type Buck-Boost Buck-Boost Buck-Boost Buck-Boost Buck-Boost Buck
No. of VCR 11 buck + 13 boost 8 buck + 9 boost 5 buck + 1 boost 4 buck + 4 boost 3 buck + 3 boost 6 buck
Integrated Cfly MOS + MIM MIM MOS + off-chip 1μF MIM N/R Off-chip 4μF
VIN [V] 0.22 ~ 2.4 2 ~ 13 0.85 ~ 3.6 0.6 ~ 2.4 0.5 ~ 3.3 1.6 ~ 3.3
VOUT [V] 0.85 ~ 1.2 5 0.1 ~ 1.9 1.2 ~ 1.5 1 0.5 ~ 3
IOUT_MAX [mA] 80.1 4 10 0.1 0.0033 120
Buck: 84.1 Buck: 81.5 Buck: 95.8
ηpeak [%] 76 70.4 91
Boost: 83.2 Boost: 70.9 Boost: 90.5
P-den@ηpeak Buck: 13.2 *Buck: 0.96
2 N/R *0.062 *0.0069 N/A
[mW/mm ] Boost: 10.2 *Boost: 0.15
*
Estimated from the corresponding literature
D. Lutz C. K. Teh M. Saadat X. Hua J. Jiang
This work
ISSCC'16 ISSCC'16 ASSCC'15 CICC'15 JSSC'17
Technology 65nm CMOS 0.35μm HVCMOS 65nm CMOS 0.25μm CMOS 65nm CMOS 130nm CMOS
Conv. type Buck-Boost Buck-Boost Buck-Boost Buck-Boost Buck-Boost Buck
No. of VCR 11 buck + 13 boost 8 buck + 9 boost 5 buck + 1 boost 4 buck + 4 boost 3 buck + 3 boost 6 buck
Integrated Cfly MOS + MIM MIM MOS + off-chip 1μF MIM N/R Off-chip 4μF
VIN [V] 0.22 ~ 2.4 2 ~ 13 0.85 ~ 3.6 0.6 ~ 2.4 0.5 ~ 3.3 1.6 ~ 3.3
VOUT [V] 0.85 ~ 1.2 5 0.1 ~ 1.9 1.2 ~ 1.5 1 0.5 ~ 3
IOUT_MAX [mA] 80.1 4 10 0.1 0.0033 120
Buck: 84.1 Buck: 81.5 Buck: 95.8
ηpeak [%] 76 70.4 91
Boost: 83.2 Boost: 70.9 Boost: 90.5
P-den@ηpeak Buck: 13.2 *Buck: 0.96
2 N/R *0.062 *0.0069 N/A
[mW/mm ] Boost: 10.2 *Boost: 0.15
*
Estimated from the corresponding literature
Benchmarking with Fully Int. SCPCs (No. of VCR ≥ 4)
SC DC-DC w/ VCR ≥ 4 in bulk CMOS
100 Bulk CMOS
(Number of VCR labeled in bracket)
Buck-Boost
95 Buck Boost
(79) Ferro-cap
(4)
90 HD-MIM
(14) (45) This Work Buck-Boost
85 (16) x13 (24)
(4) HD-MIM + TriGate
(17) Buck
80 [Lutz ISSCC’16] (4) HD-MIM
(4) Ferro-cap
75 (8) Buck
(117) (5) (8) SOI
(4) SOI
70 (6) Buck
Boost
65
-3 -2 -1 0 1 2 3 4
10 10 10 10 10 10 10 10
Power density @ ηpeak (mW/mm2)
Outline
• Motivation
• Conclusion
Conclusion
 AVFI topology
• Systematic topology design technique
• Rational FVCRs
• Optimal RSSL & ∆VCB
 MC + AC partitionable power stage

• Reduced complexity
• Full capacitor utilization
 RSBD switch driver

• Effective power-switch on/off over high operating dynamics
Acknowledgement
 Macao Science and Technology Development Fund (FDCT)
 Multi-Year Research Grant of University of Macau
Thank you for your attention!
A 10MHz Time-Domain-Controlled Current-Mode
Buck Converter with 8.5% to 93% Switching
Duty Cycle
Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, and Changsik Yoo
Hanyang University, Seoul, Korea
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 1 of 27
Contents
• Introduction
• Time-Domain-Controlled Current Mode Buck Converter
• Implementation Details
• Experimental Results
• Conclusion
© 2018 IEEE
Contents
• Introduction
• Conclusion
© 2018 IEEE
Current Mode Buck Converter – Conventional
IL
① Fast transient response
VIN MP VSW VOUT
L ② Simple freq. compensation
IL RL  Type-II compensation network
COUT
Gate
Driver MN ③  Still large silicon area and power
Ri
③ Inductor current sensor
 Sensitive to noise
VPWM
VRAMP  Switching freq. limited
① ④
_
④ Sub-harmonic oscillation
Q R  Slope compensation required
VC
S VCLK EA
⑤ R1
② VREF ⑤ Limited duty cycle due to
C1 comparator delay
© 2018 IEEE
Motivation of Time-Domain Current-Mode Control
 Fast transient response

 Keep current-mode control 
 Freq. compensation with large area and power
 Freq. compensation without amplifier and passive RC 
 Current sensor
 With time-domain circuit (voltage-controlled oscillator) 
 Sub-harmonic oscillation
 No sub-harmonic oscillation even without slope compensation 
 Limited duty cycle due to comparator delay
 No comparator and wide range of output 
© 2018 IEEE
Contents
• Introduction
• Conclusion
© 2018 IEEE
Proposed Architecture
• Time-domain control
– Voltage information converted to the
phases of CLKSET and CLKRST
– Voltage-controlled oscillator (VCO)
 Output phase = control voltage
– Voltage-controlled delay line (VCDL)
 Output phase ∝ control voltage
+ −
( )=
− −
=
+ ( − )
– Phase difference between CLKSET and

CLKRST determines duty cycle.
© 2018 IEEE
Inductor Current Sensing
IL
VIN MP VSW VOUT
L
COUT
+ Gate RL
MN
− Driver
VPWM
KVCO2
CLKRST
( RST)
VCO2
PD VREF
VCDL KVCO1
CLKSET
( SET)
KVCDL
VCO1
-1
• With series-R • VCO2

– Reduced power efficiency + −
( )= ∝
• Current-mirror based sensor
– Less power and no fSW limitation
© 2018 IEEE
– fSW limited by feedback loop
Frequency Compensation
• Type-II compensation with high- • Type-II compensation with only

BW amplifier and RC time-domain circuits
– R1; proportional, C1; integral – VCDL; proportional, VCO; integral
– High power and large silicon area – Less power and silicon area
© 2018 IEEE
Voltage Comparison and PWM Signal Generation
• Voltage comparator • Phase detector w/ negligible delay

– Duty cycle limited by its delay – Phase of CLKRST ∝ inductor current
– Phase of CLKSET ∝ type-II
compensated error voltage
© 2018 IEEE
Operation Waveforms
• Conventional • Proposed
© 2018 IEEE
Sub-Harmonic Oscillation with Current-Mode Control
• Conventional IL
Ipeak
−
∆ = ∆ = ∆
a IIND,orig
Current b S2
perturbation
∆ = ∆ =− ∆ at t=0 S1 IIND,pert
IL(0)
∆ >∆ if duty > 50% Current
IL(Tsw) perturbation
t
Sub-harmonic oscillation at t=TSW
Tsw
© 2018 IEEE
Sub-Harmonic Oscillation with Current-Mode Control
• Proposed time-domain
∆ = ∆
= + − ∆
∆ = ∆
= − ∆
∆ <∆ for all duty
No sub-harmonic oscillation
© 2018 IEEE
Contents
• Introduction
• Conclusion
© 2018 IEEE
Fully Differential Implementation
IL
VIN MP VSW VOUT
L
COUT
Gate RL
Driver MN
VPWM
KVCO2
CLKRST
VCO2
PD VREF
VCDL KVCO1
CLKSET
KVCDL
VCO1
-1
• Fully differential (latency reduced)

• VCO  GM + CCO
• VCDL  GM + CCDL
© 2018 IEEE
Linearity of VCO Gain
• For inductor current sensing,
constant VCO gain is desired.
• GMP,GMS,GMI  level shifter +
source degeneration
© 2018 IEEE
Input Offset of GM
• Offset of GMS and GMI  VOUT error

• Offset of GMP  compensated by
feedback loop
• Chopping applied to GMS and GMI
© 2018 IEEE
Phase Detector
• PD = edge detector + SR-latch + cycle slip detector
– Cycle slip detector
 Phase difference < 0  Duty = 0%
 Phase difference > 2π  Duty = 100%
SET
PWM
RST
SET RST
[S. J. Kim et al., ISSCC 2015]
© 2018 IEEE
Contents
• Introduction
• Conclusion
© 2018 IEEE
Chip Microphotograph
Process 65-nm CMOS

① PMOS power transistor
Controller 0.036-mm2
② NMOS power transistor
③ Time-domain current-mode controller COUT 4.7-μF
④ Gate driver L 220-nH
© 2018 IEEE
Steady State Waveforms
VOUT=1V
VPWM 100ns
57ns Duty=57%
IIND
Input 1.8-V
VOUT=1.69V
Output 0.15~1.69-V
VPWM 100ns
Duty cycle 8.5~93-%
Max. load current 0.6-A 93ns Duty=93%

IIND
fSW 10-MHz
© 2018 IEEE
Load Transients
• 3.5-μs settling time for up/down step change of IOUT

© 2018 IEEE
Reference Tracking
• 3-μs/3.5-μs tracking time for up/down step change of VREF

© 2018 IEEE
Power Efficiency
• 94.9% peak efficiency (VIN=1.8V, VOUT=1.5V, fSW=10MHz)
© 2018 IEEE
Performance Comparison
[1] VLSI 2012 [2] JSSC 2011 [3] JSSC 2015 This work
Technology 350-nm CMOS 350-nm CMOS 65-nm CMOS 65-nm CMOS
Voltage-domain Voltage-domain Time-domain Time-domain
Control scheme
current mode current mode voltage mode current mode
VIN (V) 2.7~3.6 2.7~4.2 1.8 1.8
VOUT (V) 2 0.5~2.6 0.6~1.5 0.15~1.69
Maximum IOUT (A) 0.6 0.5 0.6 0.6
Switching frequency (MHz) 1 5 11~25 10
Inductor (μH) 4.7 1 0.22 0.22
Capacitor (μF) 10 4.7 4.7 4.7
Die 3.8 0.54 5 2.118
Area (mm2)
Controller 0.217* 0.148* 0.037 0.036
Peak efficiency (%) 93 91 94 94.9
Load step 400mA / N.A. 200mA / N.A. 500mA / N.A. 480mA / 0.1μs
Load transient
Up 6 6 3 3.5
settling time (μs)
Down 12 8 3.5 3.5
Dynamic voltage Up 3
N.A. N.A. N.A.
scaling (μs) Down 3.5
*Controller size is estimated from the chip microphotograph
© 2018 IEEE
Contents
• Introduction
• Conclusion
© 2018 IEEE
Conclusion
• Time-domain-controlled current-mode buck converter proposed
– Time-domain PI-compensator
 Smaller silicon area and power consumption
– Inductor current sensing with VCO
 No resistor and wideband amplifier
 No sub-harmonic oscillation
– PWM signal generation with phase detector
 Wide range of duty cycle and thus wide range of output voltage
© 2018 IEEE
An 86% Efficiency SIMO DC-DC Converter
with One Boost, One Buck, and a Floating
Output Voltage for Car-Radio
A. Salimath*, E. Bonizzoni*, E. Botti#, G. Gonano#,

P. Cacciagrano#, D. Brambilla#, T. Barbieri#, F. Maloberti*
*University
of Pavia, Pavia, Italy
#STMicroelectronics, Cornaredo (MI), Italy
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 1 of 43
Outline
 Introduction
 Design Targets
 Proposed Architecture
 Experimental Results
 Conclusion
Automotive class-D audio amplifier system
Vbat Vboost
n-channels
VfloatH Vboost
Vbat
VfloatL
Power
Vreg-low Reg Vbat
Management
Level 0
VfloatH
Shift HS Driver Npow-HS
High
Speaker
Analog VPWM Lf
Digital
Processing
Core
and PWM VReg-low Cf
Level
VfloatL
Shift LS Driver
Npow-LS
Low
Automotive class-D audio amplifier system
Vbat Vboost
n-channels
VfloatH Vboost
Vbat
VfloatL
Power
Vreg-low Reg Vbat
Management
Level 0
VfloatH
Shift HS Driver Npow-HS
High
Speaker
Analog VPWM Lf
Digital
Processing
Core
and PWM VReg-low Cf
Level
VfloatL
Shift LS Driver
Npow-LS
Low
Power management in state-of-the-art car-radio
100  Supplies generated by linear
Datasheet- FDA801
regulators*.
80  Increased pin-count and BoM.
Efficiency (%)
 PDiss and efficiency of the

60
system in low power output
40 condition are determined by
the supply generator.
20  Scope to reduce PDiss in the
Vdd= 25V grey region by using a supply
Vdd= 14.4V
generator with high efficiency.
0 10 20 30 40 ….. 80
Total Output Power (W)
* M. Høyerby et al., JSSC 2016
Battery profile in a car-radio
 Requirement of voltage
regulation across large battery
voltages (4-40V).
 Fast response of the supply
generator to crank and dump
conditions as well as battery
step-up.
 Battery voltage tracking
supplies required for channel
drivers.
 Requirement of high V/I
protection circuits.
Load current profile of the channel drivers in car-radio
4 Ch
2 Ch
1 Ch
Q
Iboost & Ireg-low (mA)

O/p current profile of
80
channel driver
Average:
IAvg= 80 mA
IAvg= 40 mA 40
IAvg= 20 mA
20
IQ= 2 mA
2
TSW time 1 2 4
# of Channels
TSW= Switching period of class-D amplifier
Design target
Switching frequency of the SIMO dc-dc converter
 Switching SIMO at 0.3-0.5MHz contributes to switching-noise in MF-AM band.

 Switching SIMO at 2-2.4MHz prevents switching-noise in AM band.
Design specifications
Input battery voltage
4-40V Remarks
(Vbat)
Regulated output Vboost Vreg-low VfloatH−VfloatL 1. (V
floatH−VfloatL) requires
voltages Vbat+6.5V 4.5V 1.8V regulation across Vbat/2.
Load currents at Iboost Ireg-low Ifloat 2. VfloatH and VfloatL track

regulated outputs Vbat/2 differentially.
2-80mA 2-80mA 30mA
3. Vboost tracks Vbat.
Switching frequency
2-2.4MHz 4. Vreg-low is regulated wrt
(FSW)
ground.
Target Efficiency >80%
Proposed SIMO Architecture
Proposed schematic of the power stage
Implementation of the proposed power stage
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
Vreg-low +∆2 with sync-sw
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
Implementation of the floating output
9
VfloatH Vbat/2 VfloatL
8
Voltage
1.6V 1.8V
7
6
Linear Regulation
5
T1 T2
SIMO ON
ILinear Reg (mA)

50
ILinear Reg High
0
ILinear Reg Low
-50
T1 T2
Time
Schematic of the Regulated Floating Dual-
Slope (RFDS) driver
Slope (RFDS) driver
Slope (RFDS) driver
Slope (RFDS) driver
Slope (RFDS) driver
Error processor in the proposed SIMO converter
* Error Matrix as in Belloni et. al, ISSCC 2008.

** Type-3 Compensator.
Error processor in the proposed SIMO converter
A B
* Error Matrix as in Belloni et. al, ISSCC 2008.

** Type-3 Compensator.
Experimental Results
Micrograph of the SIMO converter
 110-nm BCD Process

 Active Area: 2.5mm2
 External Inductor: 10μH
 External Capacitors: 10μF
Unique startup sequence of the SIMO converter
Boost Only ON SIMO ON Vboost
6.5V
Vbat =14.4V
1.6V VfloatH 1.8V

Turn ON VCM,float VfloatL
VfloatH-VfloatL Vreg-low
4.5V
SIMO converter output response to battery transients
Steady-state performance of the SIMO converter
Steady-state performance of the SIMO converter
Load transient performance of the SIMO converter
Load Transient= 0.16 mV/mA

Cross Regulation= 0.13 mV/mA
Power efficiency of the SIMO converter
Peak Efficiency= 86%
Impact of the SIMO converter
on car-radio performance
 What is the impact of SIMO converter (switching regulator) on

the DR of a car-radio system?
 What is the effective reduction in the system power dissipation

using this SIMO converter in comparison with conventional
linear regulators?
Car-radio performance with SIMO converter
Vbat=14.4 V, FIn= 1kHz, Fs= 192kHz

Car-radio performance with SIMO converter
Vbat=14.4 V, FIn= 1kHz, Fs= 192kHz

Performance comparison of SIMO converters
Parameter ISSCC14 [3] ISSCC15 [4] ISSCC11 [5] This Work
Process 0.35-μm CMOS 0.35-μm BCD 0.25-μm CMOS 110-nm BCD
3 Outputs:
Outputs/Topology 4 Buck 10 Buck 1 Buck, 1 Boost
Buck/Boost/Floating
Supply Voltage (V) 2.7-5 5 2.5-5 4-40
Inductor, Capacitors L=4.7μH, CLi=10μF L=10μH, CLi=10μF L=2.2μH, Cli=20μF L=10μH, CLi=10μF
Switching Frequency 1MHz 1.2MHz 2MHz 2.4MHz
Output Ripple <30mV <40mV <80mV <25mV
Line Reg. (mV/V) NA NA NA 4-16.2
Load Tran. (mV/mA) 0.16 0.17 1.5 0.16
Cross. Reg. (mV/mA) 0.04 0.1 NA 0.13
Peak Efficiency 87% 88.7% 90% 86%
Max. Output Power (W) 2.16 2.5 (estimation) 2.5 2.8
Active Area (mm2) 5.4 11.75 7.54 2.5
Automotive Class No No No Yes
Conclusion
 An automotive-class SIMO dc-dc converter with a battery -
tracking floating, boost and a ground referred buck outputs
is introduced.
 The SIMO converter is integrated with a state-of-the-art car-
radio.
 The converter offers an efficiency exceeding 80% at the
nominal battery voltages driving up to 4 audio channels.
 The performance of the car-radio with SIMO dc-dc converter
and its advantages are presented.
Thank You
A 97% High-Efficiency 6μs Fast-Recovery-
Time Buck-Based Step-Up/Down Converter
with Embedded 1/2 and 3/2 Charge-Pumps
for Li-Ion Battery Management
Min-Woo Ko1, Ki-Duk Kim1, Young-Jin Woo2, Se-Un Shin1, Hyun-Ki Han,
Yeunhee Huh1, Gyeong_Gu Kang1, Jeong-Hyun Cho1, Sang-Jin Lim1, Se-
Hong Park1, Hyung-Min Lee3
and Gyu-Hyeong Cho1
1Korea Advanced Institute of Science and Technology, Daejeon, Korea
2Siliconworks, Daejeon, Korea
3Korea University, Seoul, Korea
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 1 of 28
Outline
 Motivation
 Proposed Step-Up/Down DC-DC Converter

 Fast-response step-Up/Down Converter (FUDC)
 Overall Architecture
 Measurement Results
 Conclusion
Motivation
Energy density characteristic of various batteries
 Li-Ion Battery shows the highest energy density

 Suitable for mobile devices application
Motivation
Discharging characteristic of a Li-Ion battery
4.2
4.0
3.8 Required Regulated
Voltage (V) Supply Voltage
3.6
3.4
3.2 Step-Down Step-Up
3.0 Mode Mode Application
2.8 Circuits
2.6
Li-ion
Battery
100 80 60 40
State-Of-Charge (%)
20 0 [Ref : Ju, ISSCC 2017]
 The voltage of Li-Ion battery decreases with time

 A step-up/down DC-DC converter is required
Prior Arts
[ Zheng, ISSCC 2010 ] < Pros >
DTS
 Well-known buck-
VX VY VOUT
boost topology
VBAT D'TS
S1 S3
 Simple buck/boost
VBAT S2 S4 b) Pseudo-buck mode mode control
D'TS
< Cons >
VBAT DTS  Poor efficiency
a) Conventional non-inverting buck- (60%~90%)
boost converter
c) Pseudo-boost mode
 Slow transient
Prior Arts
[ Ju, ISSCC 2017 ] < Pros >
DTS
 Superior efficiency
VX VOUT
(86%~96%)
VBAT D'TS
S1
S3  Suitable for Li-Ion
VBAT S2 b) Step-down mode battery application
+ VBAT -
S4
D'TS DTS < Cons >
VBAT  Voltage stress
a) Flying-Capacitor Buck-Boost D'TS problem
(FCBB)
c) Step-up mode
 Slow transient
Key Concept
Step-up
VX VOUT
Step-down
3VBAT/2 VBAT VBAT/2
 Buck-operation by using dependent voltage sources
 Fast-response step-Up/Down Converter (FUDC)

Proposed Step-Up/Down DC-DC Converter
VX VOUT
S1
CF1 S5
S2
VBAT
CF2
S4 S3
S7 S6
 Charge-pump + buck converter
Operation Principles
Step-down mode : Charging-phase
ɸc(charging) T
S1 VX=VBAT VOUT ɸc ɸd
+
1/2VBAT S5 DT
VBAT - +
S2 1/2VBAT IL
- VBAT VOUT
S4 S3
S7 S6 VBAT/2
VX,VOUT
 Inductor : Energized
 Flying capacitors : Charged up to ½ VBAT respectively

Step-down mode : Down-phase
ɸd(down) T
VX=VBAT/2 VOUT ɸc ɸd
S1 +
1/2VBAT S5 DT
VBAT - +
S2 1/2VBAT IL
- VBAT VOUT
S4 S3
S7 S6 VBAT/2
VX,VOUT
 Inductor : De-energized
 Flying capacitors : Discharged

Step-up mode : Charging-phase
ɸc(charging) T
S1 VX=VBAT VOUT ɸc ɸu
+
1/2VBAT S5 DT
VBAT - +
S2 1/2VBAT 3VBAT/2 IL VOUT
-
S4 S3 VBAT
S7 S6
VX,VOUT
 Inductor : De-energized
 Flying capacitors : Charged up to ½ VBAT respectively

Step-up mode : Up-phase
ɸu(up) T
VX= 3VBAT/2 VOUT ɸc ɸu
S1 +
1/2VBAT S5 DT
VBAT - +
S2 1/2VBAT 3VBAT/2 IL VOUT
-
S4 S3
S7 S6
VX,VOUT
 Inductor : Energized
 Flying capacitors : Discharged

Transfer Function
topology Mode Gd0 Wo Q Wz
Step- ′ ′  Control to Output

Up ′
′
conventional ( )
Step- 1
∞

Down ( ( ) )
Step-
−( )  Buck-like feature in
Up −
Proposed both step-up and
Step- step-down mode
Down +
Switch Size Optimization
IL ICF1, ICF2
T
ILT/4 when D is 0.5
ɸd S1 IL
CF1 βR
S
0.5T
VBAT ICF1 2
IL t
CF2
ICF2
IL
βR βR IS1
S7 S6
αR IS1 t
IL
DT
ɸc S5 ICF1, ICF2 t
CF1
βR
VBAT IL IL
CF2 ILT when D is 1
IS1
S4 βR
S7 S6 t
 Total amount of charge flowing through each switch is

considered
Switch Size Optimization
Normalized effective resistance
REFF Li-ion battery operating range
2R
Size optimization
0.75 0.85 0.95 1.05 1.15 1.25

Conversion ratio [V/V]
Overall Architecture
BS VX VOUT
ɸ1
Cf1 ɸ5  Hysteretic control
VBAT
ɸ2 Cf2
ɸ4 ɸ3
 VFB :
ɸ7 ɸ6 output voltage
ɸ1~7 Gm information +
current ripples
A
DTC Pi
P
Control VFB information
&Gate d Edge Detector VOUT_D
Pu VREF
Driver Logic Differentiator
CLK
Reset Controller
Detailed Operation
Step-down mode BS VX VOUT
RESET RESET RESET ɸ1

Cf1 ɸ5
CLK CLK CLK VBAT

ɸ2 Cf2
IL ɸc ɸd ɸ4 ɸ3
ɸ7 ɸ6
ɸ1~7 Gm
A
DTC Pi Control VFB
VBAT P VOUT_D
VX 1/2VBAT
&Gate d
Driver
Pu
Logic
Edge Detector
VREF
Differentiator
CLK
Reset Controller
VFB
Upper Boundary  Reference boundary :
VOUT_D VREF VFB Charging-phase
VOUT_D
VREF  Upper boundary :
Down-phase
Detailed Operation
Step-up mode BS VX VOUT
RESET RESET RESET ɸ1

Cf1 ɸ5
CLK CLK CLK VBAT

ɸ2 Cf2
IL ɸc ɸu ɸ4 ɸ3
ɸ7 ɸ6
ɸ1~7 Gm
3/2VBAT DTC Pi Control VFB

A
VBAT P VOUT_D
VX &Gate d
Driver
Pu
Logic
Edge Detector
VREF
Differentiator
CLK
Reset Controller
VFB  Reference boundary :

VOUT_D Charging-phase
VOUT_D VREF VFB
VREF  Lower boundary :
Lower Boundary
Up-phase
Detailed Operation
Transition mode ( VBAT ≈ VOUT ) BS VX VOUT
RESET RESET ɸ1
Cf1 ɸ5
CLK CLK CLK VBAT

ɸ2 Cf2
IL ɸ4 ɸ3
ɸ7 ɸ6
ɸ1~7 Gm
A
3/2VBAT DTC Pi
P
Control VFB
VX VBAT &Gate d
Driver
Pu
Logic
Edge Detector
VREF
VOUT_D
Differentiator
1/2VBAT CLK
Reset Controller
VFB Upper Boundary  Reset cycle is doubled to

VOUT_D
VOUT_D prevent irregular mode
VREF
VREF VFB Lower Boundary selection
Differentiator
BS VX VOUT
Cf1 ɸ5
ɸ1
VBAT
ɸ2 Cf2
ɸ4 ɸ3
ɸ7 ɸ6
ɸ1~7 Gm
A
DTC Pi Control VFB
P VOUT_D
&Gate d Edge Detector
Pu VREF
Driver Logic Differentiator
CLK
Reset Controller
 Removing inductor current

sub-ringing oscillation
during load transient
Chip Micrograph
 Fabricated in 180nm BCD process

1 - 7 : Power switches
8 : Control stage
Measured Waveforms
Steady-state
 Step-down mode  Step-up mode

Measured Waveforms
Steady-state
 Transition mode (VBAT ≈ VOUT)

Measured Waveforms
Load transient response
 Light to heavy transition  Heavy to light transition

Measured Power Efficiency
VBAT=4.2V
100
VBAT=3.8V
97.0% VBAT=3.4V
VBAT=2.7V
Efficiency [%]
96
92
90.4%
30 200 400 600 800 1000
Load current (mA)
 VOUT = 3.4V
 Max. Efficiency of 97.0% at VBAT=3.8V with ILOAD=200mA
 Min. Efficiency of 90.4% at VBAT=2.7V with ILOAD=30mA,
Comparison to Prior Works
[1] ISSCC ‘11 [2] ISSCC ‘12 [3] TPE ‘16 [4] ISSCC ‘17 This work
Process 0.5µm CMOS 0.18µm CMOS 0.35µm CMOS 0.18µm BCD 0.18µm BCD
Topology Buck-Boost Buck-Boost Buck-Boost FCBB FUDC
4.7µH / 22µF 2.2µH / 10uF
Inductor/Capacitor 2.2µH / 10µF 1µH / 33µF 1µH / 10µF
(10µF*) (2×20µF*)
Input Voltage (V) 3 – 5.5 2.7 – 5.5 2.5 - 5 2.7 - 4.2 2.7 – 4.2
Output Voltage (V) 3.6 0-5 3.3 3.4 3.4
Load current range (A) 0.6 – 1.2 0.1 – 2.0 0.01 – 0.4 0.25 – 2.0 0.03 – 1.0
Switching frequency 2MHz 2.5MHz ≤1.66MHz 1MHz 1MHz
Continuous current
supply
No No No No Yes
Max: 90.7% Max: 91% Max: 98.1%** Max: 96.6% Max: 97.0%
Efficiency
Min: 61% Min: 81% Min: 80.4% Min:86.1% Min: 90.4%
Recovery 50µs / 50µs 112µs / - 6µs / 12µs
Time @ VIN = 4.2V @ VIN = 4.2V @ VIN = 4.2V
Load - -
Transien
(Within 1% of (10mA→400mA) (500mA→1000m (0mA → 700mA)
VOUT) (400mA→10mA) A) (700mA → 0mA)
t
Undershoot / 50mV / 50mV 200mV / -
overshoot
- -
@ VIN = 5V @ VIN = 4.2V
100mV / 150mV
* the value of flying capacitors **measured at very low switching frequency
Conclusion
 The FUDC is a buck-boost converter, but always operates in
the buck mode
- Conventional non-inverting buck-boost : RHP-zero exists at boost mode
 Reducing design complexity
 Better transient performance (6µs settling)
 The effective resistance of the converter can be reduced

with switch size optimization strategy
- Conventional non-inverting buck-boost : Two switches in series with the inductor
 Lower conduction loss (97% peak efficiency)
Thank you
Paper 27.5
A 95.2% Efficiency Dual-Path Step-Up

Converter with Continuous Output Current
Delivery and Low Voltage Ripple
Se-Un Shin1, Yeunhee Huh1, Yongmin Ju1, Sungwon Choi1,
Changsik Shin1, Young-Jin Woo1, Minseong Choi1,
Se-Hong Park1, Young-Hoon Sohn1, Min-Woo Ko1,
Youngsin Jo1, Hyunki Han1, Hyung-Min Lee2, Sung-Wan Hong3,
Wanyuan Qu4, Gyu-Hyeong Cho
sswsin@kaist.ac.kr
1KAIST,
Daejeon, Korea
2Korea
University, Seoul, Korea
3Sookmyung Women’s University, Seoul, Korea
4Zhejiang University, Hangzhou, China
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 1 of 26
International Solid-State Circuits Conference
Outline
 Motivation
 Conventional Boost Converter
 Proposed Dual-Path Step-Up Converter
• DPUC Topology & Operation
 Overall Architecture
 Measurement Results
 Conclusions
© 2018 IEEE
Motivation
• Efficiency  Heating problem & Battery time

• Bulky inductors  Cost & Large footprint
• Performance  Ripple & Transient response
© 2018 IEEE
Conventional Boost Converter (CBC)
IL L S2 ID
VX VOUT
ILOAD
VIN S1 COUT
‫܂܃۽܄‬ ૚
• M(D) = = (0 D 1)  VIN < VOUT
‫܄‬۷‫ۼ‬ ૚ି۲
• Step-up converter is needed in many applications

• LED driver, Energy harvesting, Battery charger
© 2018 IEEE
Operation : Φ1 S1 : ON state
Φ1 Φ2
S2 : OFF state
IL + VL -
IL
VX ID VOUT
S2 ILOAD
VIN S1 COUT t
ID
Operation : Φ2 S1 : OFF state VX t

S2 : ON state
IL + VL - S2 ID
VX VOUT
t
ILOAD VOUT
VIN S1 COUT
t
© 2018 IEEE
IL L RDCR VX ID VOUT IL ID Φ1 Φ2
S2 COUT ILOAD IL,AVG
VIN S1 RESR
LESL
IL,AVG = MILOAD ILOAD
 Large Inductor Current

 Conduction loss (IL,RMS2RDCR) Large IL
 Heating problem
 Large sized inductor with small RDCR is needed.
© 2018 IEEE
IL L RDCR VX ID VOUT
ID Large di/dt
S2 COUT ILOAD
VIN S1 RESR
ΔVOUT LESL t
Discontinuous ID
=ΔVC+ΔVR+ΔVL
VOUT ΔVOUT
 Large VOUT Ripple
 Large Switching Spike
 Performance degradation of loading blocks Switching spike
( large dv/dt )
t
 Over-voltage stress on the loading blocks
Large ΔVOUT
© 2018 IEEE
Proposed Dual-Path Step-Up Converter
S3 S4
IC
CF VF=VOUT-VIN
IL L ID VOUT
S1 S2 S5
VIN COUT ILOAD
‫܂܃۽܄‬ ૛ିࡰ
• M(D) = = (0 D 1)  VIN < VOUT
‫܄‬۷‫ۼ‬ ૛ି૛۲
• 1 inductor & 1 flying capacitor (Hybrid structure)

• No limitation of conversion ratio despite the hybrid structure
© 2018 IEEE
Operation : Φ1 Φ1
S3 IC S4 S1,S3,S5 : ON state
S2,S4 : OFF state
IL
-ΔVCF CF t
IL L VX S5 ID VOUT ID C-Path
S2 ILOAD
VIN S1 C-Path COUT t
IC
t
• IL is increased
VX
• C-Path delivers the current to the output
t
VOUT
as an additional path
 CF is discharged (-∆VCF) t
© 2018 IEEE
Operation : Φ2 S1,S3,S5 : OFF state
Φ1 Φ2
S3
IC S4
S2,S4 : ON state
IL
+ΔVCF CF t
IL L VX S2 S5 ID VOUT ID L-Path
ILOAD
VIN S1 L-Path COUT t
Charge Balance
IC
t
• IL is decreased
VX
• L-Path delivers the current to the output
t
VOUT
 CF is charged (+∆VCF)
 Charge balance on CF t
© 2018 IEEE
CBC DPUC
1.9 IL
1.7 CBC: MILOAD
1.5
Normalized IL
(= IL/ILOAD)
1.3
Small IL
1.1 t
0.9 ID C-Path L-Path
0.7 DPUC: (M-0.5) ILOAD
0.5
1 1.2 1.4 1.6 1.8 2
M Conversion ratio : VOUT/VIN Continuous ID
t
VOUT
• IL = (M-0.5) ILOAD ΔVout
 Reduced IL by factor of (M-0.5)
Small ΔVOUT
t
© 2018 IEEE
Top Structure
S3 VZ S4
: LDMOS
: CMOS
VS3 VS2 VF CF VS4
L VX S2 S5 VOUT
VY ILOAD
VIN VS1 S1 VS5 COUT
RS RF1
Current Sensor
CLK
Φ1 Q S VSEN
Slope Compensator
VFB
R VC
VS1 VS2 VS3 VS4 VS5
CC VREF
Φ1,Φ3,Φ2 2P / 3P Phase CLK RF2
Gate Driver & Level RC
Shifter Mode Selector Φ1
XSM Zero Current VX
Detector VS2
© 2018 IEEE
Conduction Loss
8 20
18
Normalized Conduction Loss

7
(= Conduction Loss/IL2 )
16
6
14
CBC
5 12
CBC
10
4
DPUC 8
DPUC
3
6
2 4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
M Conversion ratio : VOUT/VIN M Conversion ratio : VOUT/VIN
• Lower total conduction loss of DPUC than that of CBC

© 2018 IEEE
Conduction Loss
8 20
18

7
16
6
14
CBC
5 12
CBC
10
4
DPUC 8
DPUC
3
6
2 4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
• When conversion ratio is low, conduction loss
increase again due to large peak capacitor current
© 2018 IEEE
3-Phase Mode Operation
Operation : Φ1 Operation : Φ2
S3 S4 S3 IC S4
IC
-ΔVCF CF +ΔVCF CF
IL L S5 ID IL L VX S2 S5 ID VOUT
VX VOUT
S2 ILOAD ILOAD
VIN S1 C-Path COUT VIN S1 L-Path COUT
Operation : Φ3
S3 IC S4
CF
IL L RDCR S2 S5 ID VOUT
COUT
VIN S1 L+C Path RESR ILOAD
LESL
© 2018 IEEE
IC : DPUC(2P)
Start-up DPUC(2P)
: DPUC(3P) 2phase
operation(Φ1,Φ2)
IL
0 t Φ2  TS-Φ1 Φ1 Φ2
Φ3  0 t
TS
Φ1 Φ3 Φ2=0.5TS YES
Φ1 > 0.5TS ?
ID Reduced RMS current DPUC(3P)
NO
& Ripple
3phase operation IL
(Φ1,Φ3,Φ2)
ILOAD Φ1 Φ3 Φ2
t
t Keep Φ2  0.5TS
TS Insert Φ3Φ1-Φ2
• Reduced peak current of C-Path
 Despite short Φ1, improved efficiency and voltage ripple
© 2018 IEEE
8 20
18

CBC
16
6
CBC
DPUC(2P)
CBC
14
CBC
5 12
DPUC(2P)
10
4 DPUC(2P) DPUC(2P)
8
3
DPUC(3P) 6 DPUC(3P)
DPUC(3P) DPUC(3P)
2 4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
 Even though Φ1 is short and M is low, reduced conduction

loss is achieved
© 2018 IEEE
RHP Zero
IL L ID
VX VOUT
S2 ILOAD
VIN S1 COUT
s
(1- )
vˆ o (s) wz
G vd (s) = = G vd0 2
ˆd(s) s s
+ +1
w 02 Qw 0
IL(t)
(1-D)2 R R ID(t)
wz = = 2
L LM ID,AVG(t) t
D=0.5 D=0.7
 Right-half-plane (RHP) zero worsens the transient response and

complicates loop gain stabilization
© 2018 IEEE
RHP Zero
Conversion ratio (M): VOUT/VIN

2L-CBC [2]
DPUC(3P)
CBC
DPUC(2P)
Normalized Positive Zero (= ωz*(L/R) )
CBC DPUC(2P) 2L-CBC [2] DPUC(3P)

RHP R 2R 2R 2.25R
Zero LM2 LM(2M -1) LM2 LM2
© 2018 IEEE
Die micrograph
• Fabricated in 180nm
BCDMOS Process
© 2018 IEEE
Measurement
2-Phase Mode (DPUC) CBC
VIN=2.8V
VOUT=4.2V
fSW=1MHz
ILOAD=600mA
VOUT : 2V/Div
VOUT,AC : 50mV/Div
IL : 500mA/Div
VX : 5V/Div
3-Phase Mode (DPUC) Output Voltage Ripple

VIN=3.3V
VOUT=4.2V
fSW=1MHz
ILOAD=600mA
VOUT : 2V/Div
VOUT,AC : 50mV/Div
IL : 500mA/Div
VX : 5V/Div
© 2018 IEEE
Measurement
DPUC (DCM) Transient Response
VIN=2.8V
VOUT=4.2V
fSW=700kHz
ILOAD=40mA
VOUT : 2V/Div
VOUT,AC : 10mV/Div
IL : 200mA/Div
VX : 5V/Div
DCM (DPUC)
VX Waveform
VX : 2V/Div
© 2018 IEEE
Measurement
Power Conversion Efficiency (%) VIN=3V, VOUT=4.2V
100 95.2%
90
80
70 DPUC(3P) w/ RDCR=200mΩ
CBC w/ RDCR=200mΩ
60
0 100 200 300 400 500 600 700 800
ILOAD (mA)
• Even though RDCR is 200mΩ, the DPUC has the peak efficiency of
95.2% which allows the use of a cheaper and smaller size inductor
© 2018 IEEE
This Work 2014JSSC [1] 2012 TPE [2] TPS6107 [3] 2013JSSC [4]
Process 0.18μm BCD 0.35μm BCD 0.3μm CMOS N/A 0.35μm CMOS
Input voltage 2-4.2V 2.7~4.5V 3.1~3.3V 0.9-5.5V 1.8~3.2V
Output voltage 3-5V 8V 4.5V 1.8-5.5V 3-4.2V
Inductor (L) 4.7μH 10μH 470nH/470nH 1.5-2.5μH 1μH
Capacitor 10μF/10μF* 10μF 20μF 10μF 10μF
1MHz : CCM 1MHz/N
Switching frequency 1MHz 5MHz 1.2MHz
(<1MHz : DCM) (N=2i and i=0-5)
Load current 10-800mA 20-300mA 400mA 5-600mA 5-800mA
Topology DPUC CBC 2-Phase CBC CBC CBC
Output delivery current Continuous Discontinuous Discontinuous Discontinuous Discontinuous
Reduced inductor current YES NO YES NO NO
Ripple Voltage < 15mV 90mV 20mV N/A 80mV
Peak Efficiency (RDCR of L) 95.2% (200mΩ) 90% (11mΩ) N/A 92% 94.8% (9mΩ)
© 2018 IEEE
* The value of flying capacitor
Conclusions
Dual-Path Structure : Reduced inductor current (IL)
 Efficiency improvement by reduced conduction loss
 Allow small inductor with large RDCR
Continuous output delivery current (ID)
 Reduced output voltage ripple
 Reduced switching spikes
Hybrid structure
 No limitation of conversion ratio with single flying capacitor
 Improved performance in wide conversion ratio by mode selector
Alleviated RHP-zero effect
 Easy to design compensator of PWM controller
 Improved transient response
© 2018 IEEE
© 2018 IEEE
An 87.1% Efficiency RF-PA Envelope-Tracking
Modulator for 80MHz LTE-Advanced Transmitter and
31dBm PA Output Power for HPUE in 0.153μm CMOS
Chen-Yen Ho, Shih-Mei Lin, Che-Hao Meng, Hao-Ping Hong,

Sheng-Hong Yan, Ting-Hsun Kuo, Chia-Sheng Peng, Chieh-Hsun
Hsiao, Hsin-Hung Chen, Da-Wei Sung, Chien-Wei Kuan
MediaTek Inc., Hsinchu, Taiwan
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 1 of 48
Outline
• Motivation of 80MHz High-efficiency ETM
• ET System and AC-coupled ETM Architecture
• ETM Circuit Blocks
– Dual-mode AC Feed-forward Class-AB Linear Amplifier
– Buck-Boost Convertor
– Dual Power Line(DPL) Buck Convertor
• Conclusions
Outline
• Conclusions
Envelope Tracking Technology - Efficiency
PAE improve > 30%
Efficiency up
Average power tracking (APT) Envelope tracking (ET)
• APT  ET
• Tracking bandwidth ≥ up-link carrier frequency
• ET enhance intrinsic efficiency of RF-PA and PAE
Envelope Tracking Technology- Temperature
Temp. 20% reduction
ETM Cool down ETM
RF-PA RF-PA
B41 antenna output 26dBm B41 antenna output 26dBm

Average power tracking (APT) Envelope tracking (ET)
• For mobile device, ET enables RF-PA to provide larger output power
within limited supply from battery and reduce thermal issue
• The ET modulator faces the design challenges of high-bandwidth
and high-power transmission
Challenge of High-bandwidth Transmission
High data-rate required for 4G LTE-Advanced:
20MHz 20MHz 20MHz 20MHz
Intra-band contiguous carrier aggregation
• Intra-band CCA is used by telecom operator

• High-bandwidth demand requires advanced modulation techniques
(QPSK, Multiple QAM) lead to higher PAPR signals causes a
degradation in PA efficiency
Challenge of High Power User Equipment (HPUE)
> 5W
Power Class 2: 26dBm

Power Class 3: 23dBm
(antenna output)
• High frequency signals (B41) can't travel as far by Power Class 3
(PC3) , so cellular carriers need to achieve higher output power
• HPUE - Power Class 2 (PC2) for the output power level of 26 dBm
doubles the maximum output power by PC3
ETM Design Issues
• High bandwidth for 80MHz 4CCA
 Dual-mode AC Feed-forward Class-AB Linear Amplifier
• High power-efficiency for HPUE
1. Linear Amplifier
 Auto-detect Selection (ADS)
2. Buck-Boost converter
 Self-Compensated Ramp Generator (SCRG) and Output Dependent
Auxiliary Switch (ODAS)
3. Buck converter
 Dynamic Body Bias (DBB) and Dynamic Driving Switch (DDS)
ET Modulator Requirements
Specification Target
Tracking Bandwidth 1RB~400RB
ET Output Swing
1.2~4.5V
(VPAmin~VPAmax)
ETM Output Power 4W
ETM Efficiency > 80%
ETM Output Capacitor Load < 0.8nF
RB: resource block (180 kHz)
• Wide bandwidth, large power, and high efficiency are mandatory
Outline
• Conclusions
Why AC-coupled ETM Architecture
  Buck regulator
VDD VDD
DC-pathET swing DC-path ET swing

Driver
VDD LBUCK
Vref
VENVP
VPA
VENVN
AC-path AC-path
TX IN TX OUT
PA
AC-coupled ETM DC-coupled ETM

• DC-path provides >80% power • DC-path provides <80% power
• AC-path provides <20% power • AC-path provides >20% power
• Small ET waveform swing • Large ET waveform swing
• Good efficiency for high-load line PA • Worse efficiency
DC-path by high efficiency (Buck), AC-path by high speed (LA)
AC-coupled ETM Architecture
• Class-AB amplifier
operates in voltage
feedback
ET swing
• Vset is chosen to maintain

a wanted level-shifting
- +
Vset voltage on the ac-coupling
capacitor
High-efficiency AC-coupled ETM Strategy
• Increase DC-DC power
and reduce LA power
ET swing • Reshape ET waveform to

achieve better ETM
efficiency
‒ De-trough
‒ PA gain compression
and reduce LA power
ET swing • Reshape ET waveform

to achieve better ETM
efficiency
‒ De-trough low side of ET
waveform
Ref [1]: X. Liu, ISSCC 2017
and reduce LA power
ET swing • Reshape ET waveform

to achieve better ETM
efficiency
‒ De-trough low side of ET
waveform
Proposed Hybrid AC-coupled ETM
L=0.68μH C=4.7μF
BB BB
BAT Maximum Power

Selection Circuit
• High speed AC Feed-Forward
Buck-Boost
Converter
VBB
BAT Class-AB Linear Amplifier for
SCRG
VRAMP
H
80MHz envelope tracking
VGP2 VGP1
PWM
DBB2 DBB1
TYPE III VCOMP
MP2 MP1
• Buck-Boost fast transient and
BAT H
H
VCTL_P2 VCTL_P1
setting for power switching
DAC VCTL_P1
Controller
LA_OUT - VCTL_P2 VGN
D2S and Level Shifter VCTL_N
VCTL_N
PA +
MN • Dual Power Line High-
efficiency Buck
DAC
BB
L=1μH
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
TX IN External TX OUT
PA
CLA C1=2.2nF
Hybrid AC-coupled ETM ET-Mode
L=0.68μH C=4.7μF
BB BB
BAT Maximum Power

Selection Circuit
• Dual-mode LA can be configured
Buck-Boost
Converter
VBB
BAT by TD-LTE/FDD-LTE operation
SCRG
VRAMP
H
and number of RBs
VGP2 VGP1
PWM
DBB2 DBB1
TYPE III VCOMP
MP2 MP1
• An additional Buck-Boost is used
BAT H
H
VCTL_P2 VCTL_P1
to provide the Class-AB LA with
VCTL_P1
an optimized supply voltage
DAC
Controller
PA + VCTL_N
MN
• DPL-buck is utilized to determine

DAC
BB
L=1μH the power path VH, VBAT or VBB
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
PA
CLA C1=2.2nF
L=0.68μH C=4.7μF
BB BB
BAT Maximum Power

Selection Circuit
Buck-Boost
Converter
VBB
SCRG
VRAMP
H
and number of RBs
VGP2 VGP1
PWM
DBB2 DBB1
TYPE III VCOMP
MP2 MP1
BAT H
H
VCTL_P2 VCTL_P1
VCTL_P1
DAC
Controller
PA + VCTL_N
MN

DAC
BB
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
PA
CLA C1=2.2nF
L=0.68μH C=4.7μF
BB BB
BAT Maximum Power

Selection Circuit
Buck-Boost
Converter
VBB
SCRG
VRAMP
H
and number of RBs
VGP2 VGP1
PWM
DBB2 DBB1
TYPE III VCOMP
MP2 MP1
BAT H
H
VCTL_P2 VCTL_P1
VCTL_P1
DAC
Controller
PA + VCTL_N
MN

DAC
BB
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
PA
CLA C1=2.2nF
Outline
• Conclusions
Hybrid AC-coupled ETM
L=0.68μH C=4.7μF
VBB
VBAT VODAS Maximum Power
Selection Circuit
Buck-Boost
Converter
VBB_P1
VBB_N1
VBB_N2
VBB_P2
VBAT Class-AB Linear Amplifier for
VBB
VRAMP ISEN_MP2 ISEN_MP1

SCRG mipi DAC Mode det. ODAS VH
PWM
VGP2 VGP1
ᵝ VPWM VODAS DBB2 DBB1
VCOMP

TYPE III VBB_P2
MP2 MP1
DDS
Gate Driver
VBAT
VH
VCTL_P2 VCTL_P1
setting for power switching for
mipi DAC VH ISEN_MN
ILPC standard
Analog VCTL_P1
DIG
Controller Level VCTL_P2

VLA_OUT -
Shifters
D2S VCTL_N VGN
VPA + VCTL_N
ISEN_MP1
DPL-Buck ISEN_MP2 Mode PWM/PFM Gate Driver MN
ISEN_MN
Converter
• Dual Power Line High-
DAC
BB
L=1μH efficiency Buck
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
PA
CLA C1=2.2nF
Dual-mode AC Feed-forward Class-AB Linear Amplifier
Class-AB Stage
VBB
Gm-AC Vgp
AC Response
ETM Loop Gain (dB)

M12
HBM+AC FF
Mode M10 9 HBM
VIP Control Vgcp
HGM 6 HGM
VIN
HBM VLAout 3
Vgcn
-3dB corner
M11 0
ETM gain=2
-3
M13
0 20 40 60 80 100 120 140
Gm-AC Vgn Frequency (MHz)
GND
• HBM/HGM Dual-mode configuration

• Bandwidth of HBM can be pushed to 2× times compared to HGM
• Direct AC feed-forward path drives a Class-AB output stage, which further
enhances the LA bandwidth by 30% to 40%
HGM AC Feed-forward Class-AB Linear Amplifier
Rc1 Cc1
Vgp
Vp2
Rc2 Cc2 VLAout
Vp1 Vgn
Vp1 Rc3 Cc3
Von1
VIN VIP Vgp Vgn
M1 M2 Vctrlp
Vgp Vctrlp Vgn
Vcasn
Vcasn
SMODE1 SMODE2
Von1/2 Vop1/2 Vop1/2
Vop2 Vop1 Von1 Vip Vin Vip
Von2
M5 M6 M3 M4 M7 M8 M9
HBM HGM AC Feed-forward
• High-loop-gain configuration to suppress receiver band noise for FDD-LTE
• AC feed-forward path from M7~M9 to output stage
• Core devices for all the signal paths, cascode I/O devices are used for all
amplifier stages and the Class-AB output stage
HBM AC Feed-forward Class-AB Linear Amplifier
Rc1 Cc1
Vgp
Vp2
Rc2 Cc2 VLAout
Vp1 Vgn
Vp1 Rc3 Cc3
Von1
VIN VIP Vgp Vgn
M1 M2 Vctrlp
Vgp Vctrlp Vgn
A B Vcasn
Vcasn
SMODE1 SMODE2
Von1/2 Vop1/2 Vop1/2
Vop2 Vop1 Von1 Vip Vin Vip
Von2
M5 M6 M3 M4 M7 M8 M9
HBM AC Feed-forward
• Push the dominant pole at node A/B to higher frequency
• 3dB frequency above 100MHz
• For all above intra-band 2CCA (40MHz) applications (TD-LTE)
Class-AB Output Stage Auto-detect Selection (ADS)
VBB
VBB
Vgp
Vgp
M12
Vgcp • When VBB > Vth Vgcp
M12 • When VBB < Vth
- M10
+ SW1 M10
GND VLAout
SW1 • Buffer is utilized GND VLAout • SW1/SW2 are on
SW2 VBB
VBB
to drive cascode and operate as
-
+ M11 device M10/M11 SW2 M11 small resistors
Vgcn Vgcn
Vgn M13 M13
Vgn
GND GND
• Achieve minimum supply voltage VBB of 1.5V

• Better efficiency at mid-range PA output power and extend ET mode dynamic
range
Class-AB Output Stage Auto-detect Selection (ADS)
VBB
VBB
Vgp
Vgp
M12
Vgcp • When VBB > Vth Vgcp
M12 • When VBB < Vth
- M10
+ SW1 M10
GND VLAout
SW1 • Buffer is utilized GND VLAout • SW1/SW2 are on
SW2 VBB
VBB
to drive cascode and operate as
-
+ M11 device M10/M11 SW2 M11 small resistors
Vgcn Vgcn
Vgn M13 M13
Vgn
GND GND
• Achieve minimum supply voltage VBB of 1.5V

• Better efficiency at mid-range PA output power and extend ET mode dynamic
range
Class-AB Output Stage Auxiliary Amplifier
VBB
Vrefp VBB
Vgcp • The high-speed auxiliary amplifier is

Vb1 MN2 Vgp utilized to drive M10 and M11
M12 Vds
Vgcp
- M10
MN1 + • To increase the 2nd pole frequency at the
GND
SW1 GND VLAout output, core devices MP2 and MN2 are
SW2 VBB used to realize high gm
VBB
MP1
-
+ M11
Vgcn Vgcn • Ensures the Vds across the core devices
Vrefn
Vgn M13 Vds M12 and M13 < 1.8V
MP2
Vb2 GND
GND
L=0.68μH C=4.7μF
BB
BAT Maximum Power

Selection Circuit • High speed AC Feed-Forward
VBB
VBAT
Class-AB Linear Amplifier for
SCRG
VRAMP ISEN_MP2
VH
ISEN_MP1 80MHz envelope tracking
PWM
VGP2 VGP1
DBB2 DBB1
TYPE III VCOMP
MP2 MP1
DDS
Gate Driver
VBAT
mipi DAC
Analog
VH
VCTL_P1 VH
VCTL_P2 VCTL_P1
ISEN_MN
DIG
Controller Level VCTL_P2

VLA_OUT -
Shifters
D2S VCTL_N VGN
VPA + VCTL_N
DPL-Buck
Converter
ISEN_MP1
ISEN_MP2
ISEN_MN
Mode PWM/PFM Gate Driver MN
• Dual Power Line High-
Dual-mode
efficiency Buck
mipi DAC AC Feed-forward L=1μH
VENV_IP VBB Class-AB LA
C=4.7μF VPA
LPF + VLA_OUT
VENV_IN
-
LPF
R1
RLA R=1ohm
C1 TX IN TX OUT
C=2.2nF External
PA
CLA
Self-Compensated Ramp Generator (SCRG) (1/2)
C2
∆VC slope=1
VCOMP
VCOMP
C1 R2 slope=1
VBAT = 2.5V
SCRG SCRG
Buck-mode Boost-mode
VAVDD
(β-1)*R1 VBB = VBAT
βVout
VOUT -
VCOMP VBAT = 5.0V VBB > VBAT
VREF
R1 + Step down Step down
VOUT=VBB ∆V β*VBB β*VBB

β*VO1 β*VO2 β*VO1 β*VO2
Step up Step up
TYPE III Error-Amplifier
• Large C1 of error-amplifier degrades transient response of Buck-Boost

• Reduce charge/discharge time through C1
• An artificial ramp, shapes the ratio of VCOMP to β·VBB into a slope of 1
• Achieve fast DVS
C2
∆VC slope=1
VCOMP
VCOMP
C1 R2 slope=1
VBAT = 2.5V
SCRG SCRG
Buck-mode Boost-mode
VAVDD
(β-1)*R1 VBB = VBAT
βVout
VOUT -
VCOMP VBAT = 5.0V VBB > VBAT
VREF
R1 + Step down Step down
VOUT=VBB ∆V β*VBB β*VBB

β*VO1 β*VO2 β*VO1 β*VO2
Step up Step up
TYPE III Error-Amplifier
• Large C1 of error-amplifier degrades transient response of Buck-Boost

• Reduce charge/discharge time through C1
• An artificial ramp, shapes the ratio of VCOMP to β·VBB into a slope of 1
• Achieve fast DVS
VAVDD VAVDD
VBAT
ITAIL2 ITAIL1
Reset VAVDD
VAVDD
(β-1)*R
VRAMP_BUCK
VRAMP_BOOST + Reset
X1 VR_BUCK
-
C2
VCCS
R
C1
V2I
Boost Buck
• Ramp slope is controlled by VBAT

VAVDD VAVDD
VBAT
ITAIL2 ITAIL1
Reset VAVDD
VAVDD
(β-1)*R
VRAMP_BUCK
VRAMP_BOOST + Reset
X1 VR_BUCK
-
C2
VCCS
R
C1
V2I
Boost Buck
• Ramp slope is controlled by VBAT

Output Dependent Auxiliary Switch (ODAS)
Buck Mode L=0.68μH Boost Mode L=0.68μH
(P2&ODAS on) (P2 on)
VBAT VBAT
VODAS VODAS
VBB VBB
VBB_P1 VBB_P1
VBB_N1 VBB_N2 C=4.7μF VBB_N1 VBB_N2 C=4.7μF
VBB_P2 VBB_P2
mipi DAC Mode det. ODAS mipi DAC Mode det. ODAS
VPWM VODAS VPWM VODAS
VBB_P2 VBB_P2
• Buck mode, P2 and ODAS are on

• ODAS provide lower voltage down to 0.5V
• Boost mode, only P2 on to reduce switching loss and enhance efficiency
Output Dependent Auxiliary Switch (ODAS)
Buck Mode L=0.68μH Boost Mode L=0.68μH
(P2&ODAS on) (P2 on)
VBAT VBAT
VODAS VODAS
VBB VBB
VBB_P1 VBB_P1
VBB_N1 VBB_N2 C=4.7μF VBB_N1 VBB_N2 C=4.7μF
VBB_P2 VBB_P2
mipi DAC Mode det. ODAS mipi DAC Mode det. ODAS
VPWM VODAS VPWM VODAS
VBB_P2 VBB_P2
• Buck mode, P2 and ODAS are on

• ODAS provide lower voltage down to 0.5V
• Boost mode, only P2 on to reduce switching loss and enhance efficiency
L=0.68μH C=4.7μF
BB
VBAT VODAS Maximum Power
Selection Circuit
Buck-Boost
Class-AB Linear Amplifier for
VBB_P1
Converter VBB_N1 BAT
VBB_N2
VBB_P2

VBB
VRAMP
SCRG mipi DAC Mode det. ODAS H
VGP2 VGP1
PWM
ᵝ VPWM VODAS DBB2 DBB1

VCOMP

TYPE III VBB_P2
MP2 MP1
BAT H
H
VCTL_P2 VCTL_P1
DAC VCTL_P1
Controller
PA + VCTL_N
MN • Dual Power Line High-
efficiency Buck
Dual-mode
mipi DAC AC Feed-forward
VBB L=1μH
VENV_IP Class-AB LA
C=4.7μF
LPF + VLA_OUT PA
VENV_IN
-
LPF
R1
RLA R=1ohm
C1
C=2.2nF
PA
CLA
Dynamic Body Bias
• DBB automatically sense
VBAT VBB VBAT VBB
and choose suitable body
VPG12 VPG11 VPG12 VPG11 voltage
VH VH VH
0V  toggling power MOS to
VH 0V
acquire lowest Ron
VDBB1 VDBB1  non-toggling MOS with
VBAT VBB VBAT VBB highest bulk voltage
VPG21 VPG22 VPG21 VPG22
VH VH • DDS technique chooses the
0V VH VH 0V highest voltage level VH to
VDBB2
drive power MOS and the
VDBB2
VBAT>VBB VBB>VBAT control circuits
Dynamic Driving Switch
VBB
Maximum Power
• DBB automatically sense
Selection Circuit and choose suitable body
VBAT voltage
 toggling power MOS to
VGP2 H VGP1
acquire lowest Ron
VBAT VH  non-toggling MOS with
DBB2 DBB1
Controller
VCTL_P1 MP2 MP1 highest bulk voltage
VCTL_P2
and Level Shifter
VCTL_N VCTL_P2 VCTL_P1
• DDS technique chooses the
H
highest voltage level VH to
VGN
VCTL_N drive power MOS and the
MN
control circuits
Outline
• Conclusions
Die Micrograph
• Technology: 0.153um CMOS

• Chip area: 5.133mm2
(2.95mm×1.74mm)
• External passive components
– 4.7uF capacitor for AC-coupled
path
– 1uH inductor for DPL Buck
– 4.7uH inductor for Buck-Boost
ETM Measurement
Efficiency
MAX 87.1%
ETM Efficiency (%)
MAX 85.5% • ETM efficiency plot with a

fixed 4Ω resistor and 0.8nF
capacitor
MAX 82.3%
MAX 81.2%
• The ETM peak efficiencies
20MHz : 87%
40MHz : 85.5%
60MHz : 82.3%
DC=3.8V 80MHz : 81.2%
ETM output power (W)
ETM Measurement
Receiver Band Noise Comparison FDD-LTE
-138.5 -139.1
-140.2
-141.3
B5,25RB -142.4 B7,75RB
(45MHz) B1,100RB
(120MHz)
(190MHz)
B2,50RB
(80MHz) -143
-143.2 B3,50RB -143.5
(95MHz)
@ PA output power 28dBm (PC3)
-147.3
-148.2
Internal Loop Power Control (ILPC) Measurement
VBAT=3.6V VBAT=2.8V
VPA VPA
0.5V  4.2V
VBAT=3.6V VBAT=2.8V
VPA VPA
4.2V  0.5V
for 3G/4G cellular system, power < +/-0.5dB within time slot 18us
B41 ETM+PA 40/60MHz ET Measurement
PA out 26dBm PA out 26dBm

E-AULR_L E-AULR_R E-AULR_L E-AULR_R
-41.68dBc -41.54dBc -40.22dBc -39.86dBc
ETM out ETM out
PA out PA out
2CCA LTE-40MHz 3CCA LTE-60MHz

HBM-Mode HBM-Mode
B41 ETM+PA 80MHz ET Measurement
ET80MHz @PA ETM out

out 26dBm
E-ACLR_L: E-ACLR_R:
-38.93dBc -38.16dBc
PA out
4CCA LTE-80MHz
HBM-Mode
• Maximum power reduction (MPR) is 2dB
• RF Front-end loss ~ 5dB
ETM ET/APT Efficiency Comparison B41 LTE-20MHz
APT-Mode
ET-Mode
DC=3.8V
lowest 1.5V VBB 450mA
@ 18dBm RF-PA out @31dBm
Crossing
Point
@18dBm
HPUE
MPR *RF Front-end loss ~ 5dB*
ET-Mode Dynamic Range
• ET-Mode achieve 13dB dynamic range from 18dBm to 31dBm

• Compared with APT-Mode, it saves power by 34.5% at 31dBm PA out (HPUE)
Comparison with Prior ETM
2017 2016 2013 2014 2015
This Work ISSCC ISSCC ISSCC ISSCC ISSCC
HKUST [1] Samsung [2] UCSD [3] STM [4] Samsung [5]
CMOS Technology 153nm 65nm 130nm 180nm 130nm 130nm
BW (MHz) 80 20 40 20 10 10
Band41 Band1 Band41 Band3 Band3
LTE Band 2.4GHz
2.593GHz 1.95GHz 2.535GHz 1.75GHz 1.75GHz
ETM 87.1 @ 20MHz
Efficiency (%) 85.5 @ 40MHz 88.7 @ 80 @
83 @ 10MHz 83 @ 20MHz 86.2 @ 10Mz
(Fix-load) 82.3 @ 60MHz 20MHz 10MHz
(peak) 81.2 @ 80MHz
-41.5 @ 40MHz
ACLR (dBc) -32 -41 -38.5 -39 -39.4
-39.9 @ 60MHz
(ETM+PA) @ 20MHz @ 40MHz @ 20MHz @ 10MHz @ 10MHz
-38.1 @ 80MHz
7.54 @ 40
PAPR(dB) 8.29 @ 60 NA NA 6.7 6.7 NA
8.30 @ 80
RF Pout (dBm) 26 @ 80MHz* 1 26.5
23.9 28.3 26.3 26
(ETM+PA) 31 @ 20MHz**
* 26dBm = power class 3 (23dBm) - MPR (2dB) + Front-end loss (5dB)
** 31dBm = power class 2 (26dBm) + Front-end loss (5dB)
Outline
• Conclusions
Conclusions
• ETM system
– Present a 80MHz ETM supporting 4G LTE-A intra-band 4CCA
– Digital algorithm assists ETM by ET shaping waveform (de-trough) and PA
gain compression to optimize efficiency
• ETM circuit block

– Use dual-mode AC Feed-forward Class-AB LA to achieve high BW/linearity
– Buck-Boost with SCRG for fast DVS and ODAS for optimized efficiency
– DPL Buck With DBB and DSS, ETM smartly select DC power source
• Achieve the highest ET bandwidth in CMOS process
A 2TX Supply Modulator for Envelope-Tracking
Power Amplifier Supporting Intra- and Inter-Band
Uplink Carrier Aggregation and
Power Class-2 High-Power User Equipment
Takahiro Nomiyama1, Yongsik Youn2, Younghwan Choo1,
Dongsu Kim1, Jaeyeol Han1, Junhee Jung1, Jongbeom Baek1,
Sungjun Lee1, Euiyoung Park1, Jeonghyun Choi1, Ji-Seon Paek1,
Jongwoo Lee1, Thomas Byunghak Cho1, Inyup Kang1
1Samsung Electronics, Hwaseong, Korea

2Samsung Semiconductor, San Jose, CA
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 1 of 33
Outline
▪ Introduction
▪ Recent LTE Standards and Requirements
▪ Uplink Carrier Aggregation
▪ Power Class-2 HPUE for Band41
▪ Proposed 2TX SM Techniques
▪ Size-efficient Architecture with Capacitor Swapping
▪ High Power Output with Return to Battery Switching
▪ Experimental Results
▪ Conclusion
Outline
▪ Introduction
▪ Conclusion
Supply Modulator(SM)
Envelope
Average Power
Tracking (ET)
Traditional PA Tracking(APT)
Dynamic supply
Fix supply Stepwise supply
Dissipated Max. Eff. Max. Eff.

as heat < 40% Toward 45%
 SM improves power efficiency of uplink communication.

 Optimum operation scenario: ET for high POUT, APT for low POUT
Outline
▪ Introduction
▪ Conclusion
Uplink Carrier Aggregation(UL-CA)
Intra-band contiguous CA
SM
20 20 PCC
M M PA
SCC
Band A Band B
Intra-band non-contiguous CA PCC: Primary
SM1 SM2
Component Carrier
20 20 PCC SCC
M M PA PA SCC: Secondary
Band A Band B Component Carrier
Inter-band CA SM1 SM2
20 20 PA PCCSCC PA
M M
Band A Band B
Conventional SM
 Conventional SM supports Intra-band contiguous CA with 40MHz ET operation[2].

[2] “An RF-PA Supply Modulator Achieving 83% Efficiency and - 136dBm/Hz Noise for LTE-40MHz and GSM 35dBm Applications,” ISSCC, pp. 354-355, Feb. 2016.
Uplink Carrier Aggregation(UL-CA)
Intra-band contiguous CA
SM
20 20 PCC
M M PA
SCC
Band A Band B
Intra-band non-contiguous CA PCC: Primary
SM
Component Carrier
20 20 PCC SCC
M M PA PA SCC: Secondary
Band A Band B Component Carrier
Inter-band CA SM
20 20 PA PCCSCC PA
M M
Band A Band B
Proposed SM
 Proposed 2TX SM supports both Intra- and Inter-band CA.
LTE Subframe structure & UL-CA power requirement
 VTX1 and VTX2 must be independent. (VTX :SM output voltage)

 Both voltage and ET-APT mode transition must be seamless.
Power Class-2 High Power User Equipment(HPUE)
VBATT 5V
Battery
INSM=2.0W range
0V
SM
INENV
OUTSM=1.6W
η=80% 29dBm 26dBm
(800mW) Duplexer (400mW)
PA + Switch
INRF OUTPA (3dB loss) OUTRF
η=50%
 HPUE requires 26dBm antenna output power and 1.6W SM output power.
 SM needs high voltage, high power buck-boost converter.
Requirements for 2TX SM
Item Contents
UL-CA Independent TX operation
HPUE Boost level envelope
Multi-band GSM/WCDMA/LTE
Multi-mode ET/APT operation
Bandwidth 40MHz ET operation
Efficiency >80% max. with ET operation
Noise Low RX band noise for FDD
Size Small die size
Outline
▪ Introduction
▪ Conclusion
High voltage, hybrid SM structure
Dual-supply
Buck
VBATT 800
Linear Amplifier
with BK 600 IPA
Class AB buffer Isw
(mA)
Current [mA]
ILinear ISW 400
Envelope LA TX
200
VBATT
IPA 0
Vref Buck- -200

DAC Boost APT switch
Ilinear
-400
100 101 102 103
High voltage Time [us]
(µs)
Buck-Boost
 A set of Buck-Boost(BB), Buck(BK) and Linear Amplifier(LA) is needed.

 BB provides boosted voltage to LA and BK.
 BK provides DC current with high efficiency, LA provides AC current with high BW.
2TX SM with 2BBs
 Two size-consuming BBs are needed.

(Four power transistors in BB)
 Two big inductors for BBs are needed.

(e.g. 2016 size)
 Passive component and PCB area

becomes almost twice.
Proposed SM architecture
VBATT
Mux BK1
Envelope1
 Only one BB and one Inductor are
LA1 TX1 used.
VBATT Bypass- GSM

DAC1 LDO PA  BB output is shared for 2TX by APT
Mux BUCK-BOOST APT switches.
switches
CBB CBK
DAC2
 CBK is also shared for BK1 and BK2.
LA2 TX2
Envelope2
Mux BK2
VBATT
2TX ET operation
VTX1_pk>VTX2_pk
VBATT
Mux BK1
Envelope1
 Each set of LA and BK operate jointly
LA1 TX1 to generate envelope.
VBATT Bypass- GSM

DAC1 LDO PA  BB provides LA and BK voltage,
Mux BUCK-BOOST APT which is shared with 2TXs.
switches
CBB CBK
DAC2
 BB output voltage is decided by the
higher power between 2TXs.
LA2 TX2
Envelope2
Mux BK2
VBATT
2TX APT operation
VTX1>VTX2
VBATT
Mux BK1
Envelope1
 BB supplies the TX power, which
LA1 TX1 requires higher voltage.
VBATT Bypass- GSM

DAC1 LDO PA  BB can support HPUE 26dBm with
Mux BUCK-BOOST APT APT mode.
switches
CBB CBK
DAC2
 BK supplies the TX power with its
own feedback loop and shared CBK.
LA2 TX2
Envelope2
Mux BK2
VBATT
1BB sharing challenge
BK1
TX1
DAC1 SWBB1 SWBK1
BB
DAC2 SWBB2 SWBK2

BK2
TX2
BK1
TX1
DAC1 SWBB1 SWBK1
BB
<Restrictions>
 TX1 transition cannot interrupt TX2
DAC2 SWBB2
SWBK2
communication.
BK2
TX2  Rush current of switches must be
avoided.
Capacitor swapping operation
BK1
VTX1 TX1
SWBB1 SWBK1
DAC1
BB
Main MIPI VBB VBK
Controller Interface
DAC2 SWBB2 SWBK2

DAC Sel.
SW
BK2
TX2
VTX2
SWAP_EN
Cap. Swap
Detector
VBB VBK VTX1 VTX2

TX(V) TX1 target voltage
TX2=BB TX2 target voltage
TX1=BK1
Time(s)
BK1
VTX1 TX1
SWBB1 SWBK1
DAC1
BB
Main MIPI VBB VBK
DAC2 SWBB2 SWBK2

DAC Sel.
SW
BK2
TX2
VTX2
SWAP_EN
Cap. Swap
Detector
VBB VBK VTX1 VTX2

TX(V) TX1 target voltage
TX2=BB TX2 target voltage
TX1=BK1
Capacitor swapping
Time(s)
BK1
VTX1 TX1
SWBB1 SWBK1
DAC1
BB
Main MIPI VBB VBK
DAC2 SWBB2 SWBK2

DAC Sel.
SW
BK2
TX2
VTX2
SWAP_EN
Cap. Swap
Detector
VBB VBK VTX1 VTX2

TX(V) TX1=BB
TX2=BB TX2=BK2
TX1=BK1
Time(s)
Outline
▪ Introduction
▪ Conclusion
Conventional Return-to-Ground(R2G) switching
VBATT VBB VBATT VBB
BB BB VSW
VBB
LA LA
VTX
VSW VBATT
VSW CAC CAC
VTX VTX Time(s)

@ VBB < VBATT @ VBB > VBATT ET operating waveform
Typical Return-to-Ground
Switching Switching
 Switching mode is changed when VBB is higher than VBATT.
 All the output power is supplied through BB, which includes conversion loss.
[3] J.-S. Paek, et al., “A -137 dBm/Hz Noise, 82% Efficiency AC-Coupled Hybrid Supply Modulator With Integrated Buck-Boost Converter,” IEEE J. Solid-State Circuits, vol. 51, no. 11,
pp. 2757-2768, Nov. 2016.
Proposed Return-to-Battery(R2B) switching
VBATT VBB VBATT VBB
BB BB
VBB
LA LA
VSW VTX
VSW VBATT
VSW CAC CAC
VSW
VTX VTX Time(s)

@ VTX < VBATT @ VTX > VBATT ET operating waveform
Typical Return-to-Battery
Switching Switching
 Switching mode is changed dynamically depending on envelope.
 R2B switching reduces the power from BB and conversion loss.
Outline
▪ Introduction
▪ Conclusion
1TX transition (APT-APT to ET-APT)
BK1
TX1
DAC1 SWBB1 SWBK1
BB
DAC2 SWBB2 SWBK2

BK2
TX2
BK1
TX1
DAC1 SWBB1 SWBK1
BB
DAC2 SWBB2
SWBK2
BK2
TX2
 No cross regulation when capacitor is swapped.

2TX transition (ET-APT to APT-APT)
BK1
TX1
DAC1 SWBB1 SWBK1
BB
DAC2 SWBB2
SWBK2
BK2
TX2
BK1
TX1
DAC1 SWBB1 SWBK1
BB
DAC2 SWBB2 SWBK2

BK2
TX2
 The SM achieves seamless transition of VTX1 and VTX2 by using BK1/BB/BK2.

ET operation
2TX ET operation waveform SM output and PAMiD output waveform

TX1:LTE 20MHz (100RB) LTE 40MHz (200RB) with LTE B41 carrier
TX2:LTE 1.4MHz (6RB) PAMiD: Power Amplifier Module with integrated Duplexer
SM efficiency (ET mode)
1RB 6RB 25RB 50RB 100RB 200RB
90
85 max 84.6%
SM efficiency (%)
80
75
VBATT=4.0V, RLOAD = 4.7Ω
70
RB: Resource Block
65 1RB=180kHz ~
200RB=36MHz
60
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SM output power (W)
 More than 80% maximum efficiency is achieved in each RB condition.

R2B switching
R2G_swtiching R2B_switching
90
VBATT=3.0V,
LTE1.4MHz (6RB),
Rload=4.7Ω 2.3%
SM efficiency (%)
85
80 1.6%
75
Boosted supply
70
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SM output power (W)
 Typical switching and R2B switching dynamically change with envelope.

 R2B switching improves efficiency by 2.3%.
ET-APT performance with PAMiD
DC APT ET
3.0
VBATT=4.0V, 800mW@ 26dBm
2.5 LTE10MHz
(50RB)
DC supply power (W)

2.0
1.5
Boosted
1.0 supply by BB
200mW@ 20dBm
0.5
ET dynamic range
0.0
14 16 18 20 22 24 26 28
PAMiD output power (dBm)
 PAMiD output power reaches 26.4dBm by BB.

 ET saves 800mW compared to APT at 26dBm.
PA output spectrum (B41)
No.
RF-PA Max. SM SM noise Carrier RF E-UTRA Die area Tech.
Supporting Operation PAE
Ref. of
Power ET BW effi. @30/95MHz freq. Pout ACLR / TX node
Protocol mode
TXClass (MHz) (%) (dBm/Hz) (GHz) (dBm) (%) (dBc) (mm2/ea) (nm)
This Class 2 LTE, WCDMA,
2 ET, APT 40 83 -133 / -142 2.593 29.4* 42.7 -38.2 3.0 90
work Class 3 GSM
LTE, WCDMA,
[2] 1 Class 3 ET, APT 40 83 -136 / -141 1.950 26.5^ 42.1 -41.2 4.0 130
GSM
[3] 1 Class 3 LTE, WCDMA ET, APT 10 82 -130 / -139 1.747 27.0 42.6 -39.0 5.0 130
[4] 1 Class 3 LTE ET 20 83 - 2.535 28.3 48.0 -41.4 1.5 180
[5] 1 Class 3 LTE ET 20 88.7" - 2.400 23.9 35.7 -32.0 3.5 65
* duplexer 3.0dB loss is added. ^ duplexer 2.5dB loss is added. " with envelope waveform shaping
Die micrograph
 Die area: 6.0mm2 (2.54×2.54mm)

 90nm CMOS process
 49pin wafer level chip scale
package (WLCSP)
 BB occupies 20% of die
 40% smaller Area/TX than Ref.[3]
Conclusion
 Proposed 2TX SM architecture reduces die size, passive components,

and PCB area while supporting both UL-CA and HPUE.
 Each TX path operates independently for combined ET/APT mode

with the capacitor swapping technique.
 ET with Return-to-Battery switching technique supports HPUE with

high efficiency.
94% Power-Recycle and Near-Zero Driving-
Dead-Zone N-type Low-Dropout Regulator
with 20mV Undershoot at Short-Period Load
Transient of Flash Memory in Smart Phone
Speaker: Wei-Chung Chen
Author: Wei-Chung Chen, Tzu-Chi Huang, Chao-Chang Chiu,
Chih-Wei Chang, Kuo-Chun Hsu
Affiliation: MediaTek, Taiwan
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 1 of 20
Outline
 Motivation
 Open-loop status of N-type LDO
 Short-period H-L-H load transient
 Proposed N-type LDO
 Virtual-ground-based dynamic-power-recycling
(VGDPR) Buffer
 Anti-ringing feed-forward (ARFF) Compensation
 Measurement Result
 Performance Summary & Conclusion
Outline
 Motivation
(VGDPR) Buffer
Motivation
LDO with N-type PowerMOS
 Widely used in Power Management IC (PMIC)
 Two power domain
 VSYS: BUCK
 VBAT: Battery
*For easier understanding,
let’s assume Vth=0 Motivation
Design Challenge of Load Transient when using N-type LDO
 Close-loop Status  Open-loop Status

 VGATE>VOUT  VGATE < VOUT
 PowerMOS is active  No reaction of driving current
 VOUT is regulated through feedback (IOUT=0)
 Suffering large undershoot
Motivation
 Characteristics of Load
 Flash Memory :
• eMMC/ UFS/ DRAM
• Frequency data access
 Short-period H-L-H load transient
• Open-loop status in conventional N-type LDO
• Large undershoot
Motivation
Motivation
Motivation
Outline
 Motivation
(VGDPR) Buffer
Proposed N-type LDO
• Fast & Efficient & Simple
Proposed VGDPR Buffer
Conventional Proposed
Buffer Buffer
Low Output
Yes Yes
Impedance
Min. VGATE
0 VOUT
Voltage Level
Keep
No Yes
Close-loop Status
Complexity
High Low
for Dynamic IQ
Power Recycling No Yes
ARFF Compensation
for Transient Improvement
Conventional
Proposed
Miller
ARFF
Compensation
Dominant
Yes Yes
Pole
Slew Rrate
No Yes
Improvement
Feed-forward
Yes Yes
Path
Smooth
No Yes
Recovery
ARFF Compensation
for Transient Improvement
Conventional
Proposed
Miller
ARFF
Compensation
Dominant
Yes Yes
Pole
Slew Rrate
No Yes
Improvement
Feed-forward
Yes Yes
Path
Smooth
No Yes
Recovery
Outline
 Motivation
(VGDPR) Buffer
Process : UMC 0.15μm 5V-CMOS,
VBAT=3.8V , VSYS=1.2V
VOUT=1V COUT=1µF Measurement Result
(a) L-H Load transient at steady-state VOUT (b) L-H Load transient at overshoot VOUT
(a) and (b) have similar good performance

Outline
 Motivation
(VGDPR) Buffer
Performance Summary
Extra 200μA is
recycled to VOUT
[5] M. Al-Shyoukh, et al., “A transient-enhanced low quiescent current low-dropout regulator with buffer impedance
attenuation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732–1742, Aug. 2007.
Conclusion
 Proposed VGDPR Buffer
 Fast Transient: using VOUT as virtual ground to avoid open-loop status
 High Efficiency: power recycle and dynamic IQ
 Dynamic IQ: benefit compensation and slew rate
• ARFF Compensation Tactic
 Feed-forward path
 Smooth recovery
Thanks for your attention
An On-Chip Resonant-Gate-Drive
Switched-Capacitor Converter
for Near-Threshold Computing
Moataz Abdelfattah1,2, Muhammad Swilam1, Brian Dupaix3, Shane

Smith1, Ayman Fayed1, Waleed Khalil1
1The
Ohio State University, Columbus, OH
2Qualcomm Inc., San Diego, CA
3Air Force Research Laboratory, Sensors Directorate , Dayton, OH
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 1 of 36
Outline
• Introduction
– Motivation: Near-Threshold Computing
– Switched-Capacitor (SC) Converter: Challenge
• Proposed Resonant Gate Drive (RGD) for SC converter
• Conclusion
© 2018 IEEE
Near-Threshold (NT) Computing
Standard Near-Threshold
Energy
- Nominal Supply - NT supply
Efficient (≈0.4-0.6V)
(≈1.2V)
- Few cores - Many cores
• Requirements for the power supply (PS):

– Integrated on-chip
– High current density
– Low output voltage
© 2018 IEEE
Near-Threshold (NT) Computing
Standard Near-Threshold
Energy
- Nominal Supply - NT supply
Efficient (≈0.4-0.6V)
(≈1.2V)
- Few cores - Many cores
• Requirements for the power supply (PS):

– Integrated on-chip SC Converter is most attractive
– High current density
– Low output voltage
© 2018 IEEE
Outline
• Introduction
– Motivation: Near-Threshold Computing
– Switched-Capacitor (SC) Converter: Challenge
• Conclusion
© 2018 IEEE
SC Challenge: Efficiency vs. Current Density
Max Achievable
Heavy Loads
Load Current (log)

Ref: “H-P.Le, JSSC 2011”
© 2018 IEEE
SC Challenge: Efficiency vs. Current Density
Max Achievable
Cfly
Area Current Density
Load Current (log)

Ref: “H-P.Le, JSSC 2011”
© 2018 IEEE
This Work: Resonant Gate Drive (RGD)
Max Achievable
Proposed
RGD
Minimal
Maintain Current
impact
Density
on Area
Load Current (log)
© 2018 IEEE
Outline
• Introduction

– Area-Efficient RGD  Concept
– SC-RGD Architecture
• Conclusion
© 2018 IEEE
Proposed RGD Scheme – Concept
Simultaneous
Gate Transition
Two power switches with complementary gate signals

© 2018 IEEE
GP
GN
Resonance pulse: energy recycled between gate caps

© 2018 IEEE
Restore switches: restore voltage levels to full rail

© 2018 IEEE
Proposed RGD – Impact on Losses
Resonant gate drive Conventional CMOS drive
Energy
from supply
Recycled
energy
( )
Reduced SW Losses
© 2018 IEEE
Proposed RGD – Silicon Area
R L
( )
CGP CGN

: quality factor at resonance frequency (1⁄ )

© 2018 IEEE
R L
( )
CGP CGN

Gate Cap (≈ pF)

© 2018 IEEE
( ) On-Chip Integration

Minimal Area Overhead
Can use (≈ pH) and get sufficient Q
Gate Cap (≈ pF)

© 2018 IEEE
Proposed RGD – Inductor Sharing
GP
GN
Time interleaved gate transitions

© 2018 IEEE
GP
GN
Time interleaved gate transitions

© 2018 IEEE
GP
GN
Multi-Phase Support Time interleaved gate transitions

© 2018 IEEE
Outline
• Introduction

– Area-Efficient RGD  Concept
– SC-RGD Architecture
• Conclusion
© 2018 IEEE
Single-Phase 2:1 SC-RGD
Introduced Conventional
RGD 2:1 Power Stage
© 2018 IEEE
© 2018 IEEE
Dead Time
- Gate transitions separated

by dead time
- Inductor can be shared
© 2018 IEEE
Single-Phase 2:1 SC-RGD – Losses
( )
8%
RGD
( )
Optimize design parameters
/
( ) ( )
Pushing Efficiency limit

© 2018 IEEE
4-Phase Interleaved SC-RGD
© 2018 IEEE
4-Phase Interleaved SC-RGD
CLK
CLK1
CLK2
CLK3
CLK4
Inductor shared across Time-interleaved

16 power switches
© 2018 IEEE
Outline
• Introduction
• Switched-Capacitor with Resonant Gate Drive (SC-RGD)
• Conclusion
© 2018 IEEE
Die Micrograph
100 pH inductor:
Active area: 0.32 mm2 5% of active area
- 45nm SOI CMOS

- 2.5 nF Cfly
- No Cout
On-chip load
© 2018 IEEE
Transient Performance
Vin = 1V
Vout = 0.4V
fsw = 300 KHz
© 2018 IEEE
Efficiency
Vin = 1V
Vout = 0.4V
© 2018 IEEE
Efficiency
Vin = 1V
Vout = 0.4V
© 2018 IEEE
Comparison to State of the Art
[Andersen ISSCC’ 14]
[Andersen ISSCC’ 15]
[Pique ISSCC’ 12] [Le ISSCC’ 10]

[Butzen ISSCC’ 17]
[Le JSSC’ 11]

[Le ISSCC’ 10]
[Souvignet TPE’ 16]
[Jain JSSC’ 15]
- 3X higher current density
[Jiang ISSCC’ 15]
[Lu ISSCC’ 15]

[Jain JSSC’ 14]
[Jain JSSC’ 14]
- Better efficiency
[Somasekhar VLSI’ 09]
[Jiang ISSCC’ 15]
[Meyvaert TPE’ 13]
[Meyvaert ESSCIRC’ 11]
-1 0 1
© 2018 IEEE
Comparison to State of the Art
- 3X higher current density

- Better efficiency
3X
© 2018 IEEE
Outline
• Introduction
• Switched-Capacitor with Resonant Gate Drive (SC-RGD)
• Conclusion
© 2018 IEEE
Conclusion
• Proposed RGD scheme:
– Reduces losses
– Minimal Area Overhead
– Inductor sharing  Multi-phase Support
• Key Design Features:

– 70% efficiency at 0.9 A/mm2, 0.4 V output
– Attractive for Near-Threshold Computing
© 2018 IEEE
Thank You!
Questions?
© 2018 IEEE

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ISSCC

conversion ratios (VCRs) Power density (mW/mm2)

Fine-grained VCR (FVCR)

85 ISSCC’14 (15) (45) MIM / MOM Cfly for low parasitic

85 ISSCC’14 (15) (45) Dickson Topology

85 ISSCC’14 (15) (45) Q-conduction (RSSL)

 Binary Recursive and Negator topologies: suboptimal parasitic loss

• ∆VCB: VIN or VOUT − VIN

Dickson Cell (DC) (boost) Q-path Folding Cell (QFC) (boost)

Si,O = Si,I + VIN − biVOUT

bi = 0: Si,O = Si,I + VIN

Algorithm for coefficient bi & mi

Applying the LBR.

C1 implementation C2~n implementation depends

• 10 main + 10 auxiliary cells • Dual-branch interleaved

• Top plate P/N switches are enabled in buck/boost, respectively.

• ST3 driving challenge ― no fixed high/low reference terminal

enP enP VGP180

• Similar performance for VIN = 0.26 ~ 2.4V @ VOUT = 1.2V,

10:11 2:3 5:6

 MC + AC partitionable power stage

 RSBD switch driver

 Macao Science and Technology Development Fund (FDCT)

 Multi-Year Research Grant of University of Macau

Thank you for your attention!

Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, and Changsik Yoo

Hanyang University, Seoul, Korea

 Fast transient response

– Phase difference between CLKSET and

• With series-R • VCO2

• Type-II compensation with high- • Type-II compensation with only

• Voltage comparator • Phase detector w/ negligible delay

∆ <∆ for all duty

• Fully differential (latency reduced)

• Offset of GMS and GMI  VOUT error

[S. J. Kim et al., ISSCC 2015]

Process 65-nm CMOS

Max. load current 0.6-A 93ns Duty=93%

• 3.5-μs settling time for up/down step change of IOUT

• 3-μs/3.5-μs tracking time for up/down step change of VREF

A. Salimath*, E. Bonizzoni*, E. Botti#, G. Gonano#,

 PDiss and efficiency of the

Iboost & Ireg-low (mA)

 Switching SIMO at 0.3-0.5MHz contributes to switching-noise in MF-AM band.

Load currents at Iboost Ireg-low Ifloat 2. VfloatH and VfloatL track

ILinear Reg (mA)

* Error Matrix as in Belloni et. al, ISSCC 2008.

* Error Matrix as in Belloni et. al, ISSCC 2008.

 110-nm BCD Process

1.6V VfloatH 1.8V

Load Transient= 0.16 mV/mA

Peak Efficiency= 86%

 What is the impact of SIMO converter (switching regulator) on

 What is the effective reduction in the system power dissipation

Vbat=14.4 V, FIn= 1kHz, Fs= 192kHz

Vbat=14.4 V, FIn= 1kHz, Fs= 192kHz

 Proposed Step-Up/Down DC-DC Converter

 Li-Ion Battery shows the highest energy density

 The voltage of Li-Ion battery decreases with time

 Buck-operation by using dependent voltage sources

 Fast-response step-Up/Down Converter (FUDC)

 Charge-pump + buck converter

 Flying capacitors : Charged up to ½ VBAT respectively

A. Salimath, E. Bonizzoni, E. Botti#, G. Gonano#,