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DATE : 14/11/2017

TITLE : FIELD EFFECT TRANSISTOR (FET)


OBJECTIVES :
1. To obtain Field Effect Transistor static characteristic
measurement.
2. To determine the relationship between Current, I and
Voltage, V for the Field Effect Transistor .
INTRODUCTION :

The Field Effect Transistor are ‘Unipolar Devices’ that operates only with one
type of charge carrier. In Bipolar Junction Transistor (BJT), we discuss that it used
both electrons and hole current making the terms Bipolar reliable.

FET are voltage controlled devices,where the BJT are current controlled
devices. FET basically have three terminals, such as Drain (D), Source (S), and Gate
(G) which are equivalent to the collector, base and emitter in BJT. In BJT Transistor
the output current is controlled by the input current which is applied to the base, but in
FET transistor the output current is controlled by the input voltage applied to the Gate
(G) terminal. The “Field Effect” term relates to the depletion region formed in the
channel as a result of voltage applied on one of its terminal (Gate) and it operates only
on either N-Channel (electrons) or P-Channel (holes).

In FET, it used the voltage that is applied to their input terminal, called the Gate
to control the current flowing through them resuting in the output current are being
proportional to the input voltage.

Diagram 1
The N-Channel and P-Channel of FET.
N-Channel : The channel is doped with donor impurities meaning that
the flow of current through the channel is negative in
the form of electrons.
P-Channel : The channel is doped with the acceptor impurities due to
this the flowing through this channel is positive (holes).
PROCEDURE : The experiment was setup as shown in the Diagram 2 below.

Id

G Power Supply
15-16V

VDS
VGS=0

Diagram 2
Experiment Setup

RESULTS :
Vgs (V) 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2
Vds (V) Id (mA)
0 0.05 0.04 0.03 0.03 0.03 0.02 0.02
0.2 1.05 1.08 0.79 0.73 0.65 0.45 0.37
0.4 1.75 1.56 1.24 1.12 0.89 0.71 0.5
0.6 2.45 2.02 1.62 1.51 1.17 0.91 0.63
0.8 2.87 2.39 2.01 1.79 1.34 1.02 0.68
1 3.29 2.77 2.22 1.93 1.47 1.08 0.72
1.2 3.67 3.06 2.41 2.05 1.56 1.11 0.73
1.5 4.09 3.31 2.53 2.19 1.64 1.15 0.76
2 4.42 3.53 2.7 2.3 1.71 1.19 0.78
4 4.79 3.79 2.86 2.44 1.79 1.25 0.83
10 4.92 3.92 2.96 2.54 1.87 1.32 0.87
16 4.94 3.95 3 2.57 1.9 1.35 0.89
Graph of I against V
6

4
Current, I

0
0 2 4 6 8 10 12 14 16 18
Voltage, V

Series1 Series2 Series3 Series4 Series5 Series6 Series7 Series8

DISCUSSION :
1.

A  B : OHMIC REGION
This is the region where voltage and current relationship follows the
Ohm’s Law.
When 𝑉𝐷𝐷 is increase from 0A, 𝐼𝐷 will increase proportionally. The channel
resistence is essentially constant because the depletion region is not large
enough to have the significant effect.

B  C : PINCH OFF REGION

When 𝑉𝐷𝑆 increases from B to C, the reverse bias voltage from gate to drain
(𝑉𝐺𝐷 ) will produces a large depletion region which is large enough to offset
the increases in 𝑉𝐷𝑆 , keeping the 𝐼𝐷 relatively constant.

C : BREAKDOWN REGION

JFET begins to breakdown where the 𝐼𝐷 increases rapidly and it is an


irreversible breakdown and FET cannot be operated in this region as
resulting damage to the devices.

CONCLUSION : The Field Effect Transistor static characteristic is obtained due


to the variefying values of voltage, 𝑉𝐺𝑆 that is applied into the
input terminal. The relationship between current 𝐼𝐷 and the
Voltage , 𝑉𝐷𝑆 have been determined and it is found that these
relationship is similar to the BJT corresponding to relationship of
𝐼𝐶 against 𝑉𝐶𝐸 .