928 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO.

UITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 12, DECEMBER 2003

A New Low Voltage Precision CMOS Current

Reference With No External Components
Rasoul Dehghani and S. M. Atarodi

Abstract—A novel current reference with low temperature and

m
supply sensitivity and without any external component has been
developed in a 0.25 mixed-mode process. The circuit is based
on a bandgap reference (BGR) voltage and a CMOS circuit sim-
ilar to a beta multiplier. An NMOS transistor in triode region has
been used in place of a resistor in conventional beta multiplier to
achieve a current which has a negative temperature coefficient and
only oxide thickness dependent. The BGR voltage has a positive
temperature coefficient to cancel the negative temperature coeffi-
cient of the beta multiplier. The simulation results using Bsim3v3

20 C +100 C
model show max-to-min fluctuation of less than 1% over a temper-

30%
ature range of to and a supply voltage range of
1.4 V to 3 V with tolerance for all of the used on-chip resis-
tors. The maximum current variation is slightly less than the oxide
thickness variation in the process corners.
Fig. 1. Architecture of the proposed current reference.

I. INTRODUCTION II. CURRENT REFERENCE ARCHITECTURE

C URRENT reference as an essential block in analog IC’s

is needed in many analog signal processing applications
such as operational amplifier and data converter bias circuits.
The proposed architecture is composed of two main parts as
shown in Fig. 1. The first part is a BGR circuit with a positive
temperature coefficient output voltage Vr and the second part
Reference currents are often implemented by applying a is a quasi CMOS beta multiplier in which the resistor in con-
bandgap voltage reference across a resistor. The main problem ventional one has been replaced by an NMOS transistor (M1).
corresponding to this method concerns the used resistor. The drain-source voltage of M1 is controlled by Vr in a nega-
On-chip resistors are typically highly process-dependent, tive feedback loop established by the operational amplifier OP.
while off-chip resistors are not suitable due to cost and area The voltage Vr is less than M1 drain-source saturation voltage
considerations. Replacing resistor with its switched capacitor ( ), therefore, M1 operates in triode region. For M1 with
equivalent requires a separate frequency clock source and adequately long channel length, the drain current can be written
on-chip capacitors that leads to complexity and large area [1], as follows
[2]. Added digital noise to the circuit is another disadvantage
of the switched capacitor method. (1)
This work circumvents the need for an accurate on-chip re-
sistor without using any external component. In Section II, gen- Where: . is the inversion layer mo-
eral architecture of the proposed current reference is reviewed bility, is the gate oxide capacitance per unit area, is the
and the corresponding relations are derived. Section III is de- threshold voltage, and are the width and length of ,
voted to the description of the current reference components in- respectively. On the other hand, diode connected is in satu-
cluding BGR circuit, quasi CMOS beta multiplier, operational ration region and its current is
amplifiers, and startup circuit. The simulation results are pre-
sented in Section IV and conclusion is made in Section V. (2)

Noting that , and , from (1) and

(2) the following relation is derived
Manuscript received February 18, 2003. The authors would like to express
their thanks to EMAD SEMICON CO. for financial supports. This paper was (3)
recommended by Associate Editor B. Razavi.
The authors are with the Department of Electrical Engineering, Sharif Uni- where and is the output current. For
versity of Technology, Tehran, Iran1 (e-mail: dehghani@mehr.sharif.edu). we have
Digital Object Identifier 10.1109/TCSII.2003.820239
1Note: New regulations imposed by the U.S. Government placed severe re-
(4)
strictions on the review process for this paper and prevented the editorial staff
of the journal from making any corrections to the paper. Please see the Editorial is a process independent voltage and has a low depen-
in this issue for more details. dency on process variations, thus the oxide thickness is the only
1057-7130/03$17.00 © 2003 IEEE

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DEHGHANI AND ATARODI: A NEW LOW VOLTAGE PRECISION CMOS CURRENT REFERENCE WITH NO EXTERNAL COMPONENTS 929

Fig. 2. Bandgap reference voltage with positive temperature coefficient.

main process parameter which affects the output current through

Fig. 3. Quasi CMOS beta multiplier circuit.
in (4). In order to have an with approximately zero tem-
perature coefficient, from (4) we must have
get (6), assuming M7-M8 and M9-M10 have the same size, the
(5) change in with respect to temperature is obtained as

Using , after some manipulations on (5),

we obtain the relative variation of with respect to temperature
as follows (8)

(6) Where . Letting we will have

Where . Therefore, the required BGR temperature

(9)
coefficient must be about according to (5). In
this design, is less than the saturation voltage of M1 so it is
in triode region. Resistances in BGR circuit are determined to Substituting (8) into (9), results in
satisfy (6) as described in the next section.

III. CIRCUIT DESCRIPTION

A. Bandgap Reference
The adopted bandgap reference circuit is shown in Fig. 2.
(10)
Transistors - provide the bias voltages and for
op amps and quasi CMOS beta multiplier, respectively. Op- amp
OP, transistors M5-M8 and resistors R1-R4 (all with the same The term in general form of in (8), (9) and
resistance) constitute a feedback loop through which the volt- (10) is the temperature coefficient of resistivity (TCR) and de-
ages Ve1 and Ve are forced to be equal. As a consequence, the termined by process. In the process used in this design, -
current through the series connected R3 and R4 is proportional and - are n-well and -poly (without silicide) resistors
to the emitter-base voltage and the current through the resistor with sheet resistance of 1100 and 180 and TCR of
R5 to the difference of two emitter-base voltages. The first cur- and , respectively.
rent component has a negative temperature coefficient due to In Fig. 2, if is too low, - should be very large to avoid
the corresponding coefficient for emitter-base voltage and the loading emitter-base voltages in and which results in
second one has a positive temperature coefficient. The drain cur- large area for these resistors. Therefore, a reasonable value must
rent of M5 and M6 (M7 and M8) is the sum of these components. be set for - to compromise the area and power dissipation.
Using , we can write the total current
as follows B. Quasi CMOS Beta Multiplier
The schematic diagram of the circuit is shown in Fig. 3. This
(7) circuit operates like a conventional gm-constant circuit [4] in
which the source resistor has been replaced by an NMOS tran-
Where: is thermal voltage ( sistor ( ) in triode region. As proved in Section II, proper
is Boltzman’s constant and is sizing of and sets the current independent of the
electron charge) and is the ratio of the emitter areas of threshold voltage of the MOS transistors. Using cascode devices
and . The generated current is mirrored through M9-M10 with long-channel for and M7 (M4 and M6), we achieve a
and establishes a reference voltage across . In order to high compliance current source. The structure of the operational

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930 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 12, DECEMBER 2003

TABLE I
SIMULATION RESULTS OF THE CURRENT REFERENCE VS. TEMPERATURE, IN
ALL PROCESS CORNERS

Fig. 4. PMOS input folded cascode op amp.

TABLE II
SIMULATION RESULTS OF THE CURRENT REFERENCE VS. SUPPLY VOLTAGE, IN
ALL PROCESS CORNERS.

current to the gate of in Fig. 3 at startup and forcing

Fig. 5. NMOS input folded cascode op amp. and to be equal.

amplifiers used in BGR and quasi CMOS beta multiplier circuits IV. SIMULATION RESULTS
is described in the next section. The current reference simulation was carried out using
Bsim3v3 models for a 0.25 CMOS process. Various
C. Operational Amplifiers
precise simulations were performed to evaluate the effects of
The schematic of the op amp used in the BGR circuit is shown the process variation on the generated current in five different
in Fig. 4. This structure is appropriate for low level input volt- process corners including TT (Typical model), SS (Slow-Slow),
ages, thus it is also used for in quasi beta multiplier. It FF (Fast-Fast), FS (Fast-Slow) and SF (Slow-Fast). The toler-
consists of a PMOS-input folded cascode as the first stage and a ance of was considered for the resistance of to
cascode output stage in the second stage. Cascode compensation in all corners. DC simulation results over a temperature range
was used to improve the bandwidth in comparison with Miller from to , for nominal and tolerance in
compensation [3]. Simulations show that applying compensa- resistances, in all process corners and for the supply voltage
tion simultaneously to two source nodes of PMOS and NMOS have been summarized in Table I.
transistors in folded cascode stage reduces the total capacitance In Table I is the output current at (as
of and to achieve a proper phase margin. Exploiting a cas- midrange temperature) and is the maximum change
code topology in the output stage has the following advantages: of the output current in temperature range for each process
it simplifies the bias circuit, increases the total op amp gain and corner. As can be seen from Table I in each process corner, the
reduces the op amp output sensitivity to the supply noise. maximum variation in is less than 0.7% for change in
in Fig. 3 has the same structure as , but with NMOS-input resistance and is about 0.9% for the temperature change from
folded cascode as shown in Fig. 5. to in the worst case (FF, ).
The maximum change in is related to transition from TT to
D. Startup Circuit SS or FF in which both threshold voltage and oxide thickness
An innovative simple startup circuit has been exploited whose change. As mentioned before, this variation is related to the
function is described as follows. The BGR circuit has two stable oxide thickness variation in these process corners. In the used
operating points: the desired one and the unwanted zero condi- 0.25 CMOS process, oxide thickness variation from TT to
tion. If the circuit in Fig. 2 enters the undesired point, voltages SS or FF is . The results obtained from Table I show a
and will go to zero and approaches to [5]. In maximum of variation in from TT to SS
Fig. 2, gate, source and drain of Msn are connected to the volt- (FF) i.e., even slightly less than thickness variation.
ages , and , respectively. As a result, since at startup DC simulation results when supply voltage is swept
Ve is greater than Ve1, Msn turns on, pulling down and from 1.4 V to 3 V, for three different temperatures
causing and to turn on. When the BGR circuit starts its ( ), in all process corners and with
normal operation, OP makes voltages and equal. Con- nominal values for to are depicted in Table II.
sequently, Msn turns off in steady state. The PMOS transistor is defined as the output current at ,
Msp helps to start the quasi beta multiplier circuit by injecting is the maximum change of the output current in supply voltage

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DEHGHANI AND ATARODI: A NEW LOW VOLTAGE PRECISION CMOS CURRENT REFERENCE WITH NO EXTERNAL COMPONENTS 931

Fig. 6. Simulated output current vs. temperature for different resistances.

Fig. 8. Simulated output current vs. time in various temperatures and process
Fig. 7. Simulated output current vs. supply voltage for different temperatures. corners.

TABLE III by applying a step function with 1 rise time for supply and
SUMMARIZED SPECIFICATIONS OF THE CURRENT REFERENCE OP AMPS. performing a transient analysis in all process corners, tempera-
ture range ( to ) and maximum tolerance in re-
sistance ( ) which some of them are shown in
Fig. 8.

range for each process corner. It can be found that the maximum
current change over a 1.4 V to 3 V supply range is less than
0.39% in the worst case (which occurs for SS,
This low supply dependency of the output current is because of
the long channel cascode devices used in the circuit.
The plot of the output current vs. temperature is shown for
and in Fig. 6. As can be seen,
large absolute error in resistance ( ) has a little effect on
the output current if the matching among resistors is good by
proper layout. Fig. 7 shows the output current characteristics
with respect to the supply voltage at three different tempera-
tures.
The summarized specifications of two types operational am-
plifiers used in the circuit are given in Table III. These op amps
have been designed as low power as possible to reduce the total
power consumption of the current reference circuit.
The ability of the startup circuit to force the current refer-
ence circuit to settle in its proper stable point was evaluated
V. CONCLISION
A new current reference with low temperature and voltage
sensitivity was designed. The circuit does not require any ex-
ternal component and is robust against large absolute error in
on-chip resistance. The output current is only oxide thickness
dependent and is stable for a wide variation range in tempera-
ture and supply voltage. The power consumption of the whole
current reference is 311 for a supply voltage of 1.5 V.
).
REFERENCES
[1] P. Bernardson, “Precision, temperature and supply independent CMOS
current source with no external components,” Electronics Letters, vol.
38, no. 25, December 2002.
[2] S. Q. Malik, M. E. Schlarmanm, and R. L. Geiger, “A low temper-
ature sensitivity switched-capacitor current reference,” in Proc. 15’th
ECCTD, vol. 1, Espoo, Finland, Aug 28–31, 2001, pp. 269–272.
[3] B. Vaz, N. Paulino, J. Goes, R. Costa, R. Tavares, and A. S. Garçao, “De-
sign of low-voltage CMOS pipelined ADC’s using 1 pico-Joule of en-
ergy per conversion,” in Circuits and Systems, 2002. ISCAS 2002. IEEE
International Symposium on, vol. 1, 2002, pp. 921–924.
[4] B. Razavi, Design of Analog CMOS Integrated Circuits. Boston, MA:
McGraw-Hill, 2001, pp. 392–393.
[5] K. N. Leung and P. K. T. Mok, “A sub-1-V 15 0 ppm= C CMOS
bandgap voltage reference without requiring low threshold voltage de-
vice ,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 526–530, April
2002.

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932 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 12, DECEMBER 2003
Rasoul Dehghani was born in Esfahan, Iran, in 1965. He received the B.Sc. and
M.Sc. degrees in electrical engineering from Sharif University of Technology,
SUT, Tehran, Iran, in 1988 and 1991, respectively.
From 1987 to 1991, he worked on developing several blocks for the receive
chain of a wireless communication system with the SUT. From 1991 to 1998,
he designed and implemented various electronic circuits with communicational
and industrial applications. Since 1998, he has worked as a senior design en-
gineer with Emad Co. while working toward the Ph.D. degree at the SUT. His
current research interests include RF IC design for wireless communication, fre-
quency synthesis, and low-voltage and low-power circuits.
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Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Tech-
nology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering
from the University of California, Irvine, in 1987. He received the Ph.D. degree
from the University of Southern California (USC) on the subject of analog IC
design in 1993.
From 1993 to 1996 he worked with Linear Technology Corporation as a se-
nior analog design engineer. Since then, he has been consulting with different
IC companies. He is currently a visiting professor at Sharif University of Tech-
nology. He has published more than 30 technical papers in the area of analog
and mixed-signal integrated circuit design as well as analog CAD tools.