VHDL for SR Flip-flop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SRff is
Port ( S : in std_logic;
R : in std_logic;
Q : inout std_logic;
QN : inout std_logic);
end SRff;
architecture Behavior of SRff is
begin
process (S,R,Q,QN)
begin
Q <= R NOR QN;
QN <= S NOR Q;
end process;
end Behavior;
VHDL for JK Flip flop
library IEEE; process(CLK,J,K)
use IEEE.STD_LOGIC_1164.ALL; begin
use IEEE.STD_LOGIC_ARITH.ALL; if (CLK='1' and CLK'event)
use then
if(J='0' and K='0') then
IEEE.STD_LOGIC_UNSIGNED.ALL;
Q <=Q;
QN <=QN;
entity JKff1 is elsif(J='0' and K='1') then
Port ( J : in std_logic; Q <= ‘0';
K : in std_logic; QN <= ‘1';
CLK : in std_logic; elsif(J='1' and K='0') then
Q : inout std_logic; Q <= ‘1';
QN : inout std_logic); QN <= ‘0';
end JKff1; elsif(J='1' and K='1') then
Q <= NOT Q;
architecture Behaviorof JKff1 is
QN <= NOT QN;
begin end if;
end if;
end process;
end Behavior;
VHDL for D Flip-flop

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY Dff IS
PORT ( D, Clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END Dff ;

ARCHITECTURE Behavior OF Dff IS

BEGIN
PROCESS ( Clk )
BEGIN
IF Clk ‘EVENT AND Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
VHDL for T Flip flop
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Tff is
Port ( T : in std_logic;
CLOCK : in std_logic;
Q : inout std_logic;
QN : out std_logic);
END Tff;
ARCHITECTURE Behavior OF Tff IS
BEGIN
PROCESS(CLOCK)
BEGIN
IF (CLOCK = '0' and CLOCK'event) THEN
Q <= (T AND (NOT Q)) OR ((NOT T) AND Q);
END IF;
QN <= NOT Q;
END PROCESS;
END Behavior: