Truth Tables

Provides a listing of every possible combination of values of binary inputs to a digital circuit and
the corresponding outputs.

In digital circuits, T and F are represented by voltage levels:

- The transistor-transistor logic (TTL) 74LS family of digital integrated circuits produces 2 voltage
levels

+ < .5V which represents low voltage L (0) and,

+ > 2.7V which represents high voltage H (1) for the digital device

The radix (or base) of the number system is the total number of digits allowed in the number
system.

Decimal-to-Binary Conversion

1. Separate the decimal number into whole and fraction portions.

2. To convert the whole number portion to binary, use successive division by 2 until the
quotient is 0. The remainders form the answer, with the first remainder as the least
significant bit (LSB) and the last as the most significant bit (MSB).

Example: Convert 179 10 to binary:

179 / 2 = 89 remainder 1 (LSB)

/ 2 = 44 remainder 1

/ 2 = 22 remainder 0

/ 2 = 11 remainder 0

/ 2 = 5 remainder 1

/ 2 = 2 remainder 1

/ 2 = 1 remainder 0

/ 2 = 0 remainder 1 (MSB)

17910 = 101100112

3. To convert decimal fractions to binary, repeated multiplication by 2 is used, until the

 fractional product is 0 (or until the desired number of binary places). The whole digits of the
multiplication results produce the answer, with the first as the MSB, and the last as the LSB.

Example: Convert 0.312510 to binary

Result Digit

.3125 × 2 = 0.625 0 (MSB)

.625 ×2 = 1.25 1

.25 ×2 = 0.50 0

.5 ×2 = 1.0 1 (LSB)

0.312510 = .01012

Conversion between Number Systems Summary

 Radix-r to decimal:

 Multiply digits with their corresponding weights and add

 Decimal to binary (radix 2)

 Whole numbers: repeated division by 2

 Fractions: repeated multiplication by 2

 Decimal to radix-r

 Whole numbers: repeated division by r

 Fractions: repeated multiplication by r

 Binary to Octal

 Substitute groups of three bits with corresponding octal digit.

 Binary to Hexadecimal

 Substitute groups of four bits with corresponding hexadecimal

digit.

Binary Arithmectic Operations Subtracstion

Two binary numbers are subtracted by subtracting each pair of bits together with borrowing,
where needed.
 0 1 0 1

0 0 1 1

0 1 -1 0

Example:

01111100

11100101

- 00101110

10110111

Negative Binary Number Representations

Signed-Magnitude Representation:

 For an n-bit binary number:

Use the first bit (most significant bit, MSB) position to represent the sign where 0 is positive
and 1 is negative.

Ex.

1 1 1 1 1 1 1 1 2 = - 12710

Sign Magnitude

 Remaining n-1 bits represent the magnitude which may range from:

-2(n-1) + 1 to 2(n-1) - 1

 This scheme has two representations for 0; i.e., both positive and negative 0: for 8 bits:
00000000, 10000000

 Arithmetic under this scheme uses the sign bit to indicate the nature of the operation and
the sign of the result, but the sign bit is not used as part of the arithmetic.

Two’s complement representation:

 MSB is the sign (MSB = 1 indicates a negative number)

 To negate a number -> complement all bits and add 1

 X plus the complement of X = 0

 There is one unique 0

 Positive numbers have 0 as their leading bit (MSB);

While negatives have 1 as their MSB.

 The range for an n-bit binary in 2’s complement representation is:

From -2(n-1) to 2(n-1) - 1

 Subtraction is done by addition to the 2’s complement of the number

 An n-bit 2’s complement number can converted to an m-bit number where m>n by
appending m-n copies of the sign bit to the left of the number. This proceses is calld sign
extension.

One’s complement representation:

 MSB is the sign (MSB = 1 indicates a negative number)

 Negative numbers are found by complementing all bits

 The range of value for an n-bit binary number in 1’s complement representation is:

From -2(n-1) + 1 to 2(n-1) - 1

Binary Multiplication

 Multiplication is achieved by adding a list of shifted multiplicands according to the digits of

the multiplier.

 Instead of listing all shifted multiplicands and then adding, we can add each shifted
multiplicand to a partial product.

 2’s-complement Multiplication: A sequence of of two’s-complement additions of shifted

multiplicands except for last step where the shifted multiplicand corresponding to MSB must
be negated.

 Before adding a shifted multiplicand to the partial product, an additional bit is added to the
left of the partial product using sign extension.

Binary Division

 Shift and substract

Error Detection Binary Codes

 Errors can occur during data transmission. They should be detected, so that re-transmission
can be requested.

 For single-error detection, one additional bit is needed:

 Even parity code: additional bit with value to make total number of 1’s even

 Odd parity code: additional bit with value to make total number of 1’s odd
Combinational logic circuits:

 Outputs depend only on its current inputs.

 A combinational circuit may contain an arbitrary number of logic gates and inverters but no
feedback loops.

 A feedback loop is a connection from the output of one gate to propagate back into the
input of that same gate

 The function of a combinational circuit represented by a logic diagram is formally described

using logic expressions and truth tables.

Sequential logic circuits:

 Outputs depend not only on the current inputs but also on the past sequences of inputs.

 Sequential logic circuits contain combinational logic in addition to memory elements formed
with feedback loops.

 The behavior of sequential circuits is formally described with state transition tables and
diagrams.

Gate propagation delay: The time between an input change and corresponding change of the
output

Circuit steady-state output: The output is evaluated when one or more inputs change values.

Output glitch: A momentary unexpected transient output change (short pulse) when an input
changes and usually caused by gate propagation delays.

Hazards: A hazard exists in a combinational circuit when it produces an output glitch when one or
more inputs change

 Static-1 Hazards: The output should be 1 but goes momentary to 0 as a result of an

input change. (possible in AND-OR circuits)

 Static-2 Hazards: The output should be 0 but goes momentary to 1 as a result of an

input change. (possible in OR-AND circuits)

 Dynamic Hazards: The output changes more than once as a result of a single input
change (impossible in 2-level circuits)
Decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded
outputs, where the input and output codes are different device is usually called an encoder.

Three-state buffers are CMOS and TTL devices whose outputs may be in one of three states: 0,1
or Hi-Z (High impedance, or floating state)

Multiplexer is a digital switches which connects data from one of n sources to the output. A
number of select inputs determine which data source is connected to the output.
Half Adder adding two single-bit binary values, X, Y produces a sum S bit and a carry C-out bit

Full Adder adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit
S and a carry out C-out bit.

n-bit Carry Ripple Adders

An n-bit adder used to add two n-bit binary numbers can built by connecting in series adders.

- Each full adder represents a bit position j (from 0 to n-1)

- Each carry out C-out from a full adder at position j is connected to the carry in C-in of the
full adder at the higher position j+1

Carry Look-Ahead Adder

The disadvantage of the ripple carry adder is that the propagation delay of adder increases as the
size of the adder, n is increased due to the carry ripple through all the full adders.

Carry look-ahead adders use a different method to create the needed carry bits for each full
adder with a lower constant delay equal to three gate delays.

Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit
with one or two inputs/outputs, designed using individual logic gates and feedback loops.

 Latches:

 The output of a latch depends on its current inputs and on its previous inputs and its
change of state can happen at anytime when its input change.

 Flip-flop:

 The output of a flip-flop also depends on current and previous input but the change in
output occurs at specific times determined by a clock input.

State Machine Design Procedure

1. Build state/output table (or state diagram) from word description using states names.

2. Minimize number of states (optional)

3. State Assignment: Choose state variables and assign bit combinations to named states.
4. Build transition/output table from state/output table (or state diagram) by substituting state
variable combinations instead of state names.

5. Choose flip-flop type (D,J-K, etc.)

6. Build excitation table for flip-flop inputs from transition table.

7. Derive excitation equations from excitation table.

8. Derive output quations from transition/output table.

9. Draw logic diagram with excitation logic, output logic, and state memory elements.

Registers: An n-bit register is a collection of n D flip-flops with a common clock used to store n
related bits.

Shift registers: Multi-bit register that moves stored data bits left/right (1 bit position per clock
cycle)

 Often used as the state register in a sequential device.

 Usually, the next state is determined by shifting right and inserting a primary input or output
into the next position

Read Only Memory (ROM)

A combnational circuit with n inputs and b outputs:

 Programmable - values determined by user

 Nonvolatile - contents retained without power

 Uniform (Random) Access - delay is uniform for all addresses

 Stores 2n words of b bits each, or

 Stores an n-input, b-output truth table.

Mask ROM

 Connections made by the semiconductor vendor

 Expensive setup cost, Several weeks for delivery. High volume only

 Bipolar or MOS technology

PROM

 Programmable ROM
  Vaporize (blow) fusible links with PROM programmer using high voltage/current pulses

 Bipolar technology

 One-time programmable

EPROM

 Erasable Programmable ROM

 Charge trapped on extra “floating gate” of MOS transistors

 Exposure to UV light removes charge. Limited number of erasures (10-100)

EEPROM (E2 ROM)

 Electrically Erasable ROM

 Not RAM (relatively slow charge/discharge)

 limited number of charge/discharge cycles (10,000)

Flash Memory

 Electronically erasable in blocks

 100,000 erase cycles

 Simpler and denser than EEPROM

Read/Write Memory (RWM / RAM)

RWM = RAM (Random Access Memory)

 Highly structured like ROMs

 Can store and retrieve data at (relatively) the same speed

 Static RAM (SRAM) retains data in latches (while powered)

 Dynamic RAM (DRAM) stores data as capacitor charge; all capacitors must be recharged
periodically (refresh).

 Volatile Memory:

 Both Static and Dynamic RAM

 Non-volatile Memory: Data retained when power lost

= ROMs, NVRAM (w/battery), Flash Memory

DRAM SRAM
DRAM requires the data to be refresed SRAM doesn’t need to refresed as the
periodically in order to retain data transitors inside would continue to hold the
data as long as the power supply is not cut off.

Slower and less desirable Faster

The much higher power used by DRAM Less power

Only need a transistor and a capacitor for every Need a lot more transistors in order to store a
bit of data certain amount of memory

Low cost More expensive

Main memory Commonly used in cache memory