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VLSI Fabrication Process

VLSI stands for "Very Large Scale Integration". This is the field which involves
packing more and more logic devices into smaller and smaller areas. We must have a
working knowledge of chip fabrication to create effective designs and in order to optimize
the circuits with respect to various manufacturing parameters.
Introduction
An Integrated Circuit (IC) is an electronic network fabricated in a single piece of a
semiconductor material. The semiconductor surface is subjected to various processing
steps in which impurities and other materials are added with specific geometrical patterns
The fabrication steps are sequenced to form three dimensional regions that act as a
transistors and interconnects that form the network.
Fabrication process sequence
1.Silicon manufacture
2.Wafer processing
3.Lithography
4.Oxide growth and removal
5.Diffusion and ion implantation
6.Annealing
7.Silicon deposition
8.Metallization
9.Testing
10.Assembly and packaging
VLSI Fabrication Process flow diagram
1. Silicon manufacture
The basic process heats silica and coke in a submerged electric arc furnace to high
temperatures. High temperatures are required to produce a reaction where the oxygen is
removed, leaving behind silicon. This is known as a reduction process. In this process,
metal carbides usually form first at the lower temperatures. As silicon is formed, it
displaces the carbon. Refining processes are used to improve purity.

Pure silicon is melted in a pot (1400º C) and a small seed containing the desired
crystal orientation is inserted into molten silicon and slowly(1mm/minute) pulled out.

Fig1:silicon manufacturing

2. Wafer processing

The silicon crystal (in some cases also containing doping) is manufactured as a cylinder
(ingot) with a diameter of 8-12 inches(1”=2.54cm). This cylinder is carefully sawed into
thin(0.50-0.75 mm thick) disks called wafers, which are later polished and marked for
crystal orientation. The wafer is a round slice of semiconductor material such as silicon.
Silicon is preferred due to its characteristics. It is more suitable for manufacturing IC. It is
the base or substrate for entire chip. First purified polycrystalline silicon is created from
the sand. Then it is heated to produce molten liquid. A small piece of solid silicon is dipped
on the molten liquid. Then the solid silicon (seed) is slowly pulled from the melt. The liquid
cools to form single crystal ingot. A thin round wafer of silicon is cut using wafer slicer.
Wafer slicer is a precise cutting machine and each slice having thickness about .01 to
.025inches. When wafer is sliced, the surface will be damaged. It can be smoothening by
polishing. After polishing the wafer, it must thoroughly clean and dried. The wafers are
cleaned using high purity low particle chemicals .The silicon wafers are exposed to ultra
pure oxygen.
The wafer serves as the substrate for microelectronic devices built in and over the wafer
and undergoes many microfabrication process steps such as doping or ion
implantation, etching, deposition of various materials, and photolithographic patterning.
Finally, the individual microcircuits are separated (dicing) and packaged.
Formation
Wafers are formed of highly pure (99.99999% purity), nearly defect-free
single crystalline material. One process for forming crystalline wafers is known
as Czochralski growth Jan Czochralski. In this process, a cylindrical ingot of high purity
mono crystalline semiconductor, such as silicon or germanium, called a boule, is formed
by pulling a seed crystal from a 'melt'. Donor impurity atoms, such
as boron or phosphorus in the case of silicon, can be added to the molten intrinsic material
in precise amounts in order to dope the crystal, thus changing it into n-type or p-
type extrinsic semiconductor.
The boule is then sliced with a wafer saw (wire saw) and polished to form wafers. The size
of wafers for photovoltaics is 100–200 mm square and the thickness is 200–300 μm. In the
future, 160 μm will be the standard. Electronics use wafer sizes from 100–450 mm
diameter.

Fig2:wafer processing
3.Lithography
Lithography: process used to transfer patterns to each layer of the IC Lithography
sequence steps: Designer: Drawing the “layer” patterns on a layout editor Silicon
Foundry: Masks generation from the layer patterns in the design data base Printing:
transfer the mask pattern to the wafer surface Process the wafer to physically pattern each
layer of the IC.
(a).Photo resist application:
the surface to be patterned is spin-coated with a light-sensitive organic polymer called
photoresist
(b)Printing (exposure):
the mask pattern is developed on the photoresist, with UV light exposure depending on
the type of
photoresist(negative or positive), the exposed or unexposed parts become resistant to
certain types of solvents
(c)Development:
the soluble photo resist is chemically removed The developed photo resist acts as a mask
for patterning of underlying layers and then is removed.

Fig3:lithography
4.Oxide growth and removal
Oxide can be grown from silicon through heating in an oxidizing atmosphere Gate oxide,
device isolation Oxidation consumes silicon SiO2is deposited on materials other than
silicon through reaction between gaseous silicon compounds and oxidizers Insulation
between different layers of metallization Once the desired shape is patterned with
photoresist, the etching process allows unprotected materials to be removed Wet etching:
uses chemicals Dry or plasma etching: uses ionized gases

Fig4:oxide growth and removal

5 .Diffusion and ion implantation


Doping materials are added to Change the electrical characteristics of silicon locally
through:
Diffusion:
dopants deposited on silicon move through the lattice by thermal diffusion (high
temperature process) Wells Ion implantation: highly energized donor or acceptor atoms
impinge on the surface and travel below it The patterned SiO2serves as an implantation
mask Source and Drain regions.
Fig5:diffusion and ion implatation

6. Annealing

Thermal annealing is a high temperature process which allows doping impurities to diffuse
further into the bulk repairs lattice damage caused by the collisions with doping ions.

7.Silicon deposition
Films of silicon can be added on the surface of a wafer Epitaxy: growth of a single-crystal
semiconductor film on a crystalline substate Polysilicon: polycrystalline film with a
granular structure obtained through deposition of silicon on an amorphous material
MOSFET gates

Fig6:silicon deposition
1. Depositions that happen because of a chemical reaction:
o Chemical Vapor Deposition (CVD)
o Electrodeposition
o Epitaxy
o Thermal oxidation

These processes exploit the creation of solid materials directly from chemical
reactions in gas and/or liquid compositions or with the substrate material. The
solid material is usually not the only product formed by the reaction. Byproducts
can include gases, liquids and even other solids.

2. Depositions that happen because of a physical reaction:


o Physical Vapor Deposition (PVD)
o Casting

8.Metallization
Metallization: deposition of metal layers by evaporation interconnections. Metallization is
the final step in the wafer processing sequence. Metallization is the process by which the
components of IC’s are interconnected by aluminum conductor. This process produces a
thin-film metal layer that will serve as the required conductor pattern for the
interconnection of the various components on the chip. Another use of metallization is to
produce metalized areas called bonding pads around the periphery of the chip to produce
metalized areas for the bonding of wire leads from the package to the chip. The bonding
wires are typically 25 micro meters diameter gold wires, and the bonding pads are usually
made to be around 100×100 micro meters square to accommodate fully the flattened ends
of the bonding wires and to allow for some registration errors in the placement of the wires
on the pads.

9.Testing
Test that chip operates Design errors Manufacturing errors A single dust particle or wafer
defect kills a die Yields from 90% to < 10% Depends on die size, maturity of process Test
each part before shipping to customer.

10.Assembly and packaging


Takeout final layout Fabrication 6, 8, 12” wafers Optimized for throughput, not latency (10
weeks) Cut into individual dice Packaging Bond gold wires from die I/O pads to package
world. So if the function is constructed with many smaller ICs connected together, then
there are many connections, and the
reliability is lower. The vlsi has fewer connections, and higher reliability