5-1 D0 D Q0

Clock • C
REG
Clear R

•
• • Clear

D1 D Q1 D0 Q0
D1 Q1
• C
D2 Q2
R

•
• D3 Q3

D2 D Q2 (b) Symbol
• C

•
•
D3 D Q3 Load • C inputs (clock inputs
Clock of flip-flops)
C

R (c) Load control input

•
(a) Logic diagram

Clock

Load

C inputs

(d) Timing diagram

Fig. 5-1 4-Bit Register

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-2

Load •

• •
D • Q0
D0 C
•

•
D • Q1
D1
• C
•

•
D • Q2
D2
• C
•

D • Q3
D3
• C

Clock

Fig. 5-2 4-Bit Register with Parallel Load

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-3

Serial Serial
input SI D D D D input S0
C C C C

Clock • • •
(a) Logic diagram

SRG 4
Clock

Sl SO

(b) Symbol

Fig. 5-3 4-Bit Shift Register

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-4

Shift • •
Clock Register A Register B
SRG 4 SRG 4
C C

0 Sl SO Sl SO

(a) Block diagram

Clock

Shift
C Input

T1 T2 T3 T4

(b) Timing diagram

Fig. 5-4 Serial Transfer

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-5

TABLE 5-1
Example of Serial Transfer

Timing
pulse Shift Register A Shift Register B

Initial value 1 0 1 1 0 0 1 0
After T1 0 1 0 1 1 0 0 1
After T2 0 0 1 0 1 1 0 0
After T3 0 0 0 1 0 1 1 0
After T4 0 0 0 0 1 0 1 1

Table 5-1 Example of Serial Transfer

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-6

Register A
SRG 4
C
Reset Clear FA
Sl SO X S
Y
Z C
Shift • •
Clock Full Adder
(Figure 3-27)
Register B
SRG 4
• C
Carry
Reset Clear
Serial Sl SO D
input
C

Reset

Fig. 5-5 Serial Addition

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-7
Shift •
Load • •
Serial
input
• •
D0 • Q0
D •
•
C
•
•

•
SHR 4
D1 • D • Q1
• Shift
• C
• Load
•
Sl
• D0 Q0
D1 Q1
•
D2 Q2
D2 • Q2
D • D3 Q3
•
• C
• (b) Symbol
•

D3 • D • Q3

• C

Clock

Fig. 5-6 Shift Register with Parallel Load

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-8

TABLE 5-2
Function Table for the Register of Figure 5-6

Shift Load Operation

0 0 No change
0 1 Load parallel data
1 ⫻ Shift down from Q0 to Q3

Table 5-2 Function Table for the Register of Figure 5-6

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-9

D • Qi – 1
C

SHR 4
Clock
MUX Mode S1 S1

S1 S1 Mode S0 S0
Left serial input LSI
S0 S0
D0 Q0
D1 Q1
0 D • Qi D2 Q2
1 • C D3 Q3
2 Right serial input RSI

Di 3
(b) Symbol

D • Qi + 1

• C
Clock

(a) Logic diagram of one typical stage

Fig. 5-7 Bidirectional Shift Register with Parallel Load

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-10

TABLE 5-3
Function Table for the Register of Figure 5-7

Mode control
Register
S1 S0 Operation

0 0 No change
0 1 Shift down
1 0 Shift up
1 1 Parallel load

Table 5-3 Function Table for the Register of Figure 5-7

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-11
J • Q0
Clock pulses
• C

• K
R
•
• J • Q1

• C

• K
R

• •
• J • Q2

• C

• K
R

• •
• J Q3

• C

• K
R

Clear • •
Logic 1

Fig. 5-8 4-Bit Ripple Counter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-12

TABLE 5-4
Counting Sequence of Binary Counter

Upward Counting Sequence Downward Counting Sequence

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0
0 0 1 0 1 1 0 1
0 0 1 1 1 1 0 0
0 1 0 0 1 0 1 1
0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 0 0
1 0 0 0 0 1 1 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 0 1
1 0 1 1 0 1 0 0
1 1 0 0 0 0 1 1
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 1
1 1 1 1 0 0 0 0

Table 5-4 Counting Sequence of Binary Counter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-13

TABLE 5-5
State Table and Flip-Flop Inputs for Binary Counter

Present Next
state state Flip-flop inputs

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 JQ3 KQ3 JQ2 KQ2 JQ1 KQ1 JQ0 KQ0

0 0 0 0 0 0 0 1 0 ⫻ 0 ⫻ 0 ⫻ 1 ⫻
0 0 0 1 0 0 1 0 0 ⫻ 0 ⫻ 1 ⫻ ⫻ 1
0 0 1 0 0 0 1 1 0 ⫻ 0 ⫻ ⫻ 0 1 ⫻
0 0 1 1 0 1 0 0 0 ⫻ 1 ⫻ ⫻ 1 ⫻ 1
0 1 0 0 0 1 0 1 0 ⫻ ⫻ 0 0 ⫻ 1 ⫻
0 1 0 1 0 1 1 0 0 ⫻ ⫻ 0 1 ⫻ ⫻ 1
0 1 1 0 0 1 1 1 0 ⫻ ⫻ 0 ⫻ 0 1 ⫻
0 1 1 1 1 0 0 0 1 ⫻ ⫻ 1 ⫻ 1 ⫻ 1
1 0 0 0 1 0 0 1 ⫻ 0 0 ⫻ 0 ⫻ 1 ⫻
1 0 0 1 1 0 1 0 ⫻ 0 0 ⫻ 1 ⫻ ⫻ 1
1 0 1 0 1 0 1 1 ⫻ 0 0 ⫻ ⫻ 0 1 ⫻
1 0 1 1 1 1 0 0 ⫻ 0 1 ⫻ ⫻ 1 ⫻ 1
1 1 0 0 1 1 0 1 ⫻ 0 ⫻ 0 0 ⫻ 1 ⫻
1 1 0 1 1 1 1 0 ⫻ 0 ⫻ 0 1 ⫻ ⫻ 1
1 1 1 0 1 1 1 1 ⫻ 0 ⫻ 0 ⫻ 0 1 ⫻
1 1 1 1 0 0 0 0 ⫻ 1 ⫻ 1 ⫻ 1 ⫻ 1

Table 5-5 State Table and Flip-Flop Inputs for Binary Counter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-14 Q1Q0 Q1
Q3 Q2 00 01 11 10

00 X X X X

01 1 X X X X
Q2
11 X X X X 1
Q3
10 X X X X

Q0

JQ3 = Q0 Q1 Q2 KQ3 = Q0 Q1 Q2

1 X X X X

X
X X X X 1

X X X X 1

1 X X X X

JQ2 = Q0 Q1 KQ2 = Q0 Q1

1 X X X X 1

1 X X X X 1

1 X X X 1

1 X X X X 1

JQ1 = Q0 KQ1 = Q0

Fig. 5-9 Maps for Input Equations of a Binary Counter

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-15 J • Q0

Count enable EN • • K

J • Q1
CTR 4
• C

• • K • EN Q0
Q1
Q2
J • Q2 Q3

• C CO

• • K
(b) Symbol

J • Q3

• C

• • K

Carry
output CO

Clock

(a) Logic diagram

Fig. 5-10 4-Bit Synchronous Binary Counter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-16 Q0
•
EN •
Count enable EN
D • Q0
•
C
Q1

• •
C1
•
D • Q1
•
• C

Q2
• •
• C2
D • Q2 •
•
• C

Q3

•
•
• C3
•
D • Q3 •
•
• C

Carry
output CO
CO
Clock

(a) Serial gating (b) Parallel gating

Fig. 5-11 4-Bit Binary Counter with D Flip-Flops

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-17 Count
•
Load •
D0
• J Q0
• •
•
C
•
• K
•

D1 • J Q1
• • CTR 4
•
• C
Load
•
• K Count
• D0 Q0
D1 Q1
D2 Q2
D3 Q3
D2
• J Q2
• • CO
•
• C
(b) Symbol
•
• K
•

D3
• J Q3
• •
•
• C
•
• K

Carry
Output CO

Clock
(a) Logic diagram

© 2001 Prentice Hall, Inc. Fig. 5-12 4-Bit Binary Counter with Parallel Load
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-18

TABLE 5-6
State Table and Flip-Flop Inputs for BCD Counter

Present State Next State Output Flip-Flop Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Y TQ8 TQ4 TQ2 TQ1

0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 0 1
0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 0 1 1 0 0 1

Table 5-6 State Table and Flip-Flop Inputs for BCD Counter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-19

CTR 4
Clock
Load
1 Count
D0 Q0 • Q0
D1 Q1 Q1
D2 Q2 Q2
• D3 Q3 • Q3
(Logic 0)
CO

Fig. 5-13 BCD Counter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-20

TABLE 5-7
State Table and Flip-Flop Inputs for BCD Counter

Present State Next State Output Flip-Flop Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Y TQ8 TQ4 TQ2 TQ1

0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 0 1
0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 0 1 1 0 0 1

Table 5-7 State Table and Flip-Flop Inputs for BCD Counter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-21

A B C

• •
•
C C C
J K J K J K
Clock • •
•

•
Logic-1
(a) Logic diagram

000 111

001 110

010 101

100 011

(b) State diagram

Fig. 5-14 Counter with Arbitrary Count

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-22

TABLE 5-8
State Table and Flip-Flop Inputs for Counter

Present
State Next State Flip-Flop Inputs

A B C A B C JA KA JB KB JC KC

0 0 0 0 0 1 0 ⫻ 0 ⫻ 1 ⫻
0 0 1 0 1 0 0 ⫻ 1 ⫻ ⫻ 1
0 1 0 1 0 0 1 ⫻ ⫻ 1 0 ⫻
1 0 0 1 0 1 ⫻ 0 0 ⫻ 1 ⫻
1 0 1 1 1 0 ⫻ 0 1 ⫻ ⫻ 1
1 1 0 0 0 0 ⫻ 1 ⫻ 1 0 ⫻

Table 5-8 State Table and Flip-Flop Inputs for Counter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-23

-- 4-bit Shift Register with Reset

-- (See Figure 5-3)
library ieee;
use ieee.std_logic_1164.all;

entity srg_4_r is
port(CLK, RESET, SI : in std_logic;
Q : out std_logic_vector(3 downto 0);
SO : out std_logic);
end srg_4_r;

architecture behavioral of srg_4_r is

signal shift : std_logic_vector(3 downto 0);
begin
process (RESET, CLK)
begin
if (RESET = '1') then
shift <= "0000";
elsif (CLK’event and (CLK = '1')) then
shift <= shift(2 downto 0) & SI;
end if;
end process;
Q <= shift;
SO <= shift(3);
end behavioral;

Fig. 5-15 Behavioral VHDL Description of 4-bit Left Shift Register with Direct Reset

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-24

-- 4-bit Binary Counter with Reset

-- (See Figure 5-10)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count_4_r is
port(CLK, RESET, EN : in std_logic;
Q : out std_logic_vector(3 downto 0);
CO : out std_logic);
end count_4_r;

architecture behavioral of count_4_r is

signal count : std_logic_vector(3 downto 0);
begin
process (RESET, CLK)
begin
if (RESET = '1') then
count <= "0000";
elsif (CLK’event and (CLK = '1') and (EN = '1')) then
count <= count + "0001";
end if;
end process;
Q <= count;
CO <= '1' when count = "1111" and EN = '1' else '0';
end behavioral;

Fig. 5-16 Behavioral VHDL Description of 4-bit Binary Counter with Direct Reset

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-25

// 4-bit Shift Register with Reset

// (See Figure 5-3)

module srg_4_r_v (CLK, RESET, SI, Q,SO);

input CLK, RESET, SI;
output [3:0] Q;
output SO;

reg [3:0] Q;

assign SO = Q[3];

always@(posedge CLK or posedge RESET)

begin
if (RESET)
Q <= 4'b0000;
else
Q <= {Q[2:0], SI};
end
endmodule

Fig. 5-17 Behavioral Verilog Description of 4-bit Left Shift Register with Direct Reset

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-26

// 4-bit Binary Counter with Reset

// (See Figure 5-10)

module count_4_r_v (CLK, RESET, EN, Q, CO);

input CLK, RESET, EN;
output [3:0] Q;
output CO;

reg [3:0] Q;

assign CO = (count == 4'b1111 && EN == 1’b1) ? 1 : 0;

always@(posedge CLK or posedge RESET)
begin
if (RESET)
Q <= 4'b0000;
else if (EN)
Q <= Q + 4'b0001;
end
endmodule

Fig. 5-18 Behavioral Verilog Description of 4-bit Binary Counter with Direct Reset

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.