VLSI Testing and Verification

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 Introduction
• VLSI realization process
• Verification and test
• Ideal and real tests
• Costs of testing
• Roles of testing

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 VLSI Realization Process
Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification

Test development
Fabrication
Manufacturing test

Chips to customer
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 Definitions
• Design synthesis: Given an I/O function, develop
a procedure to manufacture a device using
known materials and processes.
• Verification: Predictive analysis to ensure that the
synthesized design, when manufactured, will
perform the given I/O function.
• Test: A manufacturing step that ensures that the
physical device, manufactured from the
synthesized design, has no manufacturing defect.

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 Verification vs. Test
Verification Test
• Verifies correctness of • Verifies correctness of
design. manufactured hardware.
• Performed by simulation, • Two-part process:
hardware emulation, or – 1. Test generation: software
formal methods. process executed once
during design
– 2. Test application: electrical
tests applied to hardware
• Performed once prior to • Test application performed on
manufacturing. every manufactured device.
• Responsible for quality of • Responsible for quality of
design. devices.

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 Problems of Ideal Tests
• Ideal tests detect all defects produced in
the manufacturing process.
• Ideal tests pass all functionally good
devices.
• Very large numbers and varieties of
possible defects need to be tested.
• Difficult to generate tests for some real
defects. Defect-oriented testing is an
open problem.
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 Real Tests
• Based on analyzable fault models, which may
not map on real defects.
• Incomplete coverage of modeled faults due to
high complexity.
• Some good chips are rejected. The fraction
(or percentage) of such chips is called the
yield loss.
• Some bad chips pass tests. The fraction (or
percentage) of bad chips among all passing
chips is called the defect level.
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 Testing as Filter Process

Good chips Prob(pass test) = high Mostly

good
Prob(good) = y
chips

Fabricated Tested
chips chips

Defective chips Mostly

bad
Prob(bad) = 1- y Prob(fail test) = high chips

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 Costs of Testing
• Design for testability (DFT)
– Chip area overhead and yield reduction
– Performance overhead
• Software processes of test
– Test generation and fault simulation
– Test programming and debugging
• Manufacturing test
– Automatic test equipment (ATE) capital cost
– Test center operational cost

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 Present and Future*

1997 -2001 2003 - 2006

Feature size (micron) 0.25 - 0.15 0.13 - 0.10

Transistors/sq. cm 4 - 10M 18 - 39M
Pin count 100 – 900 160 - 1475
Clock rate (MHz) 200 – 730 530 - 1100
Power (Watts) 1.2 – 61 2 - 96

* SIA Roadmap, IEEE Spectrum, July 1999

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 Design for Testability (DFT)
DFT refers to hardware design styles or added hardware
that reduces test generation complexity.
Motivation: Test generation complexity increases
exponentially with the size of the circuit.
Example: Test hardware applies tests to blocks A
and B and to internal bus; avoids test generation
for combined A and B blocks.
Int.
Primary Primary
Logic bus Logic
inputs outputs
block A block B
(PI) (PO)
Test Test
input output
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 Cost of Manufacturing Testing in
2000AD
• 0.5-1.0GHz; analog instruments; 1,024 digital
pins: ATE purchase price
= $1.2M + 1,024 x $3,000 = $4.272M
• Annual running cost (five-year linear depreciation)
= Depreciation (1/5) + Maintenance (2%) + Operation ($0.5M)
= $0.854M + $0.085M + $0.5M
= $1.439M/year
• Test cost (24 hour ATE operation)
= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second

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 Roles of Testing
• Detection: Determination whether or not the
device under test (DUT) has some fault.
• Diagnosis: Identification of a specific fault
that is present on DUT.
• Device characterization: Determination and
correction of errors in design and/or test
procedure.
• Failure mode analysis (FMA): Determination
of manufacturing process errors that may
have caused defects on the DUT.

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 Textbooks
• Digital, memory and mixed-signal:
– M. L. Bushnell and V. D. Agrawal, Essentials of
Electronic Testing for Digital, Memory and Mixed-
Signal VLSI Circuits, Springer, 2000.
– http://www.eng.auburn.edu/~vagrawal/BOOK/books.html

• Digital System Testing and Testable Design

-M. Abramovici, M. Breuer, A. Friedman
-IEEE Press 1994 (now available in Jayco
Publication)

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 Problem to Solve

• Using the testing cost obtained in Slide 15,

determine what is the component of test in the
cost of a mixed-signal VLSI chip for the following
data:
– Analog test time = 1.5 s
– Digital test clock = 200MHz
– Number of digital test vectors = 109
– Chip yield = 70%

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 Solution
Assuming that one vector is applied per clock cycle during the digital test, the
rate of test application is 200 million vectors per second. Therefore,
Digital test time = (1000 × 106)/(200× 106) = 5 seconds

Adding the analog test time, we get,

Total test time = 1.5 + 5.0 = 6.5 seconds

The testing cost for a 500 MHz, 1,024 pin tester was obtained as 4.56 cents in
Slide 15. Thus,
Cost of testing a chip = 6.5 × 4.56 = 29.64 cents

The cost of testing bad chips should also be recovered from the price of good
chips. Since the yield of good chips is 70%, we obtain
Test cost in the price of a chip = 29.64/0.7 ≈ 42 cents

42 cents should be included as the cost of testing while figuring out the
price of chips.

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