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MCP PROGRAMS

MANUAL LAB SHEET

PROGRAMS::
EXPERIMENT 1(B):
IMMEDIATE ADDRESSING MODE
org 0000H

LJMP MAIN

MAIN:MOV A,#50H

MOV R1,#30H

ADD A,R1

END

INDIRECT ADDRESSING MODE


org 0000H

LJMP MAIN

MAIN:MOV 40H,#50H

MOV 41H,#30H

MOV R0,#40H

MOV R1,#41H

MOV A,@R0
MOV B,@R1

ADD A,B

END

DIRECT ADDRESSING MODE


org 0000H

LJMP MAIN

MAIN:MOV 40H,#50H

MOV A,#30H

ADD A,40H

END

REGISTER ADDESSING MODE


ORG 0000H

LJMP MAIN

MAIN:

MOV A,#03H

CPL A

ADD A,#01H

END

EXPERIMENT 2(A)
ADDITION 8-BIT

org 0000H

LJMP MAIN

MAIN:MOV A,#50H

ADD A,#30H

END
SUBTRACTION

org 0000H

LJMP MAIN

MAIN:MOV A,#50H

SUBB A,#30H

END

MULTIPLICATION

org 0000H

LJMP MAIN

MAIN:MOV A,#50H

MOV B,#30H

MUL AB

END

DIVISION
org 0000H

LJMP MAIN

MAIN:MOV A,#50H

MOV B,#30H

MUL AB

END

EXPERIMENT 3
SQUARE OF DECIMAL

ORG 0000H

LJMP MAIN
MAIN:

MOV A,#03H

MOV B,A

MUL AB

END

CUBE OF DECIMAL

EXPERIMENT 4 block transfer without over;lap


ORG 0000H

LJMP MAIN

MAIN:

MOV 30H,#00H

MOV 31H,#01H

MOV 32H,#02H

MOV 33H,#03H

MOV 34H,#04H

MOV 35H,#05H

MOV 36H,#06H

MOV 37H,#07H

MOV 38H,#08H

MOV 39H,#09H

MOV R0,#30H

MOV R1,#40H

MOV R2,#0AH

BACK:

MOV A,@R0

MOV @R1,A
DEC R1

DEC R0

DJNZ R2, BACK

END

EXPERIMENT 5 block transfer with over;lap

ORG 0000H

LJMP MAIN

MAIN:

MOV 30H,#10H

MOV 31H,#11H

MOV 32H,#12H

MOV 33H,#13H

MOV 34H,#14H

MOV 35H,#15H

MOV 36H,#16H

MOV 37H,#17H

MOV 38H,#18H

MOV 39H,#19H

MOV R0,#30H

MOV R1,#35H

MOV R2,#0AH

MOV A,R2

ADD A,R1

MOV R1,A
MOV A,R2

ADD A,R0

MOV R0,A

DEC R0

DEC R1

BACK:

MOV A,@R0

MOV @R1,A

DEC R0

DEC R1

DJNZ R2, BACK

END

EXPERIMENT 6 exchacnge
ORG 0000H

LJMP MAIN

MAIN:

MOV 30H,#10H

MOV 31H,#11H

MOV 32H,#12H

MOV 33H,#13H

MOV 34H,#14H

MOV 35H,#15H

MOV 36H,#16H

MOV 37H,#17H

MOV 38H,#18H

MOV 39H,#19H
MOV 40H,#20H

MOV 41H,#21H

MOV 42H,#22H

MOV 43H,#23H

MOV 44H,#24H

MOV 45H,#25H

MOV 46H,#26H

MOV 47H,#27H

MOV 48H,#28H

MOV 49H,#29H

MOV R0,#30H

MOV R1,#40H

MOV R2,#0AH

BACK:

MOV A,@R0

MOV B,@R1

XCH A,B

MOV @R0,A

MOV @R1,B

INC R0

INC R1

DJNZ R2, BACK

END

EXPERIMENT 7 exter4nal to internal memeory


ORG 0000H

LJMP MAIN
MAIN:

MOV DPTR,#1000H

MOV R0,#30H

MOV R2,#0AH

BACK:

MOVC A,@A+DPTR

MOV @R0,A

INC R0

DJNZ R2,BACK

ORG 1000H

DB 01H,02H,03H,04H,05H,06H,07H,08H,09H,0AH

END

EXPERIMENT SMALLEST
ORG 0000H

LJMP MAIN

MAIN:MOV 30H,#06H

MOV 31H,#03H

MOV 32H,#09H

MOV 33H,#05H

MOV 34H,#01H

MOV 35H,#0AH

MOV 36H,#02H

MOV 37H,#04H

MOV 38H,#07H

MOV 39H,#08H

MOV R0,#30H
MOV R2,#0AH

MOV A,@R0

MOV B,R0

MOV R4,B

DEC R2

LOOP1:INC R0

MOV B,@R0

CJNE A,B,LOOP2

LOOP2:JC LOOP3

MOV A,B

MOV R3,A

MOV B,R0

MOV R4,B

DJNZ R2,LOOP1

LJMP EXIT

LOOP3:MOV R3,A

DJNZ R2,LOOP1

EXIT:

END

EXPERIMENT 9(A) 2,s complement


ORG 0000H

LJMP MAIN

MAIN:

MOV A,#03H

CPL A

ADD A,#01H
END

EXPERIMENT 10(A) DECENDING


ORG 0000H

LJMP MAIN

MAIN:MOV 30H,#09H

MOV 31H,#06H

MOV 32H,#2AH

MOV 33H,#1CH

MOV 34H,#0AH

MOV 35H,#1FH

MOV 36H,#04H

MOV 37H,#01H

MOV 38H,#2DH

MOV 39H,#0CH

AGAIN:MOV R0,#30H

MOV R2,#09

MOV R3,#09

CLR C

UP:MOV A,@R0

MOV B,A

INC R0

MOV A,@R0

CJNE A,B,LOOP

LOOP:JNC SKIP

MOV A,@R0
DEC R0

MOV @R0,A

MOV A,B

INC R0

MOV @R0,A

SKIP:DJNZ R2,UP

DJNZ R3,AGAIN

END

SEARCH FOR AN ELEMENT

ORG OOOOH

LJMP MAIN

MAIN: MOV 30H,#2AH

MOV 31H,#3CH

MOV 32H,#1AH

MOV 33H,#09H

MOV 34H,#10H

MOV 35H,#6EH

MOV 36H,#8AH

MOV 37H,#1EH

MOV 38H,#7AH

MOV 39H,#3BH

MOV R0,#30H

MOV R1,#0AH
MOV R3,#00H

MOV A,#10H

LOOP1: MOV B, @R0

CJNE A,B ,LOOP2

INC R3

LJMP EXIT

LOOP2: INC R0

DJNZ R2, LOOP2

EXIT:

EXPERIMENT 10(B) ASCENDING


ORG 0000H

LJMP MAIN

MAIN:MOV 30H,#09H

MOV 31H,#06H

MOV 32H,#2AH

MOV 33H,#1CH

MOV 34H,#0AH

MOV 35H,#1FH

MOV 36H,#04H

MOV 37H,#01H

MOV 38H,#2DH
MOV 39H,#0CH

AGAIN:MOV R0,#30H

MOV R2,#09

MOV R3,#09

CLR C

UP:MOV A,@R0

MOV B,A

INC R0

MOV A,@R0

CJNE A,B,LOOP

LOOP:JC SKIP

MOV A,@R0

DEC R0

MOV @R0,A

MOV A,B

INC R0

MOV @R0,A

SKIP:DJNZ R2,UP

DJNZ R3,AGAIN

END

EXPERIMENT 11(A)ascii to packed bcd

ORG 0000H

LJMP MAIN
MAIN:MOV A,#'4'

MOV B,#'9'

XRL A,#30H

SWAP A

XRL B,#30H

ORL A,B

END

EXPERIMENT 11(B) ascii to unpacked bcd

ORG 0000H

LJMP MAIN

MAIN:MOV A,#'4'

XRL A,#30H

MOV B,#'9'

XRL B,#30H

END

EXPERIMENT 12(A) hex decimal counter


ORG 0000H

LJMP MAIN

MAIN:MOV R0,#30H

MOV @R0,#00H

CJNE @R0,#00H,DOWN

UP:MOV A,#00H

L1:INC A

CJNE A,#0FH,L1
LJMP MAIN

DOWN:MOV A,#0FH

L2:DEC A

CJNE A,#00H,L2

LJMP MAIN

END

EXPERIMENT 12(B) bcd counter


ORG 0000H

LJMP MAIN

MAIN:MOV R0,#30H

MOV @R0,#01H

CJNE @R0,#00H,DOWN

UP:MOV A,#00H

L1:MOV R5,A

ADD A,#01H

DA A

LJMP L1

DOWN:MOV A,#99H

L2:MOV R5,A

ADD A,#99H

DA A

LJMP L2

LJMP MAIN

END
EXPERIMENT 13
time delay
A.USING INSTRUCTIONS
ORG 0000H

LJMP MAIN

MAIN:MOV A,#00H

BACK:LCALL DELAY

INC A

CJNE A,#06H,BACK

DELAY:MOV R0,#0FH

HERE:DJNZ R0,HERE

RET

END

B.USING TIMERS

ORG 0000H

BACK:ACALL DELAY

LJMP BACK

DELAY:MOV TMOD,#01H

MOV R0,#0FH

LOOP:MOV TH0,#0FFH

MOV TL0,#0FEH
SETB TR0

HERE:JNB TF0,HERE

CLR TR0

CLR TF0

DJNZ R0,LOOP

RET

END

EXPERIMENT 15
hcf
ORG 0000H

LJMP MAIN

MAIN:MOV 40H,#0EH

MOV 41H,#04H

MOV 42H,#07H

CLR C

MOV A,40H

MOV B,41H

LCALL HCF

LOOP:MOV B,R5

MOV A,42H

LCALL HCF
LJMP EXIT

HCF:CJNE A,B,BIG

BIG:JNC DIVI

XCH A,B

DIVI:MOV R5,B

DIV AB

MOV A,B

JNZ AGAIN

AGAIN:MOV A,R5

LJMP DIVI

EXIT:

END

EXPERIMENT 16
lcm
ORG 0000H

LJMP MAIN

MAIN:MOV 40H,#0EH

MOV 41H,#04H

MOV A,40H

MOV B,41H

MUL AB

MOV R1,A

MOV A,40H

MOV B,41H
LCALL HCF

MOV B,R5

MOV A,R1

DIV AB

MOV R4,A

LJMP EXIT

HCF:CJNE A,B,BIG

BIG:JNC DIVI

XCH A,B

DIVI:MOV R5,B

DIV AB

MOV A,B

JNZ AGAIN

AGAIN:MOV A,R5

LJMP DIVI

EXIT:

END

PROGRAM 16
Implement parallel adder

AIM: To display message on given address, in memory window.

SOFTWARE REQURIED:Xilinx 10.1

Program:
module adder_4bit ( a ,b ,sum ,carry );

output [3:0] sum ;


output carry ;

input [3:0] a ;
input [3:0] b ;

wire [2:0]s;

full_adder u0 (a[0],b[0],1'b0,sum[0],s[0]);
full_adder u1 (a[1],b[1],s[0],sum[1],s[1]);
full_adder u2 (a[2],b[2],s[1],sum[2],s[2]);
full_adder u3 (a[3],b[3],s[2],sum[3],carry);

endmodule
RESULT: Implemented design of parallel adder