Introduction To

Semiconductor
Manufacturing Technology

T. S. Chao
Dept. of Electrophysics

1/41 1/80
 CMOS Process Flow

• Overview of Areas in a Wafer Fab

– Diffusion (oxidation, deposition and doping)
– Photolithography
– Etch
– Ion Implant
– Thin Films
– Polish
• CMOS Manufacturing Steps
• Parametric Testing
• 6~8 weeks involve 350-step

2/80
 Model of Typical Wafer Flow
in a Sub-Micron CMOS IC Fab

Wafer Fabrication (front-end)

Wafer Start

Unpatterned Thin Films Polish

Wafer

Completed Wafer Diffusion Photo Etch

Test/Sort Implant

6 major production areas

3/80
 Clean: Types of Contamination
and The Problems They Cause

• Particles
• Metallic Impurities
• Organic Contamination
• Native Oxides
• Electrostatic Discharge
• Contamination often leads to a defective chip. Killer defects are those causes
of failure where the chip on the wafer fails during electrical test.
• It is estimated that 80% of all chip failure are due to killer defects from
contamination.

4/80
 Wafer Wet-Cleaning Chemicals
Chemical Mixture Description
Contaminant Name (all Cleans are followed by a DI Chemicals
Water Rinse)
Piranha  Sulfuric acid/hydrogen
peroxide/DI water H2SO4/H2O2/H2O
(SPM)
Particles
SC-1 • Ammonium hydroxide/hydrogen
NH4OH/H2O2/H2O
(APM) peroxide/DI water
SC-1 • Ammonium hydroxide/hydrogen
Organics NH4OH/H2O2/H2O
(APM) peroxide/DI water
SC-2 • Hydrochloric acid/hydrogen
HCl/H2O2/H2O
(HPM) peroxide/DI water
Metallics Piranha  Sulfuric acid/hydrogen
peroxide/DI water H2SO4/H2O2
(not Cu) (SPM)
DHF • Hydrofluoric acid/water solution
HF/H2O
(will not remove copper)
DHF • Hydrofluoric acid/water solution
HF/H2O
Native Oxides (will not remove copper)
BHF • Buffered hydrofluoric acid NH4F/HF/H2O

5/80
 Typical Wafer Wet-Cleaning Sequence

Cleaning Step What it Cleans

H2SO4/H2O2 (piranha) Organics & metals
UPW rinse (ultrapure water) Rinse
HF/H2O (dilute HF) Native oxides
UPW rinse Rinse
NH4OH/H2O2/H2O (SC-1) Particles
UPW rinse Rinse
HF/H2O Native oxides
UPW rinse Rinse
HCl/H2O2/H2O (SC-2) Metals
UPW rinse Rinse
HF/H2O Native oxides
UPW rinse Rinse
Drying Dry

6/80
 Diffusion: Simplified Schematic of High-
Temperature Furnace
Thermocouple
Temperature measurements Gas flow
Process gas
controller controller

Quartz tube

Heater 1
Temperature-
setting voltages
Heater 2
Three-zone
Heating
Heater 3 Elements

Exhaust
Pressure
controller
Can do : oxidation, diffusion, deposition, anneals, and alloy
7/80
 Dry Oxidation Time (Minutes)
Si (solid) + O2 (gas)  SiO2 (solid)

10.0
(100) Silicon
Oxide thickness (µm)

1.0

0.1

0.01
10 102 103 104
Time (minutes)

8/80
 Wet Oxygen Oxidation

Exhaust
Gas panel
Furnace
Scrubber

Burn box

• H2+O2  H2O
• Si (solid) + 2H2O  SiO2 (solid) + 2H2
• The fast growth rate in wet atmosphere is due to
the faster diffusion and higher solubility of water
vapor than oxygen in silicon dioxide
HCl N2 O2 H2 • Hydrogen molecules produced in the reaction are
trapped in oxide, less dense, using heating
(annealing) to improve.

9/80
 Negative Lithography

• Areas exposed to light become

crosslinked and resist the
Ultraviolet light
developer chemical.
Chrome island on
glass mask Island
Exposed area of
photoresist
Window
Photoresist
Shadow on
photoresist

Photoresist
Oxide Oxide
Silicon substrate Silicon substrate

Resulting pattern after

the resist is developed.

10/80
 Positive Lithography

Ultraviolet light
Areas exposed to
light are dissolved.
Chrome island Shadow on
on glass mask photoresist Island
Window

photoresist
Photoresist

Exposed area
of photoresist
photoresist
Photoresist
oxide
Oxide oxide
Oxide
silicon
Silicon substrate
substrate silicon substrate
Silicon substrate

Resulting pattern after

the resist is developed.

11/80
 Eight Steps of Photolithography
UV Light

λ
HMDS Resist Mask

1) Vapor prime 2) Spin coat 3) Soft bake 4) Alignment

and Exposure

5) Post-exposure 6) Develop 7) Hard bake 8) Develop inspect

bake

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 Photolithography Bay in a Sub-micron
Wafer Fab
• It is to photograph the image of a circuit pattern onto the photoresist that coats the
wafer surface.
• Yellow fluorescent does not affect photoresist, but sensitive to UV

13/80
 Simplified Schematic of a
Photolithography Processing Module

Wafer Stepper
(Alignment/Exposure System)
Vapor Resist Develop- Edge-Bead
Load Station Prime Coat Rinse Removal Transfer Station

Wafer
Cassettes Wafer Transfer System

Soft Cool Cool Hard

Bake Plate Plate Bake

Note: wafers flow from photolithography into only two other areas: etch and ion implant

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 Etch: Dissociation
• Electron collides with a molecule, it can
break the chemical bond and generate free
radicals:
e + AB A+B+ e
• Free radicals have at least one unpaired
electron and are chemically very reactive.
• Increasing chemical reaction rate
• Very important for both etch and CVD.

15/80
 Simplified Schematic of Dry Plasma Etcher
• The etch process creates a permanent pattern on the wafer in areas not protected by
the photoresist pattern
• Including: dry etching, wet etching and photoresist stripper
• After dry etching: photoresist stripper + wet cleaning

Etchant gas entering

Gas distribution baffle gas inlet High-frequency energy
Anode electrode
RF coax cable
Photon
Electromagnetic field
- Glow discharge
Free electron - e λ (plasma)
e
Vacuum gauge
Ion sheath e
- Wafer

Cathode electrode
+ R
Chamber wall
Flow of byproducts and
process gases
Positive ion Radical
chemical
Exhaust to
vacuum pump
Vacuum line
16/80
 Wet Chemical Isotropic Etch
• Etch profile refers to the shape of the sidewall of the etched
feature
• Isotropic etch profile leads to a undercutting, results in an
undesirable loss of the linewidth

Isotropic etch - etches in all

directions at the same rate

Resist

Film

Substrate

17/80
 Anisotropic Etch with Vertical Etch Profile
• The rate of etching is on only one direction perpendicular to the wafer surface
• There is very little lateral etching activity
• This leaves vertical sidewalls, permitting a higher packing density of etched
features on the chip
• With smaller geometries, the etch profiles have higher aspect ratios
• It is difficult to get etchant chemicals in and reaction by-products out of the
high-aspect ratio openings
Anisotropic etch - etches
in only one direction

Resist

Film

Substrate
18/80
 Implantation: Common Dopants Used
in Semiconductor Manufacturing
• Doping is the introduction of a dopant into the crystal structure of a
semiconductor material to modify its electronic properties
• Dopants are referred to as impurities
• Two techniques: thermal diffusion and ion implantation (dominant)
Acceptor Dopant Donor Dopant
Semiconductor
Group IIIA Group VA
Group IVA
(P-Type) (N-Type)
Atomic Atomic Atomic
Element Element Element
Number Number Number
Boron (B) 5 Carbon 6 Nitrogen 7
Aluminum 13 Silicon (Si) 14 Phosphorus (P) 15
Gallium 31 Germanium 32 Arsenic (As) 33
Indium 49 Tin 50 Antimony 51

19/80
General Schematic of an Ion Implanter
• Ion source: positive charge
• Extraction assembly: extract ions
• Mass Analyzer: form a beam of the desired dopant ions
• Acceleration column: to attain a high velocity

Ion source

Plasma
Extraction assembly

Analyzing magnet
Acceleration
Ion beam column Process
chamber

Scanning
disk

20/80
 Annealing of Silicon Crystal

Ion Beam

Repaired Si lattice structure and

activated dopant-silicon bonds

a) Damaged Si lattice during implant b) Si lattice after annealing

• Using Furnace or RTA, hot-wall furnace using high temperature causes extensive
dopant diffusion and is undesirable
• RTA minimizes a phenomenon known as transient enhanced diffusion, to achieve
acceptable junction depth control in shallow implants (~150°C/sec)

21/80
Thin Film Metallization Bay

22/80
 Simple Parallel Plate DC Diode Sputtering System

Cathode (-)
Metal target
1) Electric fields + 2) High-energy Ar+ ions
+ +
create Ar+ ions. collide with metal target.
+ +
e-
Gas delivery
e- e-
Argon atoms
3) Metallic atoms are
dislodged from target. Exhaust
Plasma

6) Excess matter is removed from

Electric field chamber by a vacuum pump.
4) Metal atoms migrate toward substrate.

DC diode sputterer
5) Metal deposits on substrate

Substrate
Anode (+)

23/80
Simplified Schematics of CVD Processing System

Gas inlet

Process chamber Capacitive-

coupled RF input

Chemical vapor deposition

Wafer
Susceptor

Exhaust

Heat lamps

CVD cluster tool

24/80
 Schematic of CVD Transport and
Reaction 8 Steps

1) Mass transport
of reactants CVD Reactor
Gas delivery

7) Desorption of 8) By-product
byproducts removal
2) Film precursor
reactions By-products
Exhaust

3) Diffusion of
gas molecules
5) Precursor
diffusion into 6) Surface reactions Continuous film
4) Adsorption of substrate
precursors

Substrate

25/80
 CVD Reaction

• Take place on wafer surface: heterogeneous reaction

(surface catalyzed).
• Homogeneous reaction: above surface (gas reaction),
which is poor adhesion, low-density with high defects
• SiH4  SiH2 +H2 ( SiH2 is precursor, it is pyrolysis)
• CVD reaction steps are sequential, the slowest step defines
the bottleneck

26/80
 LPCVD Reaction Chamber for Deposition
of Oxides, Nitrides, or Polysilicon
Three-zone heating element
Pressure gauge

Exhaust to
vacuum pump

Gas inlet
Profile thermocouples
(internal)
Spike thermocouples (external, control)

• Limited by surface reaction, flow condition is not important

• Films are uniformly deposited on a large number of wafer surface as
long as the temperature is tightly controlled
• Conformal film coverage on the wafer
• Low growth rate than APCVD and need routine maintenance
• In-situ clean, using ClF3 or NF3
27/80
• 3SiCl2H2 + 4NH3  Si3N4 + 6HCl + 6H2
 Polish Bay in a Sub-micron Wafer Fab
• Chemical mechanical planarization (CMP) process is to planarize the top
surface of the wafer by lowering the high topography to be level with the lower
surface area of the wafer
• It combines chemical etching and mechanical abrading to remove layer

28/80
 Schematic of Chemical Mechanical
Planarization (CMP)
Step height: etchback ~ 7000Å vs. CMP ~ 50Å

Downforce
Wafer carrier Polishing pad
Slurry dispenser
Wafer
Polishing
Rotating slurry
platen

• CMP achieves wafer planarity by removing high features on the surface

more quickly relative to the low feature (high pressure by Preston’s eq.)
• Both metal and dielectric layers can be removed
29/80
30/80
31/80
Biasing Circuit for an NMOS Transistor
S1

Open gate (no charge)

VGG = + 0.7 V

Gate
Source Drain
n+ n+

p-type silicon substrate

Lamp
(no conduction)

VDD = + 3.0 V

Figure 3.16 32/80

NMOS Transistor in Conduction Mode
S1

VGG = + 0.7 V Positive charge

Gate
e- ++++++
++++++
Source ++++++ Drain IDS
n+ n+
Holes Lamp
p-type silicon substrate

e- e-

VDD = + 3.0 V

33/80
Biasing Circuit for a P-Channel MOSFET
S1
Open gate (no charge)
VGG = - 0.7 V
Gate
Source Drain
p+ p+

n-type silicon substrate

Lamp
(no conduction)

VDD = -3.0 V

34/80
PMOS Transistor in Conduction Mode
S1

VGG = - 0.7 V Negative charge

Gate
--------
e- Source
--------
-------- Drain IDS
p+ p+
Electrons
n-type silicon substrate Lamp

e- e-
VDD = - 3.0 V

35/80
Schematic of a CMOS Inverter
+ VDD

S
G
pMOSFET

Input Output

nMOSFET
G
S

- VSS

36/80
Cross-section of CMOS Inverter

37/80
 CMOS Manufacturing Steps
1. Twin-well Implants 14
Passivation layer
Bonding pad metal
2. Shallow Trench Isolation ILD-6

3. Gate Structure
ILD-5
4. Lightly Doped Drain Implants M-4
13
5. Sidewall Spacer ILD-4

M-3
6. Source/Drain Implants
ILD-3
12
7. Contact Formation M-2

8. Local Interconnect 11 ILD-2

M-1 10
9. Interlayer Dielectric to Via-1
Via
9 ILD-1
10. First Metal Layer Poly gate
8 LI metal 5 LI oxide
11. Second ILD to Via-2 3
n+ 2 p+ p+ STI n+ n+ p+
12. Second Metal Layer to Via-3 4 6
7 n-well p-well
13. Metal-3 to Pad Etch 1
p- Epitaxial layer
14. Parametric Testing
p+ Silicon substrate

38/80
 n-well Formation

• Epitaxial layer : improved quality and fewer defect

• In step 2, initial oxide (15 nm) : (1) protects epi layer
from contamination, (2) prevents excessive damage to
ion/implantation, (3) control the depth of the dopant
during implantation
• In step 5, anneal: (1) drive-in, (2) repair damage, (3)
activation
Phosphorus implant

Thin
Polish
Films 3 Photoresist
2 3
2
1
Diffusion Photo Etch Oxide 4 n-well
5
5 4 ~5 um
Implant
1 p- Epitaxial layer
p+ Silicon substrate (Dia = 200 mm, ~2 mm thick)

39/80
Mask # 1 : N-well formation

40/80
 p-well Formation

• 2nd mask, this mask is the direct opposite of the n-well implant mask
• Boron is 1/3 the mass of P, so 1/3 energy is used.

Boron implant

Thin
Polish
Films 1 Photoresist
1

Diffusion Photo Etch Oxide

n-well 2 p-well 3
3 2

Implant p- Epitaxial layer

p+ Silicon substrate

41/80
Mask # 2 : P-well formation

42/80
 STI Trench Etch
STI: shallow trench isolation

• Barrier oxide: a new oxide

• Nitride: (1) protect active region, (2) stop layer during CMP
• 3rd mask
• STI etching

Selective etching opens isolation regions in the epi layer.

+Ions
Thin
Polish
3 Photoresist
Films
4
1 2 3 4 2 Nitride
1 Oxide
Diffusion Photo Etch
n-well p-well
STI trench
Implant p- Epitaxial layer
p+ Silicon substrate

43/80
Mask # 3: Shallow Trench Isolation formation
44/80
 STI Oxide Fill

• Liner oxide to improve the interface between the silicon and

trench CVD oxide
• CVD oxide deposition or spin-on-glass (SOG)

Trench fill by chemical vapor deposition

Oxide

2
2 Thin
Films Polish Trench CVD oxide
1 Nitride
1
Diffusion Photo Etch
n-well p-well
Liner oxide
Implant p- Epitaxial layer
p+ Silicon substrate

45/80
 STI Formation

1. Trench oxide polish (CMP): nitride as the CMP stop layer

since nitride is harder than oxide
2. Nitride strip: hot phosphoric acid
3. Anti-punch-through and Vth adjustment ion implantation

Planarization by chemical-mechanical polishing

1
1
Thin Polish
Films
STI oxide after polish
2
2 Nitride strip

Diffusion Photo Etch

n-well p-well
Liner oxide
Implant p- Epitaxial layer
p+ Silicon substrate

46/80
 Poly Gate Structure Process
• Oxide thickness 1.5 ~ 5.0 nm is thermal grown
• Poly-Si ~ 300 nm is doped and deposited in LPCVD using SiH4
• Need Antireflective coating (ARC), very critical
• The most critical etching step in dry etching

3 Photoresist
Polysilicon
Thin deposition 2 ARC 4 Poly gate etch
Polish
Films
1 2 3 4 1 Gate oxide

Diffusion Photo Etch

n-well p-well

Implant p- Epitaxial layer

p+ Silicon substrate

47/80
Mask # 4 :Poly-Si gate formation
48/80
 n− LDD Implant

• LDD: lightly doped drain to reduce S/D leakage

• Large mass implant (BF2, instead of B, As instead of P) and
amorphous surface helps maintain a shallow junction
• 5th mask

2 Arsenic n- LDD implant

Thin Polish 1 Photoresist mask

Films
1

Diffusion Photo Etch n- n- n-

n-well p-well
2

Implant p- Epitaxial layer

p+ Silicon substrate

49/80
Mask # 5: N- LDD formation
50/80
 p− LDD Implant

• 6th mask
• In modern device, high doped drain is used to reduce series
resistance. It called S/D extension

2 BF2 p- LDD implant

Thin Photoresist Mask

Polish Photoresist mask
1 1
Films
1

Diffusion Photo Etch n- p- p- n- n- p-

n-well p-well
2

Implant p- Epitaxial layer

p+ Silicon substrate

51/80
Mask # 6: P- LDD formation
52/80
 Side Wall Spacer Formation

• Spacer is used to prevent higher S/D implant from penetrating

too close to the channel, cover LDD.
• CVD oxide + etch back by anisotropic plasma etching

2 Spacer etchback by anisotropic plasma etcher

Thin Polish
1
Films +Ions
1 Spacer oxide Side wall spacer
2

Diffusion Photo Etch n- p- p- n- n- p-

n-well p-well

Implant p- Epitaxial layer

p+ Silicon substrate

53/80
 n+ Source/Drain Implant

• Energy is high than LDD I/I, the junction is deep

• 7th mask

2 Arsenic n+ S/D implant

Thin Polish 1 Photoresist mask

Films
1

Diffusion Photo Etch n+ p-well n+

n+ n-well
2

Implant p- Epitaxial layer

p+ Silicon substrate

54/80
Mask # 7: N+ Source/Drain formation

55/80
 p+ Source/Drain Implant

• 8th mask
• Using rapid thermal anneal (RTA) to prevent dopant
spreading and to control diffusion of dopant

2 Boron p+ S/D implant

Thin Photoresist Mask

Polish Photoresist mask
1 1
Films
1

Diffusion Photo Etch

n+ p+ n-well p+ n+ p-well n+ p+
3 2

Implant p- Epitaxial layer

p+ Silicon substrate

56/80
Mask # 8 : P+ Source/Drain formation
57/80
 Contact Formation
• Titanium (Ti) is a good choice for metal contact due to low
resistivity and good adhesion
• No mask needed, called self-align
• Using Ar to sputtering metal
• Anneal to form TiSi2, tisilicide
• Chemical etching to remove unreact Ti, leaving TiSi2, called
selective etching

1 Titanium depostion

1 2 3 Thin Polish 2 Tisilicide contact formation (anneal)

Films Titanium etch
3

Diffusion Photo Etch p+ n+

n+ p+ n-well n+ p-well p+

Implant p- Epitaxial layer

p+ Silicon substrate

58/80
 LI Oxide as a Dielectric for Inlaid LI Metal
(Damascene)
• Damascene: a name doped of year ago from a practice that began
thousands ago by artist in Damascus, Syria

LI metal

LI oxide

LI: local interconnection

59/80
 LI Oxide Dielectric Formation

• Nitride: protect active region

• Doped oxide
• Oxide polish
• 9th mask

2 Doped oxide CVD

3
2 Thin 1 Nitride CVD 3 Oxide polish 4 LI oxide etch
Polish
1 Films
LI oxide
4
Diffusion Photo Etch
n-well p-well

Implant p- Epitaxial layer

p+ Silicon substrate

60/80
Mask # 9: Local Interconnection formation
61/80
 LI Metal Formation

• Ti/TiN is used: Ti for adhesion and TiN for diffusion barrier

• Tungsten (W) is preferred over Aluminum (Al) for LI metal
due to its ability to fill holes without leaving voids

1 2 3 4
Ti/TiN 3 Tungsten 4 LI tungsten polish
2 deposition deposition
Thin Polish
Films
LI oxide

Diffusion Photo Etch

1 n-well p-well
Ti deposition
Implant p- Epitaxial layer
p+ Silicon substrate

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 Via-1 Formation

• Interlayer dielectric (ILD): insulator between metal (800nm)

• Via: electrical pathway from one metal layer to adjacent metal layer
• 10th mask

1 ILD-1 oxide ILD-1 oxide etch

deposition 2 Oxide polish 3 (Via-1 formation)

2
ILD-1
Thin
1 Films Polish
LI oxide
3
Diffusion Photo Etch
n-well p-well

Implant p- Epitaxial layer

p+ Silicon substrate

63/80
Mask # 10: Via-1 formation
64/80
 Plug-1 Formation

• Ti layer as a glue layer to hold W

• TiN layer as the diffusion barrier
• Tungsten (W) as the via
• CMP W-polish

Ti/TiN 3 Tungsten
2 deposition deposition 4Tungsten polish (Plug-1)

1 2 3 4 1 ILD-1
Thin Ti dep.
Films Polish
LI oxide

Diffusion Photo Etch

n-well p-well

Implant p- Epitaxial layer

p+ Silicon substrate

65/80
 SEM Micrographs of Polysilicon,
Tungsten LI and Tungsten Plugs

Tungsten LI Polysilicon

Tungsten
plug

Mag. 17,000 X

Micrograph courtesy of Integrated Circuit Engineering

66/80
 Metal-1 Interconnect Formation

• Metal stack: Ti/Al (or Cu)/TiN is used

• Al(99%) + Cu (1%) is used to improve reliability
• 11th mask

Ti Deposition Al + Cu (1%) TiN

2 deposition 3 deposition 4 Metal-1 etch
1

1 2 3
ILD-1
Thin Polish
Films
LI oxide
4
Diffusion Photo Etch
n-well p-well

Implant p- Epitaxial layer

p+ Silicon substrate

67/80
 Common gate for input

P+ Source to Vdd N+ Source to ground

Common drain or output to next stage

Mask # 11: Metal-1 formation

68/80
SEM Micrographs of First Metal Layer
over First Set of Tungsten Vias

TiN metal cap

Metal 1, Al

Tungsten Mag. 17,000 X

plug

Micrograph courtesy of Integrated Circuit Engineering

69/80
 Via-2 Formation

• Gap fill: fill the gap between metal

• Oxide deposition
• Oxide polish
• 12th mask

ILD-2 oxide ILD-2 oxide etch

2 deposition
3 Oxide polish 4 (Via-2 formation)

1 ILD-2 gap fill

1 2 3
ILD-1
Thin
Polish
Films
LI oxide
4
Diffusion Photo Etch
n-well p-well

Implant p- Epitaxial layer

p+ Silicon substrate

70/80
Mask # 12: Via-2 formation
71/80
 Plug-2 Formation

• Ti/TiN/W
• CMP W polish

Tungsten
Ti/TiN Tungsten deposition 3
2 deposition 4 polish (Plug-2)

1 Ti deposition ILD-2

1 2 3 4
ILD-1
Thin Polish
Films
LI oxide

Diffusion Photo Etch

n-well p-well

Implant p- Epitaxial layer

p+ Silicon substrate

72/80
Metal-2 Interconnect Formation
• Metal 2: Ti/Al/TiN
• ILD-3 gap filling
• ILD-3
• ILD-polish
• Via-3 etch and via deposition, Ti/TiN/W
Metal-2 deposition ILD-3 oxide 4 Via-3/Plug-3 formation
3 polish
1 to etch
2 Gap fill ILD-3

ILD-2

ILD-1

LI oxide

n-well p-well

p- Epitaxial layer
p+ Silicon substrate
73/80
Mask # 13: Metal-2 formation
74/80
Mask # 14: Via-3 formation
75/80
Mask # 15: Metal-3 formation
76/80
CMOS layout (mask 1 to mask 12)

77/80
 Full 0.18 µm CMOS Cross Section
Passivation layer
Bonding pad metal
ILD-6

ILD-5
• Passivation layer of M-4

nitride is used to ILD-4

M-3
protect from
ILD-3
moisture, scratched,
M-2
and contamination
ILD-2
• ILD-6 : oxide
M-1
Via
ILD-1

Poly gate
LI metal LI oxide

n+ p+ p+ STI n+ n+ p+

n-well p-well

p- Epitaxial layer

p+ Silicon substrate

78/80
SEM Micrograph of Cross-section of AMD
Microprocessor

Mag. 18,250 X
Micrograph courtesy of Integrated Circuit Engineering
79/80
Wafer Electrical Test using a Micromanipulator Prober
(Parametric Testing)

• After metal-1 etch,

wafer is tested, and
after passivation test
again
• Automatically test on
wafer, sort good die (X-
Y position, previous
marked with an red ink)
• Before package, wafer
is backgrind to a
thinner thickness for
easier slice and heat
dissipation

Photo courtesy of Advanced Micro Devices

80/80
81/80