DOC/LP/01/28.02.

02
LESSON PLAN LP – VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS Date: 23/06/14
Unit : I Branch : M.E (AE) Semester: III Page 01 of 06

UNIT I TESTING AND FAULT MODELLING 9

Syllabus:
Introduction to testing – Faults in Digital Circuits – Modeling of faults – Logical Fault
Models – Fault detection – Fault Location – Fault dominance – Logic simulation – Types of
simulation – Delay models – Gate Level Event – driven simulation.

Objective: To know the various types of faults and also to study about fault detection and
dominance.

Session Teaching
Topics to be covered Time Ref
No. Method
1. Introduction to testing - Need for testing 50m 1 BB

2. Faults in Digital Circuits 50m 1,4 BB

3. Faults Modeling - Logical fault models 50m 1,4 BB

4. Fault Detection - Combinational and Sequential circuits 50m 1 BB

5. Fault Location - Combinational and Sequential circuits 50m 1 BB

6. Fault Dominance - Combinational and Sequential circuits 50m 1 BB

7. Logic simulation - Types of simulation 50m 1 BB

8. Delay models 50m 1 BB

9. Gate level Event-driven simulation 50m 1 BB

 DOC/LP/01/28.02.02
LESSON PLAN LP – VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS Date: 23/06/14
Unit : II Branch : M.E (AE) Semester: III Page 02 of 06

UNIT II TEST GENERATION 9

Syllabus:
Test generation for combinational logic circuits – Testable combinational logic circuit
design – Test generation for sequential circuits – design of testable sequential circuits.

Objective: To know the concepts of test generation for combinational and sequential circuits.

Session Teaching
Topics to be covered Time Ref
No. Method
Test Generation for combinational logic circuits -
10. One-dimensional Path sensitization and Boolean 50m 2,4 BB
Difference
Test Generation for combinational logic circuits -
11. 50m 2,5 BB/PPT
D-Algorithm
Test Generation for combinational logic circuits -
12. 50m 2 BB/PPT
PODEM
Testable combinational logic circuit design -
13. 50m 2 BB/PPT
Reed-Muller Expansion Technique
Testable combinational logic circuit design -
14. Three level OR-AND-OR design and Syndrome- 50m 2 BB/PPT
testable design
CAT I 90m
Test generation for sequential circuits - Iterative
15. 50m 2,5 BB/PPT
Combinational circuits
Test generation for sequential circuits - State
16. 50m 2,5 BB
Table verification
17. Design of testable sequential circuits 50m 2 BB
Design of testable sequential circuits - Scan-path
18. 50m 2 BB
technique
 DOC/LP/01/28.02.02
LESSON PLAN LP – VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS Date: 23/06/14
Unit : III Branch : M.E (AE) Semester: III Page 03 of 06

UNIT III DESIGN FOR TESTABILITY 9

Syllabus:
Design for Testability – Ad-hoc design – generic scan based design – classical scan based
design – system level DFT approaches.

Objective: To understand the concepts of test generation method - DFT.

Session Teaching
Topics to be covered Time Ref
No. Method
19. Testability - Controllability and Observability 50m 1,3 BB
Adhoc design for testability techniques - Test points,
20. 50m 1,4 BB
Initialization, Monostable Multivibrators
Adhoc design for testability techniques - Oscillator
21. 50m 1,4 BB
and clocks, Partitioning counters and shift registers
Adhoc design for testability techniques - Partitioning
22. of Large combinational circuits, Logical redundancy, 50m 1,4 BB
Global feedback paths
Generic scan based design - Full serial integrated
23. 50m 1 PPT
scan
Generic scan based design - Isolated serial scan and
24. 50m 1 PPT
Nonserial scan
25. Classical scan based design 50m 1 PPT/ICT
Classical scan based design - Level-Sensitive Scan
26. 50m 1 PPT
Design (LSSD)
System-level DFT approaches - system level busses,
27. 50m 1 PPT
system-level scan paths
 DOC/LP/01/28.02.02
LESSON PLAN LP – VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS Date: 23/06/14
Unit : IV Branch : M.E (AE) Semester: III Page 04 of 06

UNIT IV SELF – TEST AND TEST ALGORITHMS 9

Syllabus:
Built-In self Test – test pattern generation for BIST – Circular BIST – BIST Architectures
– Testable Memory Design – Test Algorithms – Test generation for Embedded RAMs.

Objective: To study the concepts of test generation method - BIST.

Session Teaching
Topics to be covered Time Ref
No. Method
28. Introduction to BIST concepts 50m 1,6 BB/ICT
Test pattern generation for BIST - Exhaustive
29. testing, Pseudorandom testing, Pseudoexhaustive 50m 1 BB
testing
CAT II 90m
Test pattern generation for BIST - Logical
segmentation, Constant-weight patterns,
30. 50m 1,4 BB
Identification of test signal inputs, Physical
segmentation
31. Circular BIST 50m 1,5 BB
BIST Architecture - CSBL, BEST, RTS, LOCST,
32. 50m 1,5 BB
STUMPS
BIST Architecture - CBIST, CEBS, RTD, SST,
33. 50m 5 BB
CATS, BILBO
34. Testable Memory Design 50m 5 BB

35. Test Algorithms 50m 5 BB

36. Test generation for Embedded RAMs 50m 5 BB

 DOC/LP/01/28.02.02
LESSON PLAN LP – VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS Date: 23/06/14
Unit : V Branch : M.E (AE) Semester: III Page 05 of 06

UNIT V FAULT DIAGNOSIS 9

Syllabus:
Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for
Combinational Circuits – Self-checking design – System Level Diagnosis.

Objective: To understand the fault diagnosis method.

Session Teaching
Topics to be covered Time Ref
No. Method
37. Logical level diagnosis - basic concepts 50m 1 BB

38. Diagnosis by UUT reduction 50m 1 BB

39. Fault Diagnosis for Combinational Circuits 50m 1,5 BB

Self Checking design - multiple bit errors, Checking
40. 50m 1 BB
circuits and self-checking
Self Checking design - self-checking checkers,
41. 50m 1 BB
Parity-check function
Self Checking design - Totally self-checking m/n
42. 50m 1 BB
code and equality checkers, Berger code checker
43. Self Checking Combinational circuits 50m 1 BB

44. Self Checking sequential circuits 50m 1 BB

45. System level Diagnosis 50m 1 BB

CAT III 90m

 DOC/LP/01/28.02.02
LESSON PLAN LP – VL7301
LP Rev. No: 00
Sub Code & Name: VL7301 TESTING OF VLSI CIRCUITS Date: 23/06/14
Branch : M.E. (Applied Electronics) Semester: III Page 06 of 06

Course Delivery Plan:

1 2 3 4 5 6 7 8 9 10 11 12
Week I II I II I II I II I II I II I II I II I II I II I II I II

Unit I II III IV V

REFERENCES:
CAT I CAT II CAT III
1. M.Abramovici, M.A.Breuer and A.D. Friedman, “Digital systems and Testable Design”,
Jaico Publishing House, 2002.
2. P.K. Lala, “Fault Tolerant and Fault Testable Hardware Design”, Academic Press, 2012.
3. P.K. Lala, “Digital Circuit Testing and Testability”, Academic Press, 2002.
4. M.L.Bushnell and V.D.Agrawal, “Essentials of Electronic Testing for Digital, Memory
and Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers, 2002.
5. A.L.Crouch, “Design Test for Digital IC’s and Embedded Core Systems”, Prentice Hall
International, 2002.
6. http://nptel.ac.in/courses/106103016/30

Prepared by Approved by

Signature

Name Ms.R.Kousalya Dr.S.Ganesh Vaidyanathan

Designation Assistant Professor HoD - EC
Date 23/06/2014 23/06/2014