INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT) ISSN No.

2394-9007
Vol. V, No. II, April 2018 www.ijrtonline.org

Design & Simulation of Digital Phase Locked Loop

using MOSFET SPICE Models of 300nm
Piyush Mahalka, Preeti Moolani, Ayoush Johari

Abstract— In this paper we present a Delay Phase locked loop
(DLL) design which can be used for a variety of applications.
Specifically, we have built a DPLL which is able to generate
multiple clock phases/delays with low jitter, short locking time,
and wide lock range. To achieve this design goal, several
techniques and algorithms are used in our design. Both phase-
locked loops (PLLs) and DPLLs are extensively used in many
timing circuits. When either a DPLL or a PLL can be used, a
DPLL is preferred in many cases because of its better stability,
less jitter accumulation, and faster locking time compared to a
PLL. Therefore, in our research, we have identified that the best
circuit to generate stable time delays on chip is a DPLL. The
basic simulations were carried out with LT-SPICE. Process
technology used for SPICE simulation is 300nm.
Keywords: Include at least 5 keywords or phrases.
II. DELAY PHASE LOCKED LOOP
A DLL consists of three basic blocks: a phase detector (PD), a
charge pump (CP), a low pass filter (LP) and a voltage-
controlled oscillator (VCO). Fig.1 shows the block diagram of
the DLL. For a DPLL, locking time, lock range and jitter
performance are the most important metrics. Locking time
refers to the time interval a DPLL takes to achieve a stable
locking state from an initial state. Basically, locking time
depends on the speed of the PD, the magnitude of the charging
or discharging current in the CP, and the overall delay loop
bandwidth. Lock range refers to the maximum and minimum
delays of the VCO, which set the range in which the delay of
the VCO can be varied.

I. INTRODUCTION
A DLL is widely used as a timing circuit in many systems for
clock generation, clock distribution, signal synchronization,
frequency synthesis and others. A DLL provides multiple
clock signals which are separated from each other by a well-
controlled phase shift (delay). When appropriate logic is
given, a new clock signal which is of a different frequency can Fig. 1: Block diagram of DPLL
be generated by the DLL. DLL is also used for the purpose of
A DPLL is able to achieve lock only in this range. Lock range
clock deskewing in synchronous data transfer among
directly affects the operating frequency range of a DPLL.
communication chips. Reducing clock skew has become
Phase noise, or time jitter, is the random variations of the
increasingly important with higher clock frequency. A DLL
period or phase of a clock signal. With the constantly rising
for this application requires rapid lock time and excellent
data rate or clock frequency, the clock period becomes
phase alignment between the reference signal and the ultimate
increasingly smaller, and so does the tolerance to the amount of
output signal.
time jitter.
III. PHASE FREQUENCY DETECTORS
A schematic diagram of the phase frequency detector is shown
in Fig.2. The output of the PFD depends on both the phase and
frequency of the inputs. This type of phase detector is also
termed a sequential phase detector. It compares the leading
Manuscript received on April, 2018.
edges of the data and dclock. A dclock rising edge cannot be
Piyush Mahalka, Research Scholar, Department of Electronics & present without a data rising edge. If the rising edge of the
Communication Engineering, Lakshmi Narain College of Technology & data leads the dclock rising edge, the "up" output of the phase
Science, Bhopal, M.P., India.
detector goes high, while the Down output remains low. This
Preeti Moolani, Research Scholar, Department of Electronics & causes the dclock frequency to increase, having the effect of
Communication Engineering, Lakshmi Narain College of Technology &
Science, Bhopal, M.P., India.
moving the edges closer together. When the dclock signal
leads the data (Fig. 19.11b), Up remains low, while the Down
Prof. Ayoush Johari, Asst. Professor, Department of Electronics & goes high a time equal to the phase difference between dclock
Communication Engineering, Lakshmi Narain College of Technology &
Science, Bhopal, M.P., India.

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INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT)
Vol. V, No. II, April 2018
and data. The output of the PFD should be combined into a
single output for driving the loop filter.
Fig. 2: PD blocks diagram using xor and not gate.
Fig. 3: Nand gate with 2 input.
Fig. 4: Nand gate with 4 input.
IV. THE LOOP FILTER
The loop filter is the brain of the DPLL. If the loop-filter
values are not selected correctly, it may take the loop too long
to lock, or once locked, small variations in the input data may
cause the loop to unlock
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V. CHARGE PUMP
A single ended switch at the source charge pump is used. The
current mismatch between source current and sink current is
reduced by ensuring that the source current is the same as the
sink current; thus experiencing the same process variations.
Generally, in CMOS circuits, current switching provides a
faster switching speed than voltage switching.
VI. VCO
Voltage-controlled device (VCO) is a type of oscillator which
generates the frequency oscillations controlled by the input
voltage. VCOs are used in function generators by applying
a modulating signal to the control input. They are usually used
in PLL for radio receivers. A VCO is also an integral part of
a DPLL.
Fig. 5: Block diagram of VCO
VII. FREQUENCY DIVIDER
Frequency divider is used to increase the time period of the
output signal before it is used by PFD as feedback input. In this
paper, frequency divider used divides the frequency twice and
successively increases the time period twice.
Fig. 6: Frequency Divider
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INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT)
Vol. V, No. II, April 2018
VIII. DESIGN & SIMULATION RESULTS
The LTSPICE post –layout simulation results are based on
0.05 µm CMOS technology. It can be operated at frequency 3
GHz. Fig.7 shows the eye diagram of DLL.
Fig. 7: Eye Diagram of DLL
Fig. 8 shows the output result of PD compared with the
Vdclock and Vdata collectively. Fig. 9 shows the input that is
fed into VCO.
Fig. 8: Output of PD up compared with input values.
Fig. 9: Vin to the VCO
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TABLE I: COMPARISON OF FREQUENCY, MAGNITUDE AND
PHASE ANGLE
The frequency response in the BODE plot is shown below in
the Fig.10 of vclock. This can be used at 3-4 GHz as it is noise
free successively.
Fig. 10: BODE Plot of V Clock
IX. CONCLUSION
This paper has presented the design of DLL based on the
0.05µm.There is satisfactory performance of DLL in the
frequency range upto 3GHz.there are several possible solution
to improve the DLL performance for longer range of
frequency. This design will subsequently increase the speed of
the system, which can be used in the clock and data recovery
and transmission circuits.
REFERENCES
1. Dian Huang, Ying Qiao, “A fast locked all digital phase locked loop for
dynamic frequency scaling”.
2. Rajeshwari, D. S., P. V. Rao, and V. Rajesh. "Charge Pump with
Improved High-Swing Cascode Current Source for Accurate Current
Matching in DPLL." Artificial Intelligence and Evolutionary
Computations in Engineering Systems. Springer India, 2016. 39-47.
3. Ahmad, Fazil, et al. "19.1 A 0.5-to-9.5 GHz 1.2 s-lock-time fractional-N
DPLL with 1.25% UI period jitter in 16nm CMOS for dynamic
frequency and core-count scaling in SoC." 2016 IEEE International
Solid-State Circuits Conference (ISSCC). IEEE, 2016.
4. Wagdy, Mahmoud Fawzy, and Syed Zeeshan Ahmed Kabeer. "Flash
fast-locking digital PLL using LT SPICE." 2015 11th International
Computer Engineering Conference (ICENCO). IEEE, 2015.
5. Bhattacharyya, Sabyasachi, et al. "Zero crossing DPLL based phase
recovery system and its application in wireless communication."
40
INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY (IJRT)
Vol. V, No. II, April 2018
Computer, Communication and Control (IC4), 2015 International
Conference on. IEEE, 2015.
6. Yelne, P.N. and Karule, P.T., 2015, April. Design of Frequency
modulated receiver using Digital phase locked loop. In Communications
and Signal Processing (ICCSP), 2015 International Conference on (pp.
0889-0892). IEEE.
7. Rodarte-Gutierrez, Francisco E., Ismael Araujo-Vargas, and Jazmin
Ramirez Hernandez. "FPGA Implementation of a Three-Phase PLL and
a Space Vector Modulator of a Matrix Converter for Future Electric
Vehicles." Vehicle Power and Propulsion Conference (VPPC), 2015
IEEE. IEEE, 2015.
8. Yadav, Prashant Ranjan, Ranjit Pathak, and Rajiv Bisen. "Minimization
of Lock Time and Analysis Of Ripple Voltage Of Digital Phase Locked
Loop (DPLL)." (2015).
9. Berger, Ulrich, Andrew Lawrence, Fredrik Nordvall Forsberg, and
Monika Seisen berger. "Extracting verified decision procedures: DPLL
and Resolution." arXiv preprint arXiv: 1502.02131 (2015).
10. Bhattacharyya, Sabyasachi, Ripunjoy Sarma, Kaustubh Bhattacharyya,
Ragib Nasir Ahmed, and Roushan Saikia. "MUX-based design of DPLL
for wireless communication." In Information Communication and
Embedded Systems (ICICES), 2014 International Conference on, pp. 1-
4. IEEE, 2014.
11. Al‐ Ali, Omar Al‐ Kharji, Nader Anani, Saleh Al‐ Araji, and Mahmoud
Al‐ Qutayri. "A non-uniform DPLL architecture for optimized
performance." IEEJ Transactions on Electrical and Electronic
Engineering 9, no. 1 (2014): 15-23.
12. Bhattacharyya, Sabyasachi, et al. "Efficient design of DPLL system for
wireless communication." the Proceedings of Second National
Conference on Recent Advances in Technology and Engineering (RATE
2013), Aligarh, Uttar Pradesh, India.
13. You, Bo, Jie Wang, and Songyang Li. "FPGA-based induction heating
with variable modulus control all-digital Phase-Locked Loop
research."Measurement, Information and Control (ICMIC), 2013
International Conference on. Vol. 2. IEEE, 2013.
14. Gayathri, M. G. "Design of All Digital Phase Locked Loop in
VHDL."International Journal of Engineering Research and Applications
(IJERA), ISSN: 2248-9622.
15. Langote, Rajessh B., and A. P. Khandait. "Design and SILMULATION
of High Speed Digital Phase Locked Loop."
16. Hasan, Md, and GoangSeog Choi. "A DPLL with a Modified Phase
Frequency Detector to Reduce Lock Time." Journal of the Institute of
Electronics and Information Engineers 50.10 (2013): 76-81.
17. HE, Dao-kun, Wei XU, and Wei WANG. "Design of a Digital Phase-
locked Loop Based on DSP." Research and Exploration in Laboratory 2
(2013): 068.
18. H.-J. Hsu et al, “A Low-Jitter ADPLL via a Suppressive Digital Filter
and an Interpolation-Based Locking Scheme”, IEEE Trans on VLSI
Systems, vol.19, pp.165-170, Jan. 2011
19. C.-C. Chung et al. “A Fast Tracking ADPLL for Video Pixel Clock
Generation in 65nm CMOS Technology”, IEEE Journal of Solid State
Circuits, vol. 40, pp. 2300-2311, Oct.2011
20. D.-S. Kim et al. “A 0.3-1.4 GHz All-Digital Fractional-N PLL With
Adaptive Loop Gain Controller,” IEEE Journal of Solid State
Circuits,vol. 45, pp. 2300-2311, Nov.2011
21. C. C. Hung et al, “A 40-GHz Fast-Locked All-Digital Phase-Locked
Loop Using a Modified BangBang Algorithm,” IEEE Transactions on
Impact Factor: 4.012
Published under
Asian Research & Training Publication
ISO 9001:2015 Certified
ISSN No. 2394-9007
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Circuits and Systems II: Express Briefs, vol. 58, pp. 321 -325, June
2011.
22. S. Y. Yang et al, “A 7.1mW, 10GHz All Digital Frequency Synthesizer
With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS
Technology,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 578-586,
Mar. 2010;
23. N.D.Dalt, “A Design-Oriented Study of Nonlinear Dynamics of Digital
Bang-Bang PLLs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54
no.2, pp. 181 -185, Feb. 2010
24. S. Y. Yang et al, “A 7.1mW, 10GHz All Digital Frequency Synthesizer
With Dynamically Reconfigured Digital Loop Filter in 90 nm
CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 45,
pp. 578-586, Mar. 2010;
25. Arakali, S.Gondi, and P.K. Hanumolu, “Analysis and Design Technique
for Supply Noise Mitigation in Phase-Locked Loops”, IEEE Transaction
on circuits and System---I: Regular Papers, Vol. 57 No.11 Nov 2010.
26. Quan Sun, Ypnguang Zhang, Christine Hu-Guo, Kimmo Jaaskelainen
and Yann Hu, “A fully integrated CMOS voltage regulator for supply-
noise-insensitive charge pump PLL design, ” Microelectronics Journal,
Vol. 41, Issue 4, April 2010, Pages 240-246.
27. S.J.Li, and H.H.Hsieh,” A 10 GHz Phase-Locked Loop with a Compact
Low-Pass Filter in 0.18 µm CMOS Technology”, IEEE Microwave and
Wireless Components Letters, VOL. 19, NO. 10, OCTOBER 2009
28. H.Janardhan and M.F Wagdy “Design of a 1 GHz Digital PLL Using
0.18 µm CMOS Technology,” IEEE Proc. Of the Third International
Conference on Information Technology 2006.
29. S.M.Kang, and Y.Leblebici, “CMOS Digital Integrated Circuits:
Analysis and Design,” McGraw-Hill Publication, 3 rd Edition, 2003.
30. Moon Seok Kim, Yong Bin Kim, Kyung Ki Kim, “All digital phase
locked loop with local passive interpolation time to digital converter
based on tristate inverter ” IEEE transactions 2012R.E. Best, “Phase
Locked Loops Design, Simulation and Applications,” McGraw-Hill
Publication, 5th Edition, 2003.
31. Youngshin Woo , Young Min Jang and Man Young Sung, “Phase-
locked loop with dual phase frequenct detector for high-frequency
operation and fast acquisition,” Microelectronics Journal, Vol. 33, Issue
3, March 2002,pages 245-252.
32. M.Mansuri, D.Liu, and C.K.Yang, “Fast Frequency Acquisition Phase
Frequency Detector for G Samples/s Phase Locked Loops,” IEEE
Journal of Solid State Circuit, Vol. 37, No. 10, Oct., 2002
33. B. Razavi “Design of Analog CMOS Integrated Circuits, ” Tata
McGraw Hill Edition, 2002
34. R.J.Baker, H.W.Li, and D.E.Boyce, “CMOS Circuit Design, Layout,
and Simulation,” IEEE Press Series on Microelectronic Systems, 2002
35. S. M. Shahruz, “Novel phase-locked loops with enhanced locking
capabilities,” Journal of Sound and Vibration, Vol. 241, Issue 3, 29
March 2001, Pages 513-523
36. Dan H. Wolaver, “Phase Locked Loop Circuit Design,” Prentice Hall
Publication, 1991.
37. Boise state university online tutorials at
http://cmosedu.com/cmos1/electric/electric.htm.
38. VLSI Open Source CAD Tools http://www.vlsiacademy.org/open-
source-cad-tools.html
39. Electric Static Free Software. July 2004 http://www.staticfreesoft.com
41