Вы находитесь на странице: 1из 7

See

discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/308499637

A new basic unit for cascaded multilevel


inverters with reduced number of power
electronic devices

Conference Paper · February 2016


DOI: 10.1109/PEDSTC.2016.7556859

CITATIONS READS

0 17

4 authors, including:

Ebrahim Babaei Carlo Cecati


University of Tabriz Università degli Studi dell'Aquila
226 PUBLICATIONS 1,726 CITATIONS 153 PUBLICATIONS 2,726 CITATIONS

SEE PROFILE SEE PROFILE

All in-text references underlined in blue are linked to publications on ResearchGate, Available from: Ebrahim Babaei
letting you access and read them immediately. Retrieved on: 16 November 2016
7th Power Electronics, Drive Systems & Technologies Conference (PEDSTC 2016)
16-18 Feb. 2016, Iran University of Science and Technology, Tehran, Iran

A New Basic Unit for Cascaded Multilevel Inverters


with Reduced Number of Power Electronic Devices
Ebrahim Babaei1, Member, IEEE, Mohammad Ali Hosseinzadeh2, Maryam Sarbanzadeh3, Carlo Cecati4, Senior
Member, IEEE
1&3
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran
2
Department of Electronic Engineering, University of Applied Science and Technology, Jajarm Branch, Jajarm, Iran
4
Department of Information Engineering, Computer Science and Mathematics, University of L'Aquila, L'Aquila, Italy
E-mails: e-babaei@tabrizu.ac.ir; m.a_hosseinzadeh@yahoo.com; may14_1368@yahoo.com; carlo.cecati@univaq.it

Abstract— In this paper, a new topology for asymmetrical voltage sources have different values. However, the number of
cascaded multilevel inverter is proposed. The proposed topology switching devices still remains high in these topologies.
consists of series connection of several basic units. Reduction of In this paper, first a new topology for basic unit for multilevel
number of power switches, driver circuits, IGBTs and dc voltage inverter is proposed which utilizes lower number of power
sources are some advantages of the proposed topology in
comparison with the conventional cascaded multilevel inverters.
switches and dc voltage sources. Then, series connection of the
In order to generate all output voltage levels, a new algorithm to basic units is proposed as a generalized multilevel inverter. It is
determine the magnitudes of dc voltage sources is proposed. aimed to increase the number of output voltage levels and
Finally, to verify the performance of the proposed inverter, the reduce the number of power switches, driver circuits and total
simulation results by using PSCAD/EMTDC software on a 33- cost of the inverter. In order to generate all positive and
level single-phase inverter are used. negative levels at the output, a new algorithm to determine the
magnitudes of dc voltage sources are proposed. The proposed
Keywords—Asymmetric multilevel inverters; cascaded multilevel inverter is compared with several conventional cascaded
inverter; Basic unit multilevel inverters to investigate its advantages. Finally, the
accuracy performance of the proposed inverter is reconfirmed
I. INTRODUCTION by using simulation results on 33-level proposed inverter.
Multilevel inverters due to many advantages such as high II. PROPOSED BASIC UNIT
quality output waveform, reducing lower order harmonics,
lower switching losses and better electromagnetic interference
In this paper, a new basic unit for asymmetrical cascaded
are used in different applications [1-4]. The conventional
multilevel inverter is proposed. The proposed basic unit for
topologies are divided into three main groups: the neutral point
cascaded multilevel inverter is shown in Fig. 1. As shown in
clamped (NPC) multilevel inverter, flying capacitor (FC)
this figure, the proposed basic unit consists of m dc voltage
multilevel inverter and cascaded H-bridge (CHB) multilevel
inverter [5-9]. Among the multilevel inverter topologies, the sources that their magnitudes can be different values. Each
cascaded multilevel inverters have attracted more attention basic unit consists of m + 5 power switches. The power
mainly because of simple structure and easily of extending to switches used in the basic unit inverter are unidirectional and
higher voltage levels. Cascaded multilevel inverters synthesize bidirectional types. The power switches S 1 , S 3 , S 4 , S 6 , S 7 ,
a desired voltage output based on a series connection of power …, and S m + 5 are unidirectional and two switches S 2 and S 5
cells. In recent years, researchers have presented many various are bidirectional. There are different circuit configurations for
topologies of multilevel inverters for different purposes [10- bidirectional power switches. In this paper, the common
15]. Most of the presented topologies try to reduce the number emitter structure with one gate driver for a switch is used.
of components. One of these topologies is the modular Each unidirectional power switch consists of an IGBT with an
multilevel inverter [16]. This topology is simpler than the anti-parallel diode that is able to conduct current in both
cascaded four-switch H-bridge-based inverter and has several direction and block voltage in one polarity. While, the
advantages [17]. However, the topology does not consider bidirectional power switch includes of two IGBTs with Two
reduction in the number of components. The multilevel inverter anti-parallel diodes that conducts current in both direction and
presented in [18] is based on symmetric topology and uses blocks voltage in two positive and negative polarities. In the
series/parallel connection of the dc voltage sources. This condition, each bidirectional power switch needs one driver
topology uses lower number of switches in comparison with circuit. In the proposed basic unit, if the power switches of S 1 ,
the symmetric CHB. The topologies presented in [13] and [14]
S 4 or S 2 , S 5 or S 3 , S 6 turned on simultaneously, the
consider reduction in the components. These topologies are
basically based on asymmetric topologies; hence, the used dc output voltage will be zero and if the power switches of S 2 ,

978-1-5090-0375-4/16/$31.00 ©2016 IEEE 185


S 6 with each of the switches S 7 ,…, S m + 5 turned on TABLE I. DIFFERENT OUTPUT LEVELS
vo S1 S 2 S3 S 4 S 5 S 6 S 7 S 8 " S m +3 S m + 4 S m +5
simultaneously, the inverter generates positive voltage levels.
0 0 0 0 0 0 1 1 " 0 0 0
In this condition, if S 1 , S m + 5 , S 6 turned on simultaneously, 0 0 0 0 0 1 1 0 0 " 0 0 0
the maximum positive output voltage level ( V1 + Vm ) will be 0 0 1 1 0 0 0 0 0 0 0
generated. To generate the negative output voltage level, the V1 0 0 0 1 0 0 0 1 " 0 0 0
power switches S 3 and S 4 with one of switches S 7 ,…, −V 1 0 0 0 0 1 0 1 0 " 0 0 0
S m + 5 must be turned on simultaneously. In this condition, if V2 0 0 1 0 0 0 1 0 " 0 0 0

the power switches S 3 , S m + 5 , S 4 are turned on −V 2 0 0 0 1 0 1 0 0 " 0 0 0

simultaneously, the maximum negative output voltage level V1 + V 2 0 1 1 0 0 0 0 1 " 0 0 0


−(V1 + Vm ) will be generated. Table I shows the switching − (V 1 + V 2 )
0 0 1 1 0 0 1 0 " 0 0 0
patterns and generated output levels for the proposed basic
unit. As it is obvious from this Table, the proposed basic unit is V 1 +V 3 1 0 0 0 0 1 0 1 " 0 0 0
able to generate positive and negative voltage levels at the − (V 1 + V 3 )
0 0 1 1 0 0 0 1 " 0 0 0
output. In this Table, 1 and 0 indicate the turned on and off
states of switches, respectively. As obvious from this Table, the
basic unit is able to generate 4 m − 1 levels at the output. # # # # # # # # # # # # #
Moreover, in order to generate all voltage levels at the output V 1 +V 1 0 0 0 0 1 0 0 " 0 0 1
m
except the zero level, only three power switches in different
− (V 1 + V )
operating modes are turned on. In the proposed basic unit, the m
0 0 1 1 0 0 0 0 " 0 0 1
number of power switches (N switch,unit ) , IGBTs (N IGBT,unit ) ,
driver circuits (N driver,unit ) , dc voltage sources (N source,unit ) , As an example, considering (6) and Table I for generation of 11-
maximum output voltage (V o,max,unit ) and generated output level, the proposed basic unit needs three dc voltage source (m=3)
with the values of V 1 , 2V 1 and 4V 1 as shown in Fig. 2(a). The
voltage levels (N level,unit ) are calculated as follows,
typical 11-level output voltage is shown in Fig. 2(b).
respectively:
­ 2(m + 1), for m = 1, 2 vo
N switch ,unit = ® (1)
¯ m + 5, for m > 2 +
5V 1
S1 4V 1
S2 S3
­ 4m, for m = 1, 2 3V 1
N IGBT,unit =® (2) 2V 1
¯ m + 7, for m > 2 V1 2V 1 S V1
7
wt
­ 2(m + 1), for m = 1, 2 vo 0 π 2π
N driver,unit =® (3) −V 1
¯ m + 5, for m > 2 4V1 S8 −2V 1
−3V 1
N source,unit = m (4) S4 S5 S6
−4V 1
− −5V 1
V o ,max,unit =V 1 +V m = (2m − 1)V dc (5)
(a) (b)
N level ,unit = 4m − 1 (6) Fig. 2. (a) 11-level basic unit based on the proposed basic unit; (b) typical
output voltage of the 11-level inverter.
In above equations, m is the number of used dc voltage
sources in the basic unit. III. PROPOSED CASCADED MULTILEVEL INVERTER

+ It is possible to use series connection of n numbers of the


S1 S2 S3
proposed basic unit to create a new cascaded multilevel
inverter Fig. 3 shows the proposed cascaded multilevel
V1 V2 S7
inverter. For this topology, the number of power switches
(N switch ) , IGBTs (N IGBT ) , driver circuits (N driver ) and dc
V3 S
8
voltage sources (N source ) are calculated as follows,
vo
respectively:
Vm−1 S
m+ 4

­2(m1 + m2 + " + mn ) + 2n, for m = 1, 2


N switch = ® (7)
Vm S
m+ 5
¯m1 + m2 + " + mn + 5n, for m > 2
S4 S5 S6 ­4(m1 + m2 + " + mn ) , for m = 1, 2
− N IGBT = ® (8)
Fig. 1. The proposed basic unit. ¯m1 + m2 + " + mn + 7 n , for m > 2

186
­2(m1 + m2 + " + mn ) + 2n, for m = 1, 2 In the proposed inverter, the number of generated output levels
N driver = ® (9) is completely depended on the magnitudes of dc voltage
¯m1 + m2 + " + mn + 5n, for m > 2
sources. At the following, a new algorithm to determine the
n
magnitudes of dc voltage sources is proposed.
N source = ¦ mi = m1 + m2 + " + mn (10)
i =1
For the first basic unit, the values of dc voltage sources are
considered as follows:
In order to generate the maximum number of output levels for a
fixed number of components, it is necessary to consider the V1 = Vdc (18)
equal number of dc voltage sources in each basic unit. In other
word: V i ,1 = 2 (i − 1)V 1,1 i = 2,3,! , m 1 (19)

m1 = m 2 = " = m n = m (11) For the second basic unit, the values of dc voltage sources are
determined as follows:
The different output voltage levels can be determined by
combination of switching states of basic units. If proper values V1,2 = Vdc + 2 (Vo ,max1 ) = (4 m1 − 1) Vdc (20)
for the dc voltage sources are selected, then the output voltage
n
of the inverter can be obtained between ¦ (V 1, j + V m, j ) and V i ,2 = 2 (i − 1) V 1,2 i = 2,3,! , m 2 (21)
j =1

n
−¦ (V 1, j + V m, j ) . The values of the dc voltage sources in the third basic unit are
j =1
assumed as following:
Considering (11), the equations (7) to (10) can be rewritten as
follows: V1,3 = Vdc + 2 (Vo,max1 + Vo ,max 2 ) = (4 m1 − 1)(4 m 2 − 1) Vdc (22)

­ 2n(m + 1), for m = 1, 2


N switch = ® (12) Vi ,3 = 2 (i − 1) V1,3 i = 2, 3,! , m3 (23)
¯ n( m + 5) , for m > 2
­4nm, for m = 1, 2 The k − th basic unit has dc voltage sources with the
N IGBT = ® (13)
¯n ( m + 7) , for m > 2 following values:
­2n(m + 1), for m = 1, 2
N driver = ® (14) V 1, j =V dc + 2 (V o ,max1 +V o ,max 2 + " +V o ,max(j−1) )
¯n(m + 5) , for m > 2
n −1 (24)
= ∏ (4 m j − 1) V dc
N sourse = nm (15) j =1

N variety = nm (16) V i , j = 2 (i − 1)V 1, j i = 2,3,! , m j (25)

n According to this algorithm, the number of generated output


V o ,max = ¦ (V 1, j + V m, j ) (17) levels (N level ) and maximum amplitude of output voltage
j =1
source are (V o ,max ) obtained as follows:
vo
+

n
V o ,max = ¦ (2 m j − 1) V 1, j (26)
j =1
S1,1 S 2,1 S3,1 S1,2 S2,2 S3,2 S1,n S2,n S3,n
N level = (4m1 − 1) × (4m 2 − 1) ×" × (4m n − 1)
n
V1,1 V2,1 S V1,2 V2,2 S V1,n V2,n S (27)
= ∏ (4m j − 1)
7,1 7,2 7,n

V3,1 S V3,2 S V3,n S j =1


8,1 8,2 8,n

It is also possible to propose other algorithms to determine the


S( m1 +4),1 S( m2 +4),2 S( mn + 4),n
magnitudes of dc voltage sources.
Vm1 −1,1 Vm2 −1,2 Vmn −1,n

S( m1 +5),1 S( m2 +5),2 S( mn +5),n IV. COMPARISON RESULTS


Vm1 ,1 Vm2 ,2 Vmn ,n

S 4,1 S5,1 S6,1 S4,2 S5,2 S6,2 S4,n S5,n S6,n Recently, some new topologies with reduced number of
switches have been presented for multilevel inverters. In this
First Unit Second Unit n th Unit section, the proposed cascaded multilevel inverter is compared
Fig. 3. The proposed cascaded multilevel inverter.

187
with several conventional cascaded multilevel inverters. This V1 +
Sb,1,1
comparison is done from different points of view such as the S1 v T1 T3
number of IGBTs, power switches and dc voltage sources. In Sa,1,1 Sc,1,1 o,1
V1
this comparison, the proposed cascaded multilevel inverter − i load
based on new proposed algorithm is indicated by P1 . The CHB
vo + −
multilevel inverter with binary algorithm is indicated by R1 . v load
( R1 for V 1 = 2 j −1V dc ( j = 1, 2," , n ) ) [5]. The presented Vn
+
Sb ,1,n
cascaded multilevel inverter in [19] is considered by R 2 . ( R 2 T4 T2
Sn v o,n
j −1 Sa,1,n S
for V j = ( m + 1) Vdc j = 1, 2, " , n ). In addition, for the Vn c ,1,n

presented inverter in [13], [20] and [21] three different (a) (b)
algorithms have been considered that are indicated by R 3 , R 4
and R 5 , respectively, as follows:

vo S1′
V1,1
R 3 for V j = (m j −1 ) Vdc ( j = 1, 2, " , n) V1,1
+ S2′ +
S1,1 − vo′ +
j −1
R4 for V1, j = 0.5V2, j = V3, j = 2 Vdc ( j = 1, 2, " , n) V2,1 S4,1 S5,1
vo,1
S1 S1 Uint 1
S 2,1

R 5 for V 1,1 =V 1,2 = V dc , V 1,3 = 2V 1,1 = 2V dc , V1 S


V3,1
S3,1
Vn
2 S2 −
i−4 T1 T3
V1,i = 2 × 5 Vdc ( i = 4," , m) , ! , V1,2
+
V1 Vn S1,2

V n ,1 =V n ,2 =V dc × (5 × 2m − 2 − 1) n −1 , S m −1 S m −1 Uint 2
V2,2
S2,2
S4,2 S5,2
vo,2 vo
+ vL −

V3,2 iL
V n ,3 = 2V dc × (5 × 2m − 2 − 1)n −1 , ! , V1 S m Vn Sm
S3,2

T2 T4
Vn ,i = Vdc (2i − 4 × 5)(5 × 2m − 2 − 1)n −1 ( i = 4,! , m) ) V1,n
+

S1, n
V2, n S4, n S5, n
Uint n vo, n
Fig.4 shows all of the above-mentioned topologies. Fig. 5 (a) S2, n
V3, n
compares the number of IGBTs of the proposed topology with S3,n
− −
the above-mentioned cascaded multilevel inverters. As it is (c) (d)
obvious from this figure, the proposed cascaded inverter needs
lower number of IGBTs than other presented inverters in the
references except the presented inverter by R5 . It is pointed out
that the bidirectional and unidirectional power switches are ′
S 1,2 ′
S 1,3 ′
S 1,4 ′
S 1,5
io
used in the proposed cascaded inverter. As mentioned before, V 1,1 ′ T 1,1 T 1,2
S 1,2 S 1,3 S 1,4 S 1,5
the number of IGBTs is as same as the number of power +
v o1
diodes. As a result, the proposed inverter also needs minimum V 1,2 V 1,3 V 1,4 V 1,5 −

T 1,1 ′
T 1,2
number of power diodes than other conventional cascaded S 1,1
vo
inverters. The number of power switches in the proposed ′
S 2,2 ′
S 2,3 ′
S 2,4 ′
S 2,5
cascaded inverter is compared with above-mentioned inverters. V 2,1 S 2,2 S 2,3 S 2,4 S 2,5 T 21 T 22
This comparison is shown in Fig. 5(b). As it is obvious from +
vo2
this figure, the proposed multilevel inverter needs lower V 2,2 V 2,3 V 2,5

T 21 ′

T 22
number of power switches in comparison with other presented S 2,1

multilevel inverters in literature. As it is mentioned previously,


all unidirectional and bidirectional power switches require a S n′ ,2 S n′ ,3 S n′ ,4 S n′ , m1
driver circuit. Therefore, the proposed inverter also needs lower V n ,1 S S n,3 S n ,4 S n ,5
T n ,1 T n ,2
n ,2
number of driver circuit than other inverters. Fig. 4(c) +
v on

compares the number of dc voltage sources in the proposed V n ,2 V n ,3 V n ,4 V n ,5 T n′ ,1
T n′ ,2
topology with the above-mentioned cascaded multilevel S n ,1

inverters. It is obvious that the proposed topology requires (e)


lower number of dc voltage sources than other mentioned Fig. 4. Conventional cascaded multilevel inverters; (a) CHB multilevel
topologies. It is clear from above comparisons that the inverter [5] ( R1 ); (b) presented topology in [19] ( R 2 ); (c) presented topology
proposed cascaded inverter is able to generate higher number
in [13] ( R 3 ); (d) presented topology in [20] ( R 4 ); (e) presented topology in
of output levels with lower number of power switches, IGBTs,
diodes, driver circuits and dc voltage sources than above [21] ( R 5 ).
mentioned topologies.

188
30
R2,R3
voltage of the inverter which is shown in Fig. 7 (c). As this
R4 R5 P1
25
R1
figure shows, the inverter can generate all of the expected
20
voltage levels. Fig. 7(d) shows the output current waveform.
N IGB T Regarding the waveforms of output current and voltage, there
15
is a phase displacement between them. This is resulted from the
10 inductive characteristic of the load.
5
vo
0 +


0 20 40 N level 60 80 100
(a)
S1,1 S2,1 S3,1

25 R3
R 4 R1 R4 V1,1 V2,1 S
P1 7,1 v o1
20 R5 S1,2 S2,2
vo2
15 V3,1 S8,1 V1,2
N switch S5,1 S6,1 S3,2
S4,1 S4,2
10

5 Fig. 6. The proposed 33-level inverter.

0 100 Vo1 [V]


0 20 40 N level 60 80
50
(b)
25
0
4

14 R4 R2,R3 R5
-25
0
R1 P1 -50
108
N source6 0.0000 0.0100 0.0200 0.0300 0.0400
64 (a)

20 Vo2 [V]
110
0
0 20 40 N level 60 80 100 55
(c) 0
Fig. 5. (a) variation of N IGBT versus N level ; (b) variation N switch of -55
versus N level ; (c) variation N source of versus N level . -110

0.0000 0.0100 0.0200 0.0300 0.0400


V. SIMULATION RESULTS (b)

In this section, the ability of the proposed inverter to generate Vo [V]


160
all voltage levels is reconfirmed by using simulation results on
80
a 33-level single phase inverter. The simulation results are
0
obtained by using PSCA/EMTDC software program. There are
-80
various control methods for controlling the multilevel inverters. -160
In this paper, the fundamental frequency control method is
used. According to Fig. 6 two basic units are cascaded to 0.0000 0.0100 0.0200 0.0300 0.0400
generate 33 levels. The proposed cascaded multilevel inverter (c)
has four unequal dc voltage sources. Based on the proposed
Io [A]
algorithm, the values of dc voltage sources are V 1,1 =V dc , 2.0

V2 ,1 = 2Vdc , V3,1 = 4Vdc , and V1,2 = 11 Vdc . The value of dc 1.0


0.0
voltage source V dc is assumed of 10V . Considering these
-1.0
values, the peak value of output voltage will be 160V . In the
-2.0
simulation, the frequency of the output voltage is assumed
50Hz . and the load is considered R–L with the value of 0.0000 0.0100 0.0200 0.0300 0.0400
R = 107Ω and L = 55 mH . (d)
Fig. 7. Simulation results ; (a) output voltage of the first basic unit; (b)
Figs. 7(a), 7(b) shows the output voltage of the first basic unit output voltage of the second basic unit; (c) output voltage; (d) output current.
and the second basic unit, respectively. The sum of the output
voltages of the first and the second basic units is the output

189
VI. CONCLUSION [9] F. Carnielutti, H. Pinheiro, and C. Rech, “Generalized carrier based
modulation strategy for cascaded multilevel converters operating under
fault conditions,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 679-
In this paper, a new asymmetric basic unit was proposed for 689, Feb. 2012.
cascaded multilevel inverters. The proposed multilevel inverter [10] E. Babaei, M. Farhadi Kangarlu, and M. Sabahi, “Extended multilevel
based on the basic unit is connected in series. Moreover, a new converters: An attempt to reduce the number of independent dc voltage
sources in cascaded multilevel converters,” IET Power Electron., vol. 7,
algorithm is proposed to determine the magnitude of dc voltage no. 1, pp. 157-166, Jan. 2014.
sources. The proposed cascaded multilevel inverter uses lower [11] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. Perez, “Survey on
number of power electronic switches, IGBTs, power diode, cascaded multilevel inverters,” IEEE Trans. Ind. Electron., vol. 3 no.
driver circuit and dc voltage sources for a same number of 57, pp. 2197–2206, 2010.
[12] M. Farhadi Kangarlu and E. Babaei, “A generalized cascaded multilevel
voltage levels in comparison with the conventional multilevel inverter using series connection of sub-multilevel inverters,” IEEE
inverters. The simulation results obtained from a 33-level Trans. Power Electron., vol. 28, no. 2, pp. 625-636, Feb. 2013.
inverter are presented to verify the correctness operation of the [13] E. Babaei, “A cascade multilevel converter topology with reduced
proposed topology. number of switches,” IEEE Trans. Power Electron., vol. 23, no. 6,
pp.2657–2664, 2008.
[14] E. Babaei, S.H. Hosseini, G.B. Gharehpetian, M. Tarafdar Haque, and
REFERENCES M. Sabahi, “Reduction of dc voltage sources and switches in
asymmetrical multilevel converters using a novel topology,” Electric
[1] J. Rodriguez, B. Wu, S. Bernet, J. Pontt, and S. Kouro, “Multilevel Power Syst. Res., vol. 77, no.8, pp. 1073–1085, 2007.
voltage source converter topologies for industrial medium voltage [15] W.K. Choi and F.S. Kang, “H-bridge based multilevel inverter using
drives,” IEEE Trans. Ind. Electron., vol. 54, pp. 2930-2945, Dec. 2007. PWM switching functions,” Proc. INTELEC, 2009, pp. 1–5.
[2] M.N.A. Kadir, S. Mekhilef, and H. W. Ping, “Voltage vector control of [16] A. Lesnicar and R. Marquardt, “An innovative modular multilevel
a hybrid three-stage eighteen-level inverter by vector decomposition, ” converter topology suitable for a wide power range,” in proc. IEEE
IET Trans. Power Electron., vol. 3, no. 4, pp. 601–611, Jul. 2010. Power Tech. Conf., 2003.
[3] M. Farhadi Kangarlu and E. Babaei, “A generalized cascaded multilevel [17] G.P. Adam, O. Anaya-Lara, G.M. Burt, D. Telford, B.W. Williams, and
inverter using series connection of sub-multilevel inverters,” IEEE J. R. McDonald, “Modular multilevel inverter: pulse width modulation
Trans. Power Electron., vol. 28, no. 2, pp. 625-636, Feb. 2013. and capacitor balancing technique,” IET Power Electron., vol. 3, no. 5,
[4] M.A. Eltawil and Z. Zhao, “Grid-connected photovoltaic power pp. 702–715, 2010.
systems: Technical and potential problems—A review,” Renewable and [18] Y. Hinago and H. Koizumi, “A single phase multilevel inverter using
Sustainable Energy Reviews, vol. 14, no. 1, pp. 112-129, Jan 2010. switched series/parallel dc voltage sources,” IEEE Trans. Ind. Electron.,
[5] M. Manjrekar and T.A. Lipo, “A hybrid multilevel inverter topology for vol. 58, no. 8, pp. 2643–2650, Aug. 2010.
drive application,” in Proc. APEC, 1998, pp. 523-529 [19] E. Babaei , S. Sheermohammadzadeh Gowgani, and M. Sabahi,
[6] M.A. Hosseinzadeh, E. Babaei, and M. Sabahi, “Back-to-back stacked “Modified multilevel inverters using series and parallel connection of dc
multicell converter,” in Proc. PEDSTC, 2012, Tehran, Iran, PP. 410- voltage sources, ” Arabian Journal for Science and Engineering, Vol.
415. 39, no. 4, pp 3077-3094, April 2014.
[7] E. Babaei, M. Farhadi Kangarlu, and M.A. Hosseinzadeh, [20] E. Babaei, S. Laali, and Z. Bayat, “A single-phase cascaded multilevel
“Asymmetrical multilevel converter topology with reduced number of inverter based on a new basic unit with reduced number of power
components,” IET Power Electron., vol. 6, no. 6, pp. 1188–1196, Jan. switches,” IEEE Trans. Ind. Electron., vol. 62, no. 2, pp. 922-929, Feb.
2013. 2015
[8] A.L. Batschauer, S.A. Mussa, and M.L. Heldwein, “Three-phase hybrid [21] E. Babaei, A. Dehqan, and M. Sabahi. “A new topology for multilevel
multilevel inverter based on half-bridge modules,” IEEE Trans. Ind. inverter considering its optimal structures,” Electric Power Syst. Res.,
Electron., vol. 59, no. 2, pp. 668-678, Feb. 2012. vol. 103, no. 8, pp. 145–156, 2013.

190

Оценить