Required reading

•  P. Chu, RTL Hardware Design using VHDL

Lecture 3 Chapter 2, Overview of Hardware Description

Languages
Introduction to VHDL
Chapter 3, Basic Language Constructs of VHDL
for Synthesis

George Mason University 2

Recommended reading

•  Wikipedia – The Free On-line Encyclopedia

VHDL - http://en.wikipedia.org/wiki/VHDL
Verilog - http://en.wikipedia.org/wiki/Verilog
Accellera - http://en.wikipedia.org/wiki/Accellera

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ECE 448 – FPGA and ASIC Design with VHDL 7 ECE 448 – FPGA and ASIC Design with VHDL 8

VHDL

•  VHDL is a language for describing digital

hardware used by industry worldwide

Brief History of VHDL

• VHDL is an acronym for VHSIC (Very High
Speed Integrated Circuit) Hardware
Description Language

ECE 448 – FPGA and ASIC Design with VHDL 9 10

Genesis of VHDL A Brief History of VHDL

State of art circa 1980 •  June 1981: Woods Hole Workshop
•  Multiple design entry methods and •  July 1983: contract awarded to develop VHDL
hardware description languages in use •  Intermetrics
•  No or limited portability of designs •  IBM
between CAD tools from different vendors •  Texas Instruments
•  Objective: shortening the time from a •  August 1985: VHDL Version 7.2 released
design concept to implementation from •  December 1987:
18 months to 6 months VHDL became IEEE Standard 1076-1987 and in
1988 an ANSI standard

11 12

2
 Four versions of VHDL

•  Four versions of VHDL:

•  IEEE-1076 1987
•  IEEE-1076 1993  most commonly
supported by CAD tools
•  IEEE-1076 2000 (minor changes)
•  IEEE-1076 2002 (minor changes)
•  IEEE-1076 2008

13 ECE 448 – FPGA and ASIC Design with VHDL 14

Verilog
•  Simpler and syntactically different
•  C-like

•  Gateway Design Automation Co., 1985

Verilog •  Gateway acquired by Cadence in 1990
•  IEEE Standard 1364-1995
•  Early de facto standard for ASIC programming

•  Programming language interface to allow

connection to non-Verilog code

ECE 448 – FPGA and ASIC Design with VHDL 15 16

VHDL vs. Verilog How to learn Verilog by yourself ?

Government Commercially
Developed Developed
Ada based C based

Strongly Type Cast Mildly Type Cast

Case-insensitive Case-sensitive

Difficult to learn Easier to Learn

More Powerful Less Powerful

17 18

3
 How to learn Verilog by yourself ? Features of VHDL and Verilog

•  Technology/vendor independent

•  Portable

•  Reusable

19 20

Naming and Labeling (1)

•  VHDL is case insensitive

Example:
Names or labels
databus
VHDL Fundamentals Databus
DataBus
DATABUS
are all equivalent

ECE 448 – FPGA and ASIC Design with VHDL 21 22

Naming and Labeling (2) Valid or invalid?

General rules of thumb (according to VHDL-87) 7segment_display
A87372477424
1.  All names should start with an alphabet character (a-z
or A-Z) Adder/Subtractor
2.  Use only alphabet characters (a-z or A-Z) digits (0-9) /reset
and underscore (_)
And_or_gate
3.  Do not use any punctuation or reserved characters
within a name (!, ?, ., &, +, -, etc.) AND__OR__NOT
4.  Do not use two or more consecutive underscore Kogge-Stone-Adder
characters (__) within a name (e.g., Sel__A is invalid)
Ripple&Carry_Adder
5.  All names and labels in a given entity and architecture
must be unique My adder

23 24

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 Free Format Readability standards & coding style
•  VHDL is a “free format” language Adopt readability standards based on one of the
No formatting conventions, such as spacing or the two main textbooks:
indentation imposed by VHDL compilers. Space Chu or Brown/Vranesic
and carriage return treated the same way.
Example: Use coding style recommended in
if (a=b) then
or
OpenCores Coding Guidelines
if (a=b) then linked from the course web page
or
if (a = Strictly enforced by the lab instructors and myself.
b) then
Penalty points may be enforced for not following
are all equivalent
these recommendations!!!
25 26

Comments Comments
•  Comments in VHDL are indicated with •  Explain Function of Module to Other
a “double dash”, i.e., “--” Designers
  Comment indicator can be placed anywhere in the
line •  Explanatory, Not Just Restatement of Code
  Any text that follows in the same line is treated as •  Locate Close to Code Described
a comment
  Carriage return terminates a comment •  Put near executable code, not just in a header
  No method for commenting a block extending over
a couple of lines
Examples:
-- main subcircuit
Data_in <= Data_bus; -- reading data from the input FIFO

27 28

Example: NAND Gate

a a b z
Design Entity b
z
0 0 1
0 1 1
1 0 1
1 1 0

ECE 448 – FPGA and ASIC Design with VHDL 29 30

5
Example VHDL Code Design Entity
•  3 sections to a piece of VHDL code
•  File extension for a VHDL file is .vhd design entity
•  Name of the file should be the same as the entity name
(nand_gate.vhd) [OpenCores Coding Guidelines]
entity declaration Design Entity - most basic
LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY DECLARATION
building block of a design.
ENTITY nand_gate IS
PORT(
architecture 1
a : IN STD_LOGIC; One entity can have many
ENTITY DECLARATION
b : IN STD_LOGIC; different architectures.
z : OUT STD_LOGIC);
END nand_gate;
architecture 2

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
ARCHITECTURE BODY architecture 3
END model;

31 32

Entity Declaration Entity declaration – simplified syntax

•  Entity Declaration describes the interface of

the component, i.e. input and output ports.
ENTITY entity_name IS
PORT (
Entity name Port type
Port names port_name : port_mode signal_type;
Semicolon

ENTITY nand_gate IS
port_name : port_mode signal_type;
PORT( ………….
a : IN STD_LOGIC;
No Semicolon
b : IN STD_LOGIC;
after last port
port_name : port_mode signal_type);
z : OUT STD_LOGIC
); END entity_name;
END nand_gate;

Reserved words Port modes (data flow directions)

33 34

Port Mode IN Port Mode OUT

Entity
Port signal Entity
Port signal

a
z

Output cannot be read within

c the entity
Driver resides
outside the entity
Driver resides
inside the entity c <= z

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Port Mode OUT (with extra signal) Port Mode BUFFER
Entity

Port signal
Entity

Port signal
z
x z
c
Port signal Z can be
Signal x can be read inside the entity
c
read inside the entity
Driver resides
c <= z
inside the entity
Driver resides z <= x Not recommended by OpenCores Coding Guidelines.
inside the entity
c <= x Port of mode buffer can not be connected to other types of ports
so buffer mode will propagate throughout the entire hierarchical design.
Problems reported with synthesis of designs using these ports.
37 38

Port Mode INOUT Port Modes - Summary

The Port Mode of the interface describes the direction in which data travels with
respect to the component
Port signal Entity

•  In: Data comes into this port and can only be read within the entity. It can
appear only on the right side of a signal or variable assignment.

a
•  Out: The value of an output port can only be updated within the entity. It
cannot be read. It can only appear on the left side of a signal
assignment.
Signal can be
read inside the entity •  Inout: The value of a bi-directional port can be read and updated within
the entity model. It can appear on both sides of a signal assignment.

Driver may reside •  Buffer: Used for a signal that is an output from an entity. The value of the
both inside and outside signal can be used inside the entity, which means that in an assignment
of the entity statement the signal can appear on the left and right sides of the <=
operator. Not recommended to be used in the synthesizable code.

39 40

Architecture (Architecture body) Architecture – simplified syntax

•  Describes an implementation of a design

entity
ARCHITECTURE architecture_name OF entity_name IS
•  Architecture example:
[ declarations ]
BEGIN
code
ARCHITECTURE model OF nand_gate IS
BEGIN END architecture_name;
z <= a NAND b;
END model;

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7
 Tips & Hints
Entity Declaration & Architecture
nand_gate.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all; Place each entity in a different file.
ENTITY nand_gate IS
PORT( The name of each file should be exactly the same
a : IN STD_LOGIC;
b : IN STD_LOGIC; as the name of an entity it contains.
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE dataflow OF nand_gate IS

BEGIN
z <= a NAND b; These rules are not enforced by all tools
END dataflow; but are worth following in order to increase
readability and portability of your designs

43 44

Tips & Hints

Place the declaration of each port,

signal, constant, and variable
in a separate line
Libraries

These rules are not enforced by all tools

but are worth following in order to increase
readability and portability of your designs

45 ECE 448 – FPGA and ASIC Design with VHDL 46

Library Declarations Library declarations - syntax

LIBRARY ieee;
USE ieee.std_logic_1164.all;
Library declaration
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC; LIBRARY library_name;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
Use all definitions from the package USE library_name.package_name.package_parts;
END nand_gate; std_logic_1164

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

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 Fundamental parts of a library Libraries

LIBRARY •  ieee Need to be explicitly

Specifies multi-level logic system,
including STD_LOGIC, and declared
PACKAGE 1 PACKAGE 2
STD_LOGIC_VECTOR data types

TYPES TYPES •  std

CONSTANTS CONSTANTS Specifies pre-defined data types
FUNCTIONS FUNCTIONS (BIT, BOOLEAN, INTEGER, REAL,
SIGNED, UNSIGNED, etc.), arithmetic
PROCEDURES PROCEDURES Visible by default
operations, basic type conversion
COMPONENTS COMPONENTS functions, basic text i/o functions, etc.

•  work
Holds current designs after compilation
49 50

STD_LOGIC

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(

STD_LOGIC Demystified
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE dataflow OF nand_gate IS

BEGIN
z <= a NAND b;
END dataflow;

What is STD_LOGIC you ask?

ECE 448 – FPGA and ASIC Design with VHDL 51 52

BIT versus STD_LOGIC STD_LOGIC type demystified

•  BIT type can only have a value of ‘0’ or ‘1’ Value Meaning

‘U’ Uninitialized
•  STD_LOGIC can have nine values
‘X’ Forcing (Strong driven) Unknown
•  ’U’,’X’,‘0’,’1’,’Z’,’W’,’L’,’H’,’-’
‘0’ Forcing (Strong driven) 0
•  Useful mainly for simulation ‘1’ Forcing (Strong driven) 1

•  ‘0’,’1’, and ‘Z’ are synthesizable (your codes ‘Z’ High Impedance

should contain only these three values) ‘W’ Weak (Weakly driven) Unknown

Weak (Weakly driven) 0.

‘L’
Models a pull down.
Weak (Weakly driven) 1.
‘H’
Models a pull up.

‘-’ Don't Care

53 54

9
More on STD_LOGIC Meanings (1) More on STD_LOGIC Meanings (2)

‘1’
‘X’
Contention on the bus
X

‘0’

55 56

More on STD_LOGIC Meanings (3) More on STD_LOGIC Meanings (4)

VDD • Do not care.
• Can be assigned to outputs for the case of invalid
‘-’ inputs(may produce significant improvement in
VDD resource utilization after synthesis).
• Must be used with great caution.
For example in VHDL, the comparison
‘H’ ’1’ = ’-’
‘1’ gives FALSE.
‘0’
‘L’

57 58

Resolving logic levels STD_LOGIC Rules

U X 0 1 Z W L H - •  In ECE 545 use std_logic or std_logic_vector for

U U U U U U U U U U all entity input or output ports
X U X X X X X X X X •  Do not use integer, unsigned, signed, bit for
0 U X 0 X 0 0 0 0 X ports
1 U X X 1 1 1 1 1 X •  You can use them inside of architectures if
Z U X 0 1 Z W L H X desired
W U X 0 1 W W W W X •  You can use them in generics
L U X 0 1 L W L W X •  Instead use std_logic_vector and a conversion
H U X 0 1 H W W H X function inside of your architecture
- U X X X X X X X X
[Consistent with OpenCores Coding Guidelines]

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 Signals
SIGNAL a : STD_LOGIC;

a
1
wire
Modeling Wires and Buses
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

b
8 bus

ECE 448 – FPGA and ASIC Design with VHDL 61 62

Standard Logic Vectors Vectors and Concatenation

SIGNAL a: STD_LOGIC; SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(15 DOWNTO 0);
a <= ”0000”;
SIGNAL e: STD_LOGIC_VECTOR(8 DOWNTO 0);
b <= ”1111”;
………. c <= a & b; -- c = ”00001111”
a <= ‘1’;
b <= ”0000”; -- Binary base assumed by default d <= ‘0’ & ”0001111”; -- d <= ”00001111”
c <= B”0000”; -- Binary base explicitly specified
e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
d <= X”AF67”; -- Hexadecimal base
‘1’ & ‘1’;
e <= O”723”; -- Octal base -- e <= ”00001111”

63 64

Fixed Rotation in VHDL Fixed Shift in VHDL

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);

A(3) A(2) A(1) A(0) A(3) A(2) A(1) A(0)

A>>1
A<<<1

A(2) A(1) A(0) A(3) ‘0’ A(3) A(2) A(1)

ArotL <= AshiftR <=

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 VHDL Design Styles

VHDL Design
Styles
•  Testbenches

behavioral
dataflow structural
VHDL Design Styles (sequential)
Concurrent Components and Sequential statements
statements interconnects •  Registers
•  State machines
•  Decoders

Subset most suitable for synthesis

ECE 448 – FPGA and ASIC Design with VHDL 67 68

xor3 Example Entity xor3_gate

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY xor3_gate IS
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Result : OUT STD_LOGIC
);
end xor3_gate;

69 70

Dataflow Architecture (xor3_gate) Dataflow Description

•  Describes how data moves through the system and the various
ARCHITECTURE dataflow OF xor3_gate IS processing steps.
SIGNAL U1_OUT: STD_LOGIC; •  Dataflow uses series of concurrent statements to realize logic.
•  Dataflow is most useful style when series of Boolean equations
BEGIN can represent a logic  used to implement simple combinational
U1_OUT <= A XOR B; logic
•  Dataflow code also called “concurrent” code
Result <= U1_OUT XOR C; •  Concurrent statements are evaluated at the same time; thus, the
END dataflow; order of these statements doesn’t matter
•  This is not true for sequential/behavioral statements
This order…
U1_OUT U1_out <= A XOR B;
Result <= U1_out XOR C;
Is the same as this order…
Result <= U1_out XOR C;
U1_out <= A XOR B;

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Structural Architecture in VHDL 87 xor2
ARCHITECTURE structural OF xor3_gate IS xor2.vhd
SIGNAL U1_OUT: STD_LOGIC;
A
COMPONENT xor2 LIBRARY ieee;
B xor3_gate Result USE ieee.std_logic_1164.all;
PORT(
I1 : IN STD_LOGIC; C
I2 : IN STD_LOGIC; ENTITY xor2 IS
Y : OUT STD_LOGIC PORT(
); I1
U1_OUT I1 : IN STD_LOGIC;
END COMPONENT; Y I1 I2 : IN STD_LOGIC;
I2 Y
I2 Y : OUT STD_LOGIC);
BEGIN END xor2;
U1: xor2 PORT MAP (I1 => A,
I2 => B, ARCHITECTURE dataflow OF xor2 IS
Y => U1_OUT); BEGIN
PORT NAME Y <= I1 xor I2;
U2: xor2 PORT MAP (I1 => U1_OUT, END dataflow;
I2 => C,
LOCAL WIRE NAME
Y => Result);
END structural;

73 74

Structural Architecture in VHDL 93 Structural Description

•  Structural design is the simplest to understand.
A
ARCHITECTURE structural OF xor3_gate IS
SIGNAL U1_OUT: STD_LOGIC; B Result
This style is the closest to schematic capture and
xor3_gate
C utilizes simple building blocks to compose logic
BEGIN
U1: entity work.xor2(dataflow)
functions.
PORT MAP (I1 => A,
I2 => B,
I1
Y
U1_OUT
I1
•  Components are interconnected in a hierarchical
I2 Y
Y => U1_OUT); I2 manner.
U2: entity work.xor2(dataflow)
PORT MAP (I1 => U1_OUT,
•  Structural descriptions may connect simple gates
I2 => C,
PORT NAME
or complex, abstract components.
Y => Result);
END structural; •  Structural style is useful when expressing a
LOCAL WIRE NAME
design that is naturally composed of sub-blocks.

75 76

Behavioral Architecture (xor3 gate) Behavioral Description

ARCHITECTURE behavioral OF xor3 IS •  It accurately models what happens on the inputs
BEGIN and outputs of the black box (no matter what is
xor3_behave: PROCESS (A, B, C) inside and how it works).
BEGIN
•  This style uses PROCESS statements in VHDL.
IF ((A XOR B XOR C) = '1') THEN
Result <= '1';
ELSE
Result <= '0';
END IF;
END PROCESS xor3_behave;
END behavioral;

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?

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