Extraction and simulation of complex

silicon interposer structures with

measurement correlation

11/15/2012
Sooyong Kim
Area Technical Manager
1 © 2012 ANSYS, Inc. November 19, 2012 Apache Design,
Apache Design,a asubsidiary
subsidiary of
of ANSYS
 Project Background
• Interest in tool arose from experience supporting electrical power distribution in 3D
IBM interposer module
– Simple model (two pins) vs. entire interposer
– Difficulties in model extraction (Several tools)
– Large run times/capacity issues even for simple models
– No direct IR drop data across interposer
– No direct dynamic simulations
– Strategic tool for future 3D designs
• Redhawk from Apache team in Ansys for interposer/chip carrier electrical analysis &
3D modules
– IR drop (DC analysis/ EM analysis)
– Dynamic (Transient analysis)
– Power model extraction (SPICE parasitic model, CPM )
– Point to point resistance Check

Apache Design, a subsidiary of ANSYS

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2 © 2012 ANSYS, Inc. November 19, 2012
 Apache Power and Noise Platforms
PowerTheater / PowerArtist

RPM (RTL Power Model)

 Activity, cycle-to-cycle
 Block power

Totem RedHawk Sentinel

CMM (Custom Macro Model) CPM (Chip Power Model)
 Hierarchical model  Distributed RLC, current
 IP protection  Power, signal, EMI, thermal
3 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS
 Chip/Chip Carrier/Package Software
Tool A
Tool C

Tool B

• Apache software addresses entire module (Tool A)

• Packaging level software (Tool B)
• Chip level software (Tool C)

Apache Design, a subsidiary of ANSYS

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4 © 2012 ANSYS, Inc. November 19, 2012
 Initial Test Cases

• Hendrix (200mm) and Beyonce (300mm) silicon interposer test vehicles

• Same design – different cross section & TSVs
• Four identical quadrants for 4 chips

Apache Design, a subsidiary of ANSYS

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5 © 2012 ANSYS, Inc. November 19, 2012
 Beyonce Design (Top Right) & Pins For Measurements

1 2

5 4

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6 © 2012 ANSYS, Inc. November 19, 2012
 Beyonce DC resistance measurements*

tested net (ohm)

interposer position
E
1 2 3 4 5
D A 0.737 2.000 0.213 2.079 0.786
B 0.725 2.028 0.214 2.127 0.805
C 0.646 2.059 0.221 2.150 0.859
D 0.710 2.060 0.218 2.150 0.815
A E 0.673 2.083 0.227 2.183 0.830

Tool used Keithley 2700

Tool # 1076534
B cal date 2012-04-03
cal due 2013-04-03

C * From J. Audet

Tested interposer location

Apache Design, a subsidiary of ANSYS

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7 © 2012 ANSYS, Inc. November 19, 2012
 Redhawk to Measurements Comparison

Redhawk Measured Difference

(Ohms) (Ohms) (Ohms)
0.566 0.673 - 0.107

1.879 2.083 - 0.204

0.336 0.227 +0.109

1.976 2.183 - 0.207

0.884 0.830 +0.054

Apache Design, a subsidiary of ANSYS

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8 © 2012 ANSYS, Inc. November 19, 2012
 Redhawk Dynamic Simulations
PAD current at VDD

• No need for separate tool for static vs. dynamic

• Graph shows effect of having decaps vs no caps on interposer
• Die Power Model ( CPM ) created , open spice format

Apache Design, a subsidiary of ANSYS

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9 © 2012 ANSYS, Inc. November 19, 2012
 Pad voltage at VDD

10 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS
 Hendrix Small Test Case Details
• Results for dynamic simulation
• Name and size of gds/lef file: hendrix_vdd_grn.gds (28KBytes),
hendrix_3_18_09.def (8.3MBytes)
• Machine run: bucksport (Linux64) in IBM EFK
• Linux OS: Redhat v5.2
• Processor: AMD Opteron 252 - 2 2.6 GHz
• Total physical memory: 10G
• Run time used by Redhawk: 8 mins 0 secs.
• Memory used by Redhawk: 1.324 GBytes
• Diskspace used by Redhawk: 362 Mbytes
• Improvement in model size/run time vs. existing
8 mins vs. 1 week runtime

Apache Design, a subsidiary of ANSYS

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11 © 2012 ANSYS, Inc. November 19, 2012
 Hendrix/Beyonce Large Test Case Details
• Results for dynamic simulation
– (static simulation a bit smaller than this)
• Name and Size of gds file: hendrix_mike.gds (2.48M),
hendrix_3_18_09.def (3G)
• Machine run: ae256 Linux64 in Ansys CA
• Linux OS: Redhat v5.2
• Processor: AMD Opteron 6128HE 4 – 2.0GHz
• Total Physical memory: 256G
• Run time used by Redhawk: 45 hrs 42 mins 20 secs
• Memory used by Redhawk: 48.2G
• Diskspace used by Redhawk: 14G
Static DC/EM analysis
– Beyonce test case (a bit larger): 69G memory and 68
hrs run time Dynamic analysis
CPM ( Chip Power
• Tool can handle large data volumes but large run
times/memory requirements model generation ) in
one shot

Apache Design, a subsidiary of ANSYS

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12 © 2012 ANSYS, Inc. November 19, 2012
 Simplified User Experience
Multi-pane, Multi-canvas Based Power Analysis

13 13 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS
 Enabling 3D/2.5D Designs
 Shared P/G network and SSN in multiple designs
 Needs simultaneous multi-die simulation for shared noise
Concurrent analysis: Model based analysis:
(a) Full-layout visibility of all IC / interposer (a) Inclusion of CPM for some dies
(b) hierarchical capacity (b) Interposer modeling

14 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS
 Model Based CPS Convergence

R Metal L Metal R Pkg L PKG R PCB

Global PDN
Leaf Tx
VRM

view On die
Decap C Metal
C4 PG Bump
C Pkg
On Board
decap

SoC Designers Leaf Tx

R Metal L Metal PCB/Pkg RLC,
view S parameter
in RedHawk On die C4 PG Bump From Sentinel
Decap C Metal

PCB Designers R Pkg L PCB R PCB

CPM
VRM
view
C4 PG Bump
in Sentinel From RedHawk On Board
C Pkg
decap

Only Common reference point

15 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS
 What is CPM?

 Chip on-die Power Grid RLC

Apache  Transistor current/cap/ESR

 Open SPICE netlist format

Package/Board
 Multi-domain, distributed model Model

 DC to multi-GHz validity System ASIC

 Advanced chip excitation modes Houses Vendors
Chip Power
 Silicon correlated Model

Apache Ecosystem

16 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS
 What is CPM?

CHIP DATA

Layout Library
(Early to Sign-off)

CHIP ANALYSIS

Static Dynamic Dynamic

VCD VectorLess

Static (Iavg, R)
Chip Power Model
Modes Frequency domain (RLC)
Time-domain (I(t), RLC)

17 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS
 CPM Benefits Against Traditional Models
Traditional die model Traditional CPM™
Apache Die Model

RedHawk (SoC)
Chip Current

Layout Library

Chip Power Model

 RLC reduction: billions of

Chip Parasitics

parasitics to thousands of Spice

elements
 Distributed with full couplings
Single Lumped Model

18 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS
 Multi-die Analysis Framework

Memory Logic

Silicon
Interposer

19 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS
 Apache Design Inc. ( Subsidiary of Ansys )

www.apache-da.com
www.ansys.com

20 © 2012 ANSYS, Inc. November 19, 2012 Apache Design, a subsidiary of ANSYS