Chapter 5

APPLIED ELECTRONICS I (ECEG2111): CHAPTER 5: FIELD EFFECET TRANSISTORS (FETS) 01/01/2017
Chapter 5Field effect transistors (FETs)

What is FET?
FET is uni-polar device i.e. operation depends on only one type of charge carriers (h or
e) . It is a Voltage controlled Device (gate voltage controls drain current).
• The term field-effect relates to the depletion region formed in the channel of a
FET as a result of a voltage applied on one of its terminals (gate).
ADVANTAGES OF FET
1. Very high input impedance (109-1012 )
2. Source and drain are interchangeable
3. Low Voltage Low Current Operation is possible (Low-power consumption)
4. Less Noisy
5. No minority carrier storage (Turn off is faster)
6. Very small in size, occupies very small space in Ics
7. Low voltage low current operation is possible in MOSFETS
Current Controlled vs Voltage Controlled Devices
Types of Field Effect Transistors

(The Classification)
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ADU, CET, Department of Electrical and Computer Engineering compiled by Tsegay A.&Hadush
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Types of Field Effect Transistors

Device are controlled by base current and not by base voltage. However, in a field
effect transistor
(FET), the output characteristics are controlled by input voltage (i.e., electric field) and
not by input
Current. This is probably the biggest difference between BJT and FET. There are two
basic types of
Field effect transistors:
(i) Junction field effect transistor (JFET)
(ii) Metal oxide semiconductor field effect transistor (MOSFET)
MOSFET is also called the insulated-gate FET or IGFET.
 Quite small
 Simple manufacturing process
 Low power consumption
 Widely used in VLSI circuits(>800 million on a single IC chip)
To begin with, we shall study about JFET and then improved form of JFET, namely;
MOSFET.
Junction Field Effect Transistor (JFET)
A junction field effect transistor is a three terminal semiconductor device in which
current conduction is by one type of carrier i.e., electrons or holes. The JFET was
developed about the same time as the transistor but it came into general use onlyin the
late 1960s. In a JFET, the current conduction is either by electrons or holes and is
controlled by
means of an electric field between the gate electrode and the conducting channel of the
device. The
JFET has high input impedance and low noise level.
• The JFET ( junction field-effect transistor) is a type of FET that operates with
a reverse-biased pnjunction to control current in a channel.
• The JFET is always operated with the gate-source pn junction reverse-biased.
Reverse biasing
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of the gate-source junction with a negative gate voltage produces a depletion region
along the pnjunction, which extends into the n channel and thus increases its resistance
by restricting the channel width.
Constructional details. A JFET consists of a p-type or n-type silicon bar containing
two pn Junctions at the sides as shown in Fig.5.1. The bar forms the conducting
channel for the charge Carriers. If the bar is of n-type, it is called n-channel JFET as
shown in Fig. 5.1 (i) and if the bar is Of p-type, it is called a p-channel JFET as shown
in Fig. 5.2 (ii). The two pn junctions forming Diodes are connected *internally and a
common terminal called gate is taken out. Other terminals are Source and drain taken
out from the bar as shown. Thus a JFET has essentially three terminals with,
gate(G), source (S) and drain (D).
• There are two types of JFET’s: n-channel and p-channel

• The n-channel is more widely used.
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Fig 5.1
JFET polarities. Fig. 5.2 (i) shows n-channel JFET polarities whereas Fig. 5.2 (ii)
shows the p-channel JFET polarities. Note that in each case, the voltage between the
gate and source is such that the gate is reverse biased. This is the normal way of JFET
connection. The drain and source terminals are interchangeable i.e., either end can be
used as source and the other end as drain.
The following points may be noted:

(i) The input circuit (i.e. gate to source) of a JFET is reverse biased. This means that
the device has high input impedance.
(ii) The drain is so biased w.r.t. source that drain current ID flows from the source to
drain.
(iii) In all JFETs, source current IS is equal to the drain current i.e. IS = ID.
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Shows the circuit of n-channel JFET with normal polarities. Note that the gate is
reverse Biased.
Principle and Working of JFET
Principle. The two pnjunctions at the sides form two depletion layers. The current
conduction by Charge carriers (i.e. free electrons in this case) is through the channel
between the two depletion layers and out of the drain. The width and hence *resistance
of this channel can be controlled by changing the input voltage VGS. The greater the
reverse voltage VGS, the wider will be the depletion layers and narrower will be the
conducting channel. The narrower channel means greater resistance and hence source
to drain current decreases. Reverse will happen should VGS decrease. Thus JFET
operates on the principle that width and hence resistance of the conducting channel
can be varied by changing the reverse voltage VGS. In other words, the magnitude of
drain current (ID) can be changed by altering VGS.
Working. The working of JFET is as under :
(i) When a voltage VDS is applied between drain and source terminals and voltage on
the gate is zero [ See Fig. 5.3 (i) ], the two pnjunctions at the sides of the bar establish
depletion layers. The electrons will flow from source to drain through a channel
between the depletion layers. The size of these layers determines the width of the
channel and hence the current conduction through the bar.
(ii) When a reverse voltage VGSis applied between the gate and source [See Fig. 5.3
(ii)], the width of the depletion layers is increased. This reduces the width of
conducting channel, thereby increasing the resistance of n-type bar. Consequently, the
current from source to drain is decreased.
On the other hand, if the reverse voltage on the gate is decreased, the width of the
depletion layers also decreases. This increases the width of the conducting channel and
hence source to drain current.
Fig 5.3
Schematic Symbol of JFET
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Characteristics of FET
The curve between drain current (ID) and drain-source voltage (VDS ) of a JFET at
constant gate source voltage (VGS) is known as output characteristics of JFET. Fig.
5.4 shows the circuit for determining the output characteristics of JFET. Keeping VGS
fixed at some value, say 1V, the drain source voltage is changed in steps.
Corresponding to each value of VDS, the drain current ID is noted. A plot of these
values gives the output characteristic of JFET at VGS = 1V. Repeating similar
procedure, output characteristics at other gate-source voltages can be drawn. Fig. 5.4
shows a family of output characteristics.
Fig 5.5
The following points may be noted from the characteristics:

(i) At first, the drain current ID rises rapidly with drain-source voltage VDS but then
becomes constant. The drain-source voltage above which drain current becomes
constant is known as pinch off voltage. Thus in Fig. 5.4, OA is the pinch off voltage
VP.
(ii) After pinch off voltage, the channel width becomes so narrow that depletion layers
almost
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touch each other. The drain current passes through the small passage between these
layers. Therefore, increase in drain current is very small with VDS above pinch off
voltage. Consequently, drain current remains constant.
Transfer Characteristics
•The input-output transfer characteristic of the JFET is not as straight forward

as it is for the BJT
• In a JFET, the relationship (Shockley’s Equation) between VGS (input voltage)
and ID (output current) is used to define the transfer characteristics, and a little
more complicated (and not linear):
2
 V GS 
I =I
D DSS  1 - 
 V P 
• As a result, FET’s are often referred to a square law devices
• JFET Transfer Curve
This graph shows the value of ID for a given value of VGS
Important Terms
In the analysis of a JFET circuit, the following important terms are often used :
1. Shorted-gate drain current (IDSS)
2. Pinch off voltage (VP)
3. Gate-source cut off voltage [VGS (off)]
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1. Shorted-gate drain current (IDSS). It is the drain current with source short-
circuited to gate (i.e. VGS = 0) and drain voltage (VDS) equal to pinch off voltage. It
is sometimes called zero-bias current.
The following points may be noted carefully:
(i) Since IDSS is measured under shorted gate conditions, it is the maximum drain
current that you can get with normal operation of JFET.
(ii) There is a maximum drain voltage [VDS (max)] that can be applied to a JFET. If
the drain voltage exceeds VDS (max), JFET would breakdown.
2. Pinch off Voltage (VP). It is the minimum drain-source voltage at which the drain
current Essentially becomes constant.
3. Gate-source cut off voltage VGS (off). It is the gate-source voltage where the
channel is completely cut off and the drain current becomes zero.
Example 19.2. A JFET has the following parameters: IDSS = 32 mA; VGS (off) = –
8V; VGS
= – 4.5 V. Find the value of drain current.
Biasing of FET circuits

Biasing circuit. The biasing circuit uses supply voltage VDD to provide the necessary
bias.
Two most commonly used methods are (i) self-bias (ii) potential divider method. We
shall discuss each method in turn.
Fixed bias circuit

The simplest of biasing arrangements for the n-channel JFET
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Example 10.13. Find VDS and VGS in Fig. 19.21, given that ID = 5 mA.
Solution.
VS = ID*RS = (5 mA) (470 Ω) = 2.35 V
AndVD = VDD – ID RD
= 15V – (5 mA) × (1 kΩ) = 10V
∴VDS = VD – VS = 10V – 2.35 V = 7.65V
Since there is no gate current, there will be no voltage drop across RG
andVG = 0.
Now VGS = VG – VS = 0 – 2.35V = – 2.35 V
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Self-bias circuit
The self-bias configuration eliminates the need for two dc supplies.
• The controlling gate-to-source voltage is now determined by the voltage across
a resistor RS introduced n the source leg of the configuration.
• The d.c. component of drain current flowing through RS produces the desired
bias voltage.
Voltage across RS, VS = ID RS
Since gate current is negligibly small, the gate terminal is at d.c. ground i.e., VG = 0.
∴VGS= VG–
VS= 0 −ID RS
orVGS= −*ID RS Thus bias voltage VGS keeps gate negative w.r.t. source.
Fig 5.6
Potential Divider bias circuit (Voltage-Divider Bias)

• The voltage-divider bias arrangement applied to BJT transistor amplifiers is
also applied to FET amplifiers
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Zi= R1 || R2
Example: Determine ID and VGS for the JFET with voltage-divider bias in Fig. given
below, given that VD = 7V
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Excersice Determine the following for the network
Small Signal model of FET

The drain-current expressions for the JFET and MOSFET can be written in essentially
identical form. So that the small-signal models also have the same form.
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FET AC Equivalent Circuit
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Common source JFET amplifier
The
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Summary
Metal Oxide Semiconductor FET (MOSFET)

The main drawback of JFET is that its gate must be reverse biased for proper operation
of the device i.e. it can only have negative gate operation for n-channel and positive
gate operation for p-channel. This means that we can only decrease the width of the
channel (i.e. decrease the *conductivity of the channel) from its zero-bias size. This
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type of operation is referred to as **depletion-mode operation Therefore, a JFET can

only be operated in the depletion-mode. However, there is a field effect transistor
(FET) that can be operated to enhance (or increase) the width of the channel (with
consequent Increase in conductivity of the channel) i.e. it can have enhancement-mode
operation. Such a FET is CalledMOSFET.
Types of MOSFETs
There are two basic types of MOSFETs viz.
1. Depletion-type MOSFET or D-MOSFET. The D-MOSFET can be operated in both
the depletion-Mode and the enhancement-mode. For this reason, a D-MOSFET is
sometimes called Depletion/enhancement MOSFET.
2. Enhancement-type MOSFET or E-MOSFET. The E-MOSFET can be operated only
in enhancement-Mode.
1. Depletion –type MOSFET.

the constructional details of n-channel D-MOSFET. It is similar to n-channel
JFET except with the following modifications/remarks.
(i) The n-channel D-MOSFET is a piece of n-type material with a p-type region (called
substrate) on the right and an insulated gate. The free electrons (Q it is n-channel)
flowing from source to drain must pass through the narrow channel between the gate
and the p-type region (i.e. substrate).
(ii) Note carefully the gate construction of D-MOSFET. A thin layer of metal oxide
(usually silicon dioxide, SiO2) is deposited over a small portion of the channel. A
metallic gate is deposited over the oxide layer. As SiO2 is an insulator, therefore, gate
is insulated from the channel.
Note that the arrangement forms a capacitor. One plate of this capacitor is the gate and
the other plate is the channel with SiO2 as the dielectric. Recall that we have a gate
diode in a JFET.
(iii) It is a usual practice to connect the substrate to the source (S) internally so that a
MOSFET
has three terminals vizsource (S), gate (G) and drain (D).
(iv) Since the gate is insulated from the channel, we can apply either negative or
positive voltage to the gate. Therefore, D-MOSFET can be operated in both depletion-
mode and enhancement-mode.
However, JFET can be operated only in depletion-mode.
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Symbol for n-channel D-MOSFET
Symbol for p-channel D-MOSFET
Circuit Operation of D-MOSFET

we can apply either negative or positive voltage to the gate. The negative-gate
operation is called depletion mode whereas positive-gate operation is known as
enhancement mode.
(i) Depletion mode. Since gate is negative, it means electrons are on the gate .these
electrons
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*repel the free electrons in the n-channel, leaving a layer of positive ions in a part of
the channel. In other words, we have depleted (i.e. emptied) the n-channel of some of
its free electrons. Therefore, lesser number of free electrons are made available for
current conduction through the n-channel. This is the same thing as if the resistance of
the channel is increased. The greater the negative voltage on the gate, the lesser is the
current from source to drain. Thus by changing the negative voltage on the gate, we
can vary the resistance of the n-channel and hence the current from source to drain.
Note that with negative voltage to the gate, the action of D-MOSFET is similar to
JFET.
(ii) Enhancement mode. Since the gate is positive, it induces negative charges in the
n-channel These negative charges are the free electrons drawn into the channel.
Because these free electrons are added to those already in the channel, the total number
of free electrons in the channel is increased. Thus a positive gate voltage enhances or
increases the conductivity of the channel. The greater the positive voltage on the gate,
greater the conduction from source to drain.
D-MOSFET Transfer Characteristic
i) The point on the curve where VGS = 0, ID = IDSS. It is expected because IDSS is the value of IDwhen gate
and source terminals are shorted i.e. VGS = 0.
(ii) As VGS goes negative, ID decreases below the value of IDSS till ID reaches zero when VGS = VGS (off) just
as with JFET.
(iii) When VGS is positive, ID increases above the value of IDSS. The maximum allowable value of ID is
given on the data sheet of D-MOSFET.
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E-MOSFET
Two things are worth noting about E-MOSFET. First, E-MOSFET operates only in the
enhancement
mode and has no depletion mode. Secondly, the E-MOSFET has no physical channel
from source to drain because the substrate extends completely to the SiO2 layer.
It is only by the application of VGS (gate-to-source voltage) of proper magnitude and
polarity that the device starts Conducting. The minimum value of VGS of proper
polarity that turns on the E-MOSFET is called
Threshold voltage [VGS (th)]. The n-channel device requires positive VGS (ú VGS (th))
and the p-channel device requires negative VGS (ú VGS (th)).
Operation.
(i) When VGS = 0Vthere is no channel connecting the source and drain. Thep
substrate has only a few thermally produced free electrons (minority
carriers) so that drain currentis essentially zero. For this reason, E-MOSFET
is normally OFF when VGS = 0 V. Note that thisbehaviour of E-MOSFET
is quite different from JFET or D-MOSFET
ii.)When gate is made positive (i.e. VGS is positive) as shown in Fig. 19.55 (ii), it
attracts free electrons into thp region. The free electrons combine with the holes next to
the SiO2 layer. If VGS is positive enough, all the holes touching the SiO2 layer are
filled and free electrons begin to flow from the source to drain. The effect is the same
as creating a thin layer of n-type material (i.e. inducing a thin n-channel) adjacent to
the SiO2 layer. Thus the E-MOSFET is turned ON and drain current ID starts flowing
form the source to the drain.
The minimum value of VGS that turns the E-MOSFET ON is called threshold voltage
[VGS (th)].
(iii) When VGS is less than VGS (th), there is no induced channel and the drain current
ID is zero.
When VGS is equal to VGS (th), the E-MOSFET is turned ON and the induced channel
conducts drain current from the source to the drain. Beyond VGS (th), if the value of
VGS is increased, the newly formed channel becomes wider, causing ID to increase. If
the value of VGS decreases [not less than VGS (th)], the channel becomes narrower and
ID will decrease. This fact is revealed by the trans conductance curve of n-channel E-
MOSFET shown in Fig below. As you can see, ID = 0 when VGS = 0. Therefore, the
value of IDSS for the E-MOSFET is zero. Note also that there is no drain current until
VGS reaches VGS (th).
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Fig.
(i)
Shows the schematic symbols for n-channel E-MOSFET
Whereas (ii) shows the schematic symbol for p-channel E-MOSFET.
Example The data sheet for an E-MOSFET gives ID(on) = 500 mA at VGS = 10V and
VGS (th) = 1V. Determine the drain current for VGS = 5V.
Common source FET amplifier

Frequency response of common source FET amplifier
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Frequency response of common source FET amplifier
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APPLIED ELECTRONICS I (ECEG2111): CHAPTER 5: FIELD EFFECET TRANSISTORS (FETS) 01/01/2017

Chapter 5Field effect transistors (FETs)

Types of Field Effect Transistors

Types of Field Effect Transistors

• There are two types of JFET’s: n-channel and p-channel

The following points may be noted:

The following points may be noted from the characteristics:

•The input-output transfer characteristic of the JFET is not as straight forward

Biasing of FET circuits

Fixed bias circuit

Potential Divider bias circuit (Voltage-Divider Bias)

Excersice Determine the following for the network

Small Signal model of FET

FET AC Equivalent Circuit

Common source JFET amplifier

Metal Oxide Semiconductor FET (MOSFET)

type of operation is referred to as **depletion-mode operation Therefore, a JFET can

1. Depletion –type MOSFET.

Symbol for n-channel D-MOSFET

Symbol for p-channel D-MOSFET

Circuit Operation of D-MOSFET

Common source FET amplifier

Frequency response of common source FET amplifier

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