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7.

ADC Layout
國立成功大學電機工程學系
張順志 soon@mail.ncku.edu.tw

回章節大綱

編撰者:張順志
Outline
• 1. Introduction
• 2. Specifications of A/D converter
• 3. Circuit design and simulations
• 4. The implement of pipelined ADC layout
• 5. Measurement setup and consideration
• 6. Conclusion
• 7. Reference

編撰者:張順志
7-2
What is A/D Converter?

ADC Output

VIN
× 2 N = CODE + RESIDUE
VREF
N

0 <= RESIDUE < 1

編撰者:張順志
7-3
w1
Why A/D Converter?
• Why digital signal processing?
– Accuracy considerations.
– Signal stored considerations.
– Cost considerations.
So, using ADC can convert signal from analog to
digital, then increasing the system performance!!

編撰者:張順志
7-4
投影片 4
w1 用數位信號來做儲存會比類比來的好,因此一收到類比信號都希望快速轉成數位信來處理.
winhong6, 2003/10/29
Summary of ADC in System
• NTSC/PAL Decoder 8Bits,14-17MHz
• HDTV 8-10Bits,50-75MHz
• CATV Channel Modems 8-12Bits,10-15MHz
• ADSL/HDSL Transceivers 12-16Bits,3MHz
• CDDI Transceivers, VG 8-10Bits,30-60MHz
• Mag Storage Read Channel 6-8Bits,75-150MHz
• High Performance Imager 12Bits,75MHz
• Scanner 10-16Bits,6-40MHz
• LCD Monitor 8Bits,150MHz
• APS CMOS Sensor 8-12Bits,20MHz
編撰者:張順志
7-5
Applications of ADC

Bit number

20
Digital
Audio
18

16 High
Speed
14 Modems

12

10
Video
Voice Application
8
Process
Wireless
6 Communication

Sampling Rate (Hz)


1k 10k 100k 10M 100M

編撰者:張順志
7-6
Outline
• 1. Introduction
• 2. Specifications of A/D converter
• 3. Circuit design and simulations
• 4. The implement of pipelined ADC layout
• 5. Measurement setup and consideration
• 6. Conclusion
• 7. Reference

編撰者:張順志
7-7
Specifications
• Resolution and LSB
• Input range
• Sample rate, Conversion time and Latency
• Offset error, Gain error, Differential nonlinearity
Error (DNL), Integral nonlinearity Error (INL)
• Signal-to-noise ratio (SNR)
• Effective resolution bandwidth
• Jitter issues

編撰者:張順志
7-8
w22 Resolution and LSB
Resolution: The number of distinct analog levels
corresponding to the different digital
words. (How small analog signal can
be digitized )

LSB: Least Significant Bit.

VMAX = VRT - VRB


VMAX
LSB = N
VRT: Higher Reference Voltage
2 VRB: Lower Reference Voltage

編撰者:張順志
7-9
投影片 9
w22 Resolution:多小的類比訊號還可被轉換出來.
winhong6, 2003/10/30
w3 Input Range
Input Range:
The Max. Input swing range, usually
associate with the reference voltage.
For example:
VRT (Higher Reference Voltage)=2.3v
VRB (Lower Reference Voltage)=1.0v
Then the input range is 1.0v~2.3v.
Input Capacitance:
The load of Input signal. The value of
the capacitance dependent on the ADC
structure and design, the load will affect
the ADC bandwidth.
編撰者:張順志
7 - 10
投影片 10
w3 輸入電容越大,則ADC頻寬下降.
winhong6, 2003/10/29
Sample Rate,
Conversion Time and Latency

Sample Rate: ADC sample data rate.


Unit: Hz.
Conversion Time: Convert data time from sample to data out.
Unit: Sec.
Latency: Clock cycle from sample edge to data out edge.
7 - 11 Unit: clock cycle. 編撰者:張順志
Offset Error and Gain Error

EOT( Top offset )


∆V1 ∆V
EOT = × 100% Unit : % or EOT = ∆V1 Gain Error = × 100 % Unit : %
VREF VREF
Unit: mv or
EOB( Bottom Offset )
Gain Error = ∆V Unit : mv
∆V2
EOB = × 100% Unit : % or EOB = ∆V2
VREF Gain Error is the same with EOT!
Unit: mv
編撰者:張順志
7 - 12
DNL and INL (1/2)
¾ Differential nonlinearity (DNL) :
This parameter measures how far each of the step
sizes deviates from the nominal value of the step
size.

¾ Integral nonlinearity (INL) :


This parameter is the difference between the actual
transfer characteristic and the straight line
characteristic which the ADC is intended to
approximate.

編撰者:張順志
7 - 13
w2 DNL and INL (2/2)

INL

∆ V(i) ∆V (i ) / 1LSB
DNL(i) = −1
1LSB
DNL
i = 2 N −1
INL(i) = ∑ DNL(i)
i =0
INL
DNL >= 1 =>Missing code!!
編撰者:張順志
7 - 14
投影片 14
w2 (1)DNL=>是在看Missing code問題.
INL=>是在看線性之情形問題.
(2)INL是將DNL做累加.
winhong6, 2003/10/29
SNR ( Signal to Noise Ratio)
• SNR:
Import a Sine wave to ADC and make ADC output code to
FFT transform. The ratio of main frequency amplitude to the
RMS of the other frequency amplitude is the SNR of ADC.

⎧ ⎫
⎪ ⎪
⎪ AM ⎪
SNR = 20 log ⎨ ⎬dB
N 2
⎪ ( ) ⎪
⎪ ∑i iA 2
i ≠ M ⎪
⎩ ⎭

AM: Main frequency amplitude.


Ai : Include noise and harmonic distortion.
SNDR: Signal to Noise and Distortion Ratio.
編撰者:張順志
7 - 15
w4 Quantization Error
1/ 2
⎡1 T /2 2 ⎤
VQ ( rms ) = ⎢ ∫ VQ dt ⎥
⎣ T −T / 2 ⎦
−t
VQ = V LSB
T
V
⇒ VQ ( rms ) = LSB
12
1/ 2
⎡ 1 2π 2 ⎤
V IN ( rms ) = ⎢ ∫ (1 / 2V REF ∗ Sin ω t ) dωt ⎥
⎣ 2π 0 ⎦
V
V IN ( rms ) = REF
8
⎡ V REF ⎤
⎡ V ( rms ) ⎤ ⎢ ⎥
IN 8
SNR = 20 log ⎢ ⎥ = 20 log ⎢ ⎥
⎢⎣ Q
V ( rms ) ⎥⎦ ⎢ V LSB ⎥
⎢ 12 ⎥
⎣ ⎦
= 20 log ⎡ (3 / 2) ∗ 2 N ⎤
⎢⎣ ⎥⎦
= 6.02 N + 1.76 dB
SNR = 6.02N + 1.76dB
編撰者:張順志
7 - 16
投影片 16
w4 經ADC後得SNR,透過SNR的公式,即可求出最終實際BIT數.
winhong6, 2003/10/29
w5 Effective Resolution Bandwidth

編撰者:張順志
7 - 17
投影片 17
w5 fin頻率越高,則SNDR會逐漸下降.
winhong6, 2003/10/29
w6 Jitter Issues
• Sampling time uncertainly (jitter) in SHA may
introduce the noise or distortion.

∆V
∆t

編撰者:張順志
7 - 18
投影片 18
w6 理想要抓的點與實際要抓的點不一致時,即發生Jitter Issues.
winhong6, 2003/10/29
SNR Due to Jitter

SNR
Timing uncertainty reflects in
Amplitude uncertainly
130dB

dVs (t )
120dB
Vn ≈ ∆ t ⋅ = ∆ t ⋅ As 2π f cos(2π ft )
dt
110dB
where
100dB
Jitter =0.1ps
Is the timing jitter
Vs =Assin(2πft)
∆t
90dB
Jitter =1ps
80dB Vn = ∆ t ⋅ As 2π f
70dB Jitter =10ps 2
As
SNR = 20 log 2 = −20 ⋅ log(2π f ∆t )
60dB
Vn

1MHz 10MHz 100MHz


Input Signal Frequency
⇒ The SNR of ADC is limited by
jitter.
編撰者:張順志
7 - 19
Outline
• 1. Introduction
• 2. Specifications of A/D converter
• 3. Circuit design and simulations
• 4. The implement of pipelined ADC layout
• 5. Measurement setup and consideration
• 6. Conclusion
• 7. Reference

編撰者:張順志
7 - 20
System Specifications
• Resolution: 10 bits
• Sampling Frequency (fs) : 50MS/s
• DNL < 0.5 LSB, INL < 0.5 LSB
• Voltage supply (VDD): 1.8V
• Technology: TSMC 0.18um (1.8V) 1p6m CMOS
MIM capacitor, poly resistor

編撰者:張順志
7 - 21
Building Blocks
• The typical pipelined ADC contains:
– Sample and hold circuit
– Multiplying DAC (MDAC) circuit
• Sample and hold
• DAC
• Substractor
• Gain amplifier
– Sub-ADC circuit
– Synchronization circuit
– Digital error correction circuit
編撰者:張順志
7 - 22
Pipelined ADC Topology
N bits digital output
Digital
Digital error
error correction
correction

Synchronization
Synchronization Circuit
Circuit
B1 bits B2 bits B3 bits Bn bits
input
S/H Stage1 Stage2 Stage3 Final Stage
(Stage p)

subtractor
Residue_in +
Σ Av=2B-1 S/H Residue out
-

Sub
DAC
ADC

MDAC
B bit

編撰者:張順志
7 - 23
Pipelined ADC Operation (1/4)
• A generic pipelined ADC consists of N cascaded stages,
each resolving B bits.
• Within each stage, the analog input is first sampled and held.
Then it is coarsely quantized by a sub-ADC to resolve B bits.
• Then using a DAC, the quantized value is subtracted from
original input signal to yield the quantization error.
• The quantization error is then amplified to the half-scale range
by an amplifier of gain 2B-1.The resulting residue signal is then
applied to the next pipelined stage for further quantization on
the next clock cycle.
• The function of the D/A, the subtraction, S/H, and the
amplification of the reminder are combined into one single
circuit called the multiplying DAC (MDAC)

編撰者:張順志
7 - 24
Pipelined ADC Operation (2/4)
• Due to the sample-and-hold nature of the pipeline, each stage
works concurrently to achieve high throughput.
• All digital codes produced by each stages are processed
through synchronization and digital error correction circuits.
Then the fully resolved N bits of resolution per sample
experiences a delay P/2 clock cycles from the sampling
instant to full quantization.
• The digital error correction circuit is used to correct error
introduced by comparator offset.

編撰者:張順志
7 - 25
w8 Pipelined ADC Operation (3/4)
Stage 1 2 3 4 5 6

Period1 D1
z High Throughput Rate
⇒ 1 period and 1 data
Period2 D2 D1

Period3 D3 D2 D1 z Latency = N
⇒ N depend on pipeline stage
Period4 D4 D3 D2 D1

Period5 D5 D4 D3 D2 D1

Period6 D6 D5 D4 D3 D2 D1 Read D1

Period7 D7 D6 D5 D4 D3 D2 Read D2

Period8 D8 D7 D6 D5 D4 D3 Read D3

編撰者:張順志
7 - 26
投影片 26
w8 若有6級,則資料輸出要等待6個Latency.
........N....................................N.................
winhong6, 2003/10/29
Pipelined ADC Operation (4/4)

編撰者:張順志
7 - 27
Pipelined ADC Timing Issue

編撰者:張順志
7 - 28
Per-Stage Resolution Consideration
• 1.5-bits/Stage
– High speed potential Larger feedback factor
– Higher latency Much more stages
– Smaller Cap. Array Need smaller inter-stage gain
– Large Opamp size Much more stages

• N-bits/Stage (N > 1.5)


– High resolution potential
– Lower Latency
– Higher scale down ratio Reduced resolution requirement
of later stages
– Large Cap. array
– Lower power consumption For higher than 10bits resolution
編撰者:張順志
7 - 29
Sample-and-Hold (S/H)
• The S/H relaxes the timing requirements of the first
stage by holding the instantaneous value of the analog
input
• The S/H circuit is typically implemented by closed loop,
switched-capacitor topology which need high gain,
wideband operational amplifier.
• As the supply voltage is scaled down, the performance
of the switch (Ron) is decayed seriously so that distorts
the S/H signal. The clock bootstrapped circuit must be
used to the critical switches of the S/H.
• Bottom plate sampling
– Reduce the charge injection induced by switch
• Correlated Double Sampling
– Reduce offset of OP amp

編撰者:張順志
7 - 30
w35 S/H Error and its Solution

Error Sources Possible Solution/Techniques


Finite Bandwidth Low Vth process or Large W/L
switch to reduce RON.
Gate voltage bootstrapping.
Charge Injection Bottom plate sampling.
Dummy switch or Use fully
differential.
Clock Feedthrough Dummy switch or Use fully
differential.
編撰者:張順志
7 - 31
投影片 31
w35 S/H我們使用Bootstrapping來改善
Finite Bandwidth,用Pseudo-differential
structure改善Charge Injection and Clock
Feedthrough.
winhong6, 2003/10/29
Finite Bandwidth

¾Increase Switch Size.


¾Boost Gate Control Voltage (at Low supply design).
編撰者:張順志
7 - 32
w31 Charge-Injection
¾When the device turns off, this charge leaves the channel
through the source and drain terminals, introducing an error
voltage on the sampling capacitor. This error appears as an
offset if QCH is constant, a gain error if QCH is linearly
proportional to the input signal, or a nonlinear term if QCH has
nonlinear dependence on the input signal.
¾IF half of QCH is injected onto CH.
QCH = WLCox(VGS-Vth)

WLCox (VGS − Vth )


∆V =
2C H
編撰者:張順志
7 - 33
投影片 33
w31 當一個MOS開關從導通至開路時,由於導通時通道間反轉產生的電荷需要被排除,因而導致了電荷注入的效應,這時候一部份的電流入CH,使產
生電壓誤差,此效應稱Charge-Injection.
winhong6, 2003/10/30
w30 Clock Feedthrough
¾Another source of error in MOS switches is clock feedthrough
, caused by the finite overlap capacitance between the gate
and source or drain terminals.
¾When the gate control voltage VCK changes state to turn off
the switch, Cov conducts the transition and changes the
voltage stored on CH by an amount equal to

WC OV
∆ V = VCK
WC OV + C H

COV :Overlap Capacitance


per unit width.
編撰者:張順志
7 - 34
投影片 34
w30 時脈訊號VCK會經由雜散電容Cgs、Cgd影響接點Vin,Vout的電壓值.如此的效應稱為Clock Feedthrough.
winhong6, 2003/10/30
S/H Circuit and its Operations (1/2)
¾ The diagram is the single-end version for simplicity
¾ The φ1a clock phase is used to the bottom plate sampling technique
¾ The correlated double sampling (CDS) technique
¾ Feedback factor =1 => high speed application
Sample phase
¾ φ1, φ1a => high
¾ sample input signal
φ2 Vin
_ ¾ store the offset of
Cs Vout OPamp
+
Vos

φ1a
Vin φ1
_
Hold phase
Cs Vout
+ ¾ φ2 => high
Cs
¾ hold input signal
Vin
_ ¾ Vout(nt)=Vin((n-1/2)t)
+ Vout ¾ cancel the offset of
OPamp

編撰者:張順志
7 - 35
S/H Circuit and its Operations (2/2)
¾ The full differential version of S/H circuit
clk2

clk1
clk1a
cs1
vip

_ Out+
+
+ _
Clock boostrapping Out-

cs2
vin

clk1a
clk1

clk2
編撰者:張順志
7 - 36
MOS Switch (1/2)
¾An MOS transistor can be used as an analog switch, with its
gate voltage controlling the resistance between its source and
drain. For a square-law NMOS device that operates in linear
(triode) region, this resistance can be expressed as

1
RON =
µnC ox (Wn Ln )(V gs −V th)

where µn is the electron mobility in the channel, Cox is the


gate oxide capacitance per unit area, W and L are effective
width and length of the device, respective Vgs is the gate-
source voltage, and Vtn is threshold voltage.

編撰者:張順志
7 - 37
w32 MOS Switch (2/2)
¾ In high-speed low-voltage Designs
VDD gds NMOS PMOS

Vi
Vtp Vtn VDD On-resistance:
Vi V0 gds
z Limitation tracking speed
and settling time.
Vtn VDD
Vi
z Have a nonlinear voltage
gds
dependence.
gds
Vi V0
Vi
Vtn VDD

編撰者:張順志
7 - 38
投影片 38
w32 使用了三種不同的Vdd分別為Vdd大於Vtp+Vtn、Vdd接近Vtp+Vtn及Vdd小於Vtp+Vtn當輸入電壓Vi增加,NMOS導通電阻變大,gds下降,這時
PMOS還沒導通,當Vi增加至PMOS的Vtp值時,PMOS開始導通,Vi繼續增加到Vdd-Vtn,之後NMOS於不導通狀態,在Vtp<Vi<Vdd-Vtn 這段時間中導通
電阻是PMOS的Ron或NMOS的Ron的並聯值,電阻值大致維持水平,隨著Vdd的下降,使得中段gds下降,也就是並聯導通電阻大的上升,使開關更不
理想,當Vdd下降至小於Vtp+Vtn時,中間並聯的部分己經完全不導通。
winhong6, 2003/10/30
Operation of Bootstrapped
w33 Switch (1/2)

¾Two advantages:
zReliability is improved ,never exceeds VDD. (need
additional dummy transistors)
zOn-resistance almost constant, reduces the distortion.

編撰者:張順志
7 - 39
投影片 39
w33 針對上一頁當VDD電壓越來越小Ron導通上有困難,使用Bootstrapped 可改善.而此其Bootstrapped優點有二:
(1)可靠度增加.
(2)導通電組近似一常數.
winhong6, 2003/10/30
Operation of Bootstrapped
Switch (2/2)
¾ ‘Off’ phase ¾ ‘On’ phase
¾ The bootstrapped switch is turn off ¾ The bootstrapped switch is turn on
¾ The capacitor which acts as the ¾ The Vgs of the switch contains VDD
battery is charged to the supply contribute low and constant Ron
voltage

+
C C VDD
_

編撰者:張順志
7 - 40
Clock Bootstrap Circuit
M3 clk1b

M8
M7 M10

c1
M4
clk1

M13
M5
D
M9
clk1b S
M12
Bootstrapped Switch

編撰者:張順志
7 - 41
The Diagram of Each
Pipeline Stage
¾ The 1.5bits resolution per stage is chosen for high speed
consideration
¾ In the 1.5-bit/stgae architecture, the accuracy requirements on the
sub-ADCs are greatly reduced.
¾ Switched-capacitor implementation of the MDAC circuit is used
typically, which operates on a two phase clock.

S1
S2
Vi _
_ S3 + Vo
LATCH

+
+VR/4 MUX
_
+ +VR cm +VR
MDAC
-VR/4

SUB-ADC DAC 2X GAIN


編撰者:張順志
7 - 42
Multiplying DAC (MDAC) (1/4)
• The DAC output voltage (VR) is controlled by the sub-ADC output digital
code.
• The MDAC circuit included the S/H, gain amplifier, ADC, substractor
outputs residue signal to match up the operation of digital error correction .

φ2 φ1a
φ1
Cf
Vi
_

φ1 Cs + Vo
φ2

VR

編撰者:張順志
7 - 43
Multiplying DAC (MDAC) (2/4)
Sample phase
¾ Sample input signal on both capacitors
¾ Store the offset of opamp
_

Vi +
Vo
⇒ Q1 = (C f + Cs )(0 − Vi )
Vos

¾ Amplify the held input signal


Hold phase
¾ Subtract the amplified signal with VR
¾ Cancel the offset of opamp
_
⇒ Q2 = Cs (0 − VR ) + C f (0 − Vo )
+
Vo
VR Vos

Cs + C f Cs
Q1 = Q2 ⇒ Vout = +D
Cf Cf

編撰者:張順志
7 - 44
Multiplying DAC (MDAC) (3/4)
• The residue output of MDAC for digital error correction

Vout

⎧ Cs
+Vref ⎪(1+ )Vi −Vref , if Vi > Vref / 4
+1/2Vref
⎪ Cf
⎪⎪ C
0 Vo = ⎨(1+ s )Vi , if −Vref / 4 ≤ Vi ≤ +Vref / 4
“00” “01” “10” ⎪ Cf
-1/2Vref ⎪ C
⎪(1+ s )Vi +Vref , if Vi < −Vref / 4
-Vref
⎪⎩ Cf
Vin
-Vref 0 +Vref

編撰者:張順志
7 - 45
Multiplying DAC (MDAC) (4/4)
• MDAC Circuit
Vinp

clk2
clk1 clk1a
clk1

x y z cs1 cf1

Out+
_ +
Ref- cm Ref+
+ _
Ref+ cm Ref-
Out-
x y z
cs2 cf2

clk1
clk1 clk1a
clk2

Vinn
編撰者:張順志
7 - 46
Sub-ADC in 1.5-Bit/Stage
• The configuration of sub-ADC and its digital encoder
• The sub-ADC in 1.5bit/stage output only 3 code because of
digital error correction.
Dummy phi2

MSB
In+ +
+ + x
_ _
Ref-
_ LSB xb
In- LSB

+ zb
+ +
_ y
_
_
yb

編撰者:張順志
7 - 47
Sub-ADC in Final Stage
• The output digital code is four full digital codes

In+ +
Ref+ + +
_ _
Ref-
In- _ LSB

+
+ +
_ _
cm
_

+
+ +
_ _
_

MSB
編撰者:張順志
7 - 48
Resistive Divider
Dynamic Comparator (1/3)
• The sub-ADC in 1.5bit/stage can tolerate 250mV offset
because of error correction, so we can use dynamic
comparator as sub-ADC to reduce power consumption
and area.

M9 M10
M11 M12

latch
latch
O+
M7
M8 Out+
O-

M5 M6
Out-

Vref- M1 M2 M3 M4 Vref+
In+ In-

編撰者:張順志
7 - 49
Resistive Divider
Dynamic Comparator (2/3)
• Conductance (G1=1/R1 and G2=1/R2 ) of NMOS pairs
biased in triode region are given to the first order by

1 ⎡W W ⎤
G1 = = Kp ⎢ 1 .(Vin+ − Vth ) + 2 .(Vref − − Vth ) ⎥
R1 ⎣L L ⎦
1 ⎡W W ⎤
G2 = = Kp ⎢ 1 .(Vin− − Vth ) + 2 .(Vref + − Vth ) ⎥
R ⎣L L ⎦

• The input voltage which causes G1 equal to G2 is the


comparator threshold voltage

W2
Vin |threshold = ⋅ Vref
W1
where Vin = Vin+ − Vin− and Vref = Vref+ − Vref−

編撰者:張順志
7 - 50
Resistive Divider
Dynamic Comparator (3/3)
• The offset of the comparator depends on the mismatch of
transistors M1-M4 (assume all other transistor match
perfectly ).
• Any mismatch between the transistors M5 and M6 causes
large offset voltage.
• We need large size transistors to reduce offset (increasing
power).
• Mismatches in transistors M7-M12 are not so critical for the
offset voltage.
• The mismatch loading sensitivity the latch can be avoided
by adding an extra latch or inverter.

編撰者:張順志
7 - 51
Synchronization Circuit
• The synchronization circuit is implemented by static flip-
flops.
• This static flip-flops must be used with two phase non-
overlapped clocks.
clk2
clk1

In Out

clk1 clk2
clk2

Flip-Flop

編撰者:張順志
7 - 52
Implementation of Digital
Correction Circuit
• The digital error correction just need ‘add’ the overlapped
digital code, so we can use the simple ‘binary adder’ to
implement it.

ci i1 i2 d1 d2
i1 d1
0 0 0 0 0
No operation 0 0 1 0 1
0 1 0 1 0
i2
ci
1 0 0 0 1
Addition 1 0 1 1 0
d2 1 1 0 1 1

adder

編撰者:張順志
7 - 53
Digital Circuit for the
Error Correction

編撰者:張順志
7 - 54
Clock Generator
• The clock generator produces 10 clock phases included
the non-overlapped clocks, the clocks for comparator,
and its inverted clock.
clk1a

clk1

Clock_in

clk2a

clk2a

clk1 Com_clk1

編撰者:張順志
7 - 55
Clock Phases
• The inverted clock phases are not shown for simplicity.

clk1

clk1a

Clk2

Clk2a

Clk_com1

Clk_com2

編撰者:張順志
7 - 56
How to Choose the
Value of Capacitor (1/5)
• How to choose the value of capacitors in pipeline stage?
– Capacitor matching issue
– The error effect induced by switches
– Total noise consideration
• Because we can use some circuit techniques to reduce
the error effect induced by switches (bottom plate
sampling), total noise consideration dominate the lower
bound value of capacitor.
• The total noise includes two sources:
– KT/C noise
– OP amp noise

編撰者:張順志
7 - 57
How to Choose the
Value of Capacitor (2/5)
• KT/C noise calculation
– During the input sampling process, KT/C noise is sampled on
the capacitors along with the input signal
Sample phase

KT
Vn2 =
C s + C f + C opamp
+Qin-
Vi Cf
– Assuming Vin=0, the total noise _
charge is Cs + Vo
+Qin-

Qn2 = (C ⋅ V ) 2 = KT (C s + C F + C opamp ) VR

Where Copamp is the input capacitance of the op amp.

編撰者:張順志
7 - 58
How to Choose the
Value of Capacitor (3/5)
• The sampled signal and noise charge gets transferred to CF, and will
cause an output voltage of
Hold phase

Qn2 (C S + C F + C opamp ) KT 1
V 2
= 2 = KT ⋅ = ⋅
C F2
out
CF CF f
+2Qin-
Vi Cf
_
• Input referred noise power can be
Cs + Vo
found by dividing the output noise 0

power by the square of the gain:


2
KT ⋅ (C S + C F + C opamp )
VR
2
Vout KT 1 ⎛ C F ⎞
V = 2 =
2
⋅ ⋅⎜ ⎟ =
C f ⎝ CS + CF ⎠ (C S + C F ) 2
in
G

Where f is the feedback factor of amplifier

編撰者:張順志
7 - 59
How to Choose the
Value of Capacitor (4/5)
• The value of op amp noise is dependent on the op amp topology and
bias
• The noise source in this case is the thermal noise source from the
transistor for simplicity
2
in 2 = 4 K T ⋅ ( gm )
3

• Noise power at the output can be found by KCL, KVL analysis


Vo ro
H (s) = = i n2
sC LT ro
in
(1 + g m ⋅ ro ⋅ f ) ⋅ (1 + ) CF
1 + g m ⋅ ro ⋅ f Cs Copamp +
Vx gmVx CL
ro
∞ _
= ∫ | ( H ( s | j 2 π f )) | ⋅ in ⋅ df
2 2 2
V o 0

編撰者:張順志
7 - 60
How to Choose the
Value of Capacitor (5/5)
• The input referred noise variance can be obtained by dividing
the output noise power by the square of the gain
2
Vo2 2 1 1 ⎛ CF ⎞
σ = 2 = ⋅ KT ⋅ ⋅
2
⋅⎜ ⎟
G 3 f C LT ⎝ S
C + C F ⎠
where CLT = CL + f ⋅ (CS + Copamp ) , CL is the loading of later stage

• Assume KT/C noise and op amp noise are uncorrelated, we


can find the total input referred noise (fully differential version
must time “2” factor)
2
KT ⋅ (C S + C F + C opamp ) 2 1 1 ⎛ CF ⎞
σ 2
= 2 ⋅{ + ⋅ F ⋅ KT ⋅ ⋅ ⋅⎜ ⎟ }
(C S + C F ) 2 +
total
3 f C LT ⎝ S
C C F ⎠

Where F is noise factor dependent on different topology .

F=6 for two-stage or folded-cascode configuration


F=3 for telescopic-cascode opamps
編撰者:張順志
7 - 61
Example (1/2)
• For 10 bit resolution pipelined ADC
• The input referred noise of single stage
Assume Cs=CF=C, Copamp =(1/2)C, Cother=(1/3)C, F=6

165 KT KT KT
vni2 ,tot = ⋅ = 4.58 ⋅ ≈ 6⋅ Save some margin
36 C C C

• The converter’s total input-referred noise will be:

6 KT 6 KT 1 1 1 1 11KT
vni2 , ADC ≈ + (1 + 2 + 4 + 6 + 8 + ggg) ≈
2C C 2 2 2 2 C

S/H ALL Stage

編撰者:張順志
7 - 62
Example (2/2)
• Supposing total input-referred noise should be a fraction
of one LSB, e.g. 1/6 so that total noise don’t degrade the
SNDR of ADC too much.
2 1
VFS = 2volt , VLSB = 10
= 1953 × 10 −6
V , δ n = v 2
ni , ADC = LSB = 325 × 10 −6
V
2 6
11KT
= (325 × 10 −6 ) 2 ⇒ C = 0.4321 p ≈ 0.5 p
C
• So, we can choose the values of capacitors in MDAC and
S/H (Assume we don’t scale down in per stage design)

MDAC: 0.5p
S/H: 1p
編撰者:張順志
7 - 63
How to Specify the
Specifications of Opamp (1/4)
• The bandwidth and slew rate of op amp
– Derived from the sampling rate and resolution of ADC

• In the feedback system, the settling time includes:


– Linear settling time
– Nonlinear settling time (slew time )

• Time constant of the closed-loop amplifier, τ, for a step


input is
1 1
τ = =
ω −3 dB βω ta

• For the closed loop amplifier, the step response is


−t
Vout (t ) = Vstep (1 − e τ )
To be continued…
編撰者:張順志
7 - 64
How to Specify the
Specifications of Opamp (2/4)
−t
– eτ
: settling error

– If we want to implement 10 bit ADC, the settling error must be


controlled within 0.1%.
=> we can choose the bandwidth of op amp through this relationship.

• The slew rate is also the important factor about settling time
of closed loop amplifier
V
SR =
t

• For 10bit, 50Mhz pipelined ADC, the settling time equal 10ns.
Actually, the real settling time is smaller because of the rise
time, fall time, and non-overlap time of clock.
編撰者:張順志
7 - 65
How to Specify the
Specifications of Opamp (3/4)
• Example:
– 10bit, 50MHz pipelined ADC
– For 10bit accuracy, the settling must be less 0.1%

−t
e τ = 0.001 ⇒ t = 7τ
– Assume we allocate linear settling time equal 5n and slew
time equal 5n.
t > 7τ (in order to keep error<<0.001)
⇒ 1
τ= (β =
CF 1
≈ )
βωta CS + CF + Cop 2

⇒ 5n > 7 ⋅
1
βωta
⇒ fT =
7
1
5n ⋅ 2π
≈ 445MHz

V 1
SR = = = 200 V
t 5n µs
編撰者:張順志
7 - 66
How to Specify the
Specifications of Opamp (4/4)
• The gain of op amp
– Derived from the resolution requirement of ADC
– The finite gain error induce the distortion into pipelined
ADC

1
Gactual = G ( ) Finite gain error
1 + Af

– For 10 bits 1.5bit/stage, the first stage need 9 bits


accuracy with ‘1/2’ feedback factor. So, the gain of op
amp can be decided as 68dB for saving some safe
margin.

編撰者:張順志
7 - 67
The Specifications of Opamp
• The required specifications of op amp for 10 bit 50MHz
pipelined ADC are listed below:
DC gain 68dB

Unity gain bandwidth 445MHz

Slew Rate 200V/us

Supply voltage 1.8V

Output Swing (fully


2Vpp
differential)
TSMC 0.18um 1p6M
Technology
CMOS salicide process
編撰者:張順志
7 - 68
The Circuit of Opamp (1/2)
• Two stage configuration is adopted because of low
voltage consideration.
• The first stage is telescopic architecture for high gain
purpose, and the second stage is simple differential pair
for high swing.
• This op amp is full differential, so it need CMFB
(switched-capacitor type) to stable the output common
mode voltage.
• The lead frequency compensation (with miller capacitor
and resistor) is adopted to obtain sufficient phase margin.

編撰者:張順志
7 - 69
The Circuit of Opamp (2/2)

outp outn

lead compensation

Vip Vin

Telescopic Cascode Stage Differential pair Stage


編撰者:張順志
7 - 70
Wide Swing and
Constant Gm Bias Circuit
Vbias-p

Mb7 Mb11 Vcasc-p


Mb8
Mb14 Mb18

Mb9 Mb6 Mb10

M15 Mb16

Mb1 Mb4 Mb13

Mb5

Mb17

Mb2 Mb3 Mb12

Rb Vcasc-n

Vbias-n
Start-up circuit
編撰者:張順志
7 - 71
Common Mode Feedback Circuit
• This version of SC-CMFB can stable common mode
level during both two phases, so we can always use op
amp to process signal. (Amplify, Offset-cancellation)
• This circuit need more area than traditional SC-CMFB.

Φ1 Φ2 Φ1
Φ2 Out+

Vcmref Vcmref

C1 C2
Φ2 Φ1 Φ2 C1 Φ1

Vbias Vbias
vb

C1 C2 C1
Φ1 Φ2 Φ1

Vcmref Vcmref
Φ2 Out-

編撰者:張順志
7 - 72
Opamp Simulation (1/3)
• AC Simulation
– DC gain: 75dB
– Unity-gain bandwidth=462Mhz
– phase margin=680

編撰者:張順志
7 - 73
Opamp Simulation (2/3)
• DC Simulation (Output Swing Test)
– 1.4V Æ slope=1200 (V/V)
– 0.4V Æ slope=2420 (V/V)

編撰者:張順志
7 - 74
Opamp Simulation (3/3)
• Slew Rate Simulation
– Rising edge:214V/μs
– Falling edge: 261 V/μs

編撰者:張順志
7 - 75
Opamp Performance
¾ All Specifications of opamp is sufficient to the specifications
derived before.
DC Gain 75 dB
Unity-gain Bandwidth (fT) 462 MHz

Phase Margin 68°

Load 2.5pF

Slew Rate 214 V/µs 261 V/µs

Output Swing (Diff.) 2Vpp

Power Supply (VDD) 1.8 V

Power Consumption 4.3 mW

CMOS Process TSMC 0.18µm CMOS 1P6M


編撰者:張順志
7 - 76
Pipelined ADC Simulation (1/2)
• FFT Simulation
– Fin=1MHz
– Fs=50MHz
– 2048 points FFT
– SNDR=61.38dB
– ENOB=9.9Bit

編撰者:張順志
7 - 77
Pipelined ADC Simulation (2/2)
• INL/DNL Simulation
– Input: Ramp signal
– Code density=20samples / per code
– DNL=-0.2LSB~0.15LSB
– INL=-0.25LSB~0.25LSB

編撰者:張順志
7 - 78
ADC Performance
Specification Performance
Sampling Frequency 50 MS/s
Resolution 10 bit
Power Supply 1.8 V
Operation Range 0.4~1.4 V
SNDR 61.38 dB @ fin = 1MHz
ENOB 9.9 bit
INL -0.25~0.25 LSB
DNL -0.2~0.15 LSB
Die Area 1mm × 1mm
Power Consumption 50 mW
Process Technology TSMC 0.18µm CMOS 1P6M
編撰者:張順志
7 - 79
Outline
• 1. Introduction
• 2. Specifications of A/D converter
• 3. Circuit design and simulations
• 4. The implement of pipelined ADC layout
• 5. Measurement setup and consideration
• 6. Conclusion
• 7. Reference

編撰者:張順志
7 - 80
Contents of ADC Layout
• Noise Coupling Issues.
z Chip Floor plan Technique.
z Guard Ring Technique.
z Shield Technique.
z Power Issues.
• Device Matching Issues.
z Dummy Cell Technique.
z Capacitor Matching.
z Resistor Matching.
z Transistor Matching.

編撰者:張順志
7 - 81
Consideration of
ADC Chip Floor Plan
• Consideration1:The farer distance between analog and digital ckt,
the lower noise effect to analog from digital.
• Consideration2:The sensitive analog lines are as short as possible.
• Consideration3:Considering the cost, we must care the smallest chip
area floor plane.

編撰者:張順志
7 - 82
Guard Ring Technique (1/2)

¾Because twin-well process only ¾Using substrate contact or well


have one p-sub, the digital clock contact to decrease digital noise
noise would affect analog circuit affect.
through p-sub.

編撰者:張順志
7 - 83
Guard Ring Technique (2/2)

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7 - 84
Shielded Technique

編撰者:張順志
7 - 85
Capacitor or Resistor Shielded

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7 - 86
Matching Guidelines
¾The components to be matched should have
z The same type.
z The same shape.
z Non minimum size.
z The same orientation.
z Closer to each other.
z Common centroid.
z The same contact, interconnections.
z Affect in the same way.
z The same temperature.
z The same bias.
編撰者:張順志
7 - 87
Dummy Cell Technique
• Dummy cell:
In order to make the layout to be the same type
and shape, and decrease the mismatch.

編撰者:張順志
7 - 88
Capacitor Matching
¾Capacitor un-match source:
z Edge effect in process.
z Gradient error of oxide thickness.
z Parasitic cap. Component between top and
bottom plate.
z Line parasitic cap. Component made by the
connection to other element.
The first, second and third reason can be ignored using
unit capacitors and common centroid layout scheme. By
the way, the line parasitic component is gradually a dominant
effect of the capacitors mismatch as the size of elements is
decreased with process evolution.
編撰者:張順志
7 - 89
Capacitors Array Layout Scheme

Common Centroid:
Having better element matching,
but the connect line will introduce
some different parasitic capacitor.

編撰者:張順志
7 - 90
Common-Centroid Layout of
Capacitor
(contact on top of capacitor not allowed)

(a) Common centroid


(b) Dummy poly2 strips
c1 c2
(c) Contact on top of thick oxide
(d) Matched poly2 terminals
c2 c1
(e) Protective well
(f) Well multiple biased

編撰者:張順志
7 - 91
Implement of the
Pipelined ADC Layout (1/2)
• Sample-and-hold
– Operational Amplifier
– Bias circuit
– Common mode feedback circuit
– Clock bootstrapped circuit
• One single stage
– MDAC
• Operational Amplifier
• Bias circuit
• Common mode feedback circuit
– Sub-ADC

編撰者:張順志
7 - 92
Implement of the
Pipelined ADC Layout (2/2)
• Clock generator
– Inverter
– NAND Gate
– OR Gate
• Delay element
– D-flipflop circuit
• Digital error correction circuit
– adder

編撰者:張順志
7 - 93
The Layout of Bias Circuit (1/12)
• The bias circuit is listed below Vbias-p

Mb7 Mb11 Vcasc-p


Mb8
Mb14 Mb18

Mb9 Mb6 Mb10

M15 Mb16

Mb1 Mb4 Mb13

Mb5

Mb17

Mb2 Mb3 Mb12

Rb Vcasc-n

Vbias-n
編撰者:張順志
7 - 94
The Layout of Bias Circuit (2/12)
¾電晶體匹配排法:

鑒於M1、M2、
M3、M4、12、
M13在尺寸大小
需匹配,故將此
2 3 2
五顆電晶體排成
如圖所示。

1 4 13
使用熱鍵”Ctrl+m”呼叫
出所需電晶體

2 12 2

編撰者:張順志
7 - 95
The Layout of Bias Circuit (3/12)
¾將繞線排列好:

將繞線排列在區
間中,此種做法
可以方便連線。

2 3 2

Contact 可使用熱鍵 可使用’path’繞線,


“o” 呼叫出來 1 4 13 熱鍵 “p”,如此方便
日後修改 layout

2 12 2

編撰者:張順志
7 - 96
The Layout of Bias Circuit (4/12)
¾將多餘的線段截掉,並將接點連接好:
如此便可完成此九
顆電晶體的連線。

2 3 2

1 4 13

2 12 2

編撰者:張順志
7 - 97
The Layout of Bias Circuit (5/12)
¾利用跨接的方式,以減少跨接電容效應:

編撰者:張順志
7 - 98
The Layout of Bias Circuit (6/12)
¾增加M6~M11,並考慮匹配排列:

8 6 11

9 7 10

編撰者:張順志
7 - 99
The Layout of Bias Circuit (7/12)
¾增加M18及Rb電阻:

M18

可利用Create->Resistor選
擇所需要的電阻值 Rb

編撰者:張順志
7 - 100
The Layout of Bias Circuit (8/12)
¾連接各點的POWER、GROUND:
將電晶體上連接
到VDD/GROUND
的點接起來,並加
上Body contact(
圖中框起來的地方)
,如此不僅可以連
起電源線,亦可減
少Latch-up的效應
,亦可使整體佈局
更完全。

編撰者:張順志
7 - 101
The Layout of Bias Circuit (9/12)
• 打上pin name,以進行LVS比對

¾ 打pin name 的注意事項:


¾ 利用熱鍵 ”l” 輸入pin
name (text)
¾ 選取text,利用熱鍵“q”選
擇text所在的pin Name材

¾ 此時text 落在metal 2 故
我們需選取 [pn] metal2
這個材質,如此做 LVS
時,電腦才能辨別。

編撰者:張順志
7 - 102
The Layout of Bias Circuit (10/12)
• 利用熱鍵”l”,叫出create text 視窗

輸入pin name
Text 的字型、大
小、方向的設定

編撰者:張順志
7 - 103
The Layout of Bias Circuit (11/12)
• 選擇 text 所需材質

1. 選取 text

2. 熱鍵”q”叫出property
視窗

7 - 104 3. 選擇 “pn” 開頭的材質,而非”dg” 編撰者:張順志


The Layout of Bias Circuit (12/12)
¾LVS驗證:
此階段可參考CIC
提供的Calibre-LVS
操作方式完成。

編撰者:張順志
7 - 105
The OPAMP Circuit
• The opamp circuit is listed below:

M7 M8 M11 M12

outp outn
M5 M6

M3 M4
M9 M10

M1 M2
Vip Vin Critical transistors need
perfect matching using
Common-centroid layout
Mc1 Mc2
technique

編撰者:張順志
7 - 106
The Layout of
Differential Pair (1/5)
¾將M1、M2匹配排列:

1 2 21

211 2

122 1

21 1 2 將電晶體排列成
Common-centroid
以達到match的效果

編撰者:張順志
7 - 107
The Layout of
Differential Pair (2/5)
¾以對稱的方式將線段連接好:

1221

2112

編撰者:張順志
7 - 108
The Layout of
Differential Pair (3/5)
¾為防止雜訊干擾,以Guard Ring保護差動對:

可利用Create->
Guard Ring的方式
建立。

編撰者:張順志
7 - 109
The Layout of
Differential Pair (4/5)
¾以對稱的方式完成M3~M8:

M5 M7

M6 M8

M3

M4

編撰者:張順志
7 - 110
The Layout of
Differential Pair (5/5)
¾以對稱的方式完成剩下的電晶體對:

M11

M12

M5 M7

M6 M8 M9/M10
對稱排列
M3 如M1/M2
MC1 MC2
排列方式
M1/M2 M4

編撰者:張順志
7 - 111
The Layout of Capacitance
¾以metal5、metal6及CTM5完成電容的佈局 (MIM電容):

CTMDUMMY,用於LVS驗證
此區域為電容。

CTM5 (定義電容大小),並將其切割
成八角形狀預防尖端放電的現象。

編撰者:張順志
7 - 112
Fully Layout of OPAMP (1/6)
¾將所有的單元擺置在一起,並思考排放的位置:
如此作法,可方便思
考佈局的排列方式,
可依照匹配的考慮或
電路拉線的方式等等
的考量,確定佈局排
列的方式。

編撰者:張順志
7 - 113
Fully Layout of OPAMP (2/6)
¾經由位置上的選擇,暫時將各元件排列如下:
此排列方式,也僅
是目前的考量,可
由之後的繞線後再
慢慢調整整個佈局
的形狀。

編撰者:張順志
7 - 114
Fully Layout of OPAMP (3/6)
¾開始M1~M8與Bias電路間的連線:

編撰者:張順志
7 - 115
Fully Layout of OPAMP (4/6)
¾完成M1~M8與Bias電路間的連線:

編撰者:張順志
7 - 116
Fully Layout of OPAMP (5/6)
¾完成整體電路的連線:
其中在繞線的時候,
需考量pre-sim中各
節點的電流大小,以
決定在佈局上信號線
的寬度,且在拉線上
,需要考慮對稱性,
並且盡量避免主要信號
線彼此跨線,若跨線則
需做shielding,減少
Coupling。

編撰者:張順志
7 - 117
Fully Layout of OPAMP (6/6)
¾將POWER、GROUND連起來完成OP的佈局:

input

output

Second Stage Bias First Stage

編撰者:張順志
7 - 118
The Layout of CMFB
• The CMFB circuit is shown below
Φ2 Φ1 Out+ Φ2 Φ1

Vcmref 1 4 7 10 Vcmref

C1 C2 C1
Φ2 Φ1 Φ2 Φ1
Vbias 2 5 8 11 Vbias
vb

C2 C1
C1
Φ2 Φ1 Φ2 Φ1

Vcmref 3 6 9 12 Vcmref
Out-

編撰者:張順志
7 - 119
The Layout of CMFB (1/4)
• 利用熱鍵 ”Ctrl+m”叫出電晶體,並依照電路圖的位置放置
電晶體

1 2 5 7 9 10

3 4 6 8 11 12

編撰者:張順志
7 - 120
The Layout of CMFB (2/4)
• 利用前述的電容的畫法,畫出單位電容,並且盡量靠近擺

•在電容週遭擺置dummy layer,使電容matching更好

• Guard ring: 防止noise coupling進來


• 將電容放置在N-Well 上面,使noise隔絕的效果更好

編撰者:張順志
7 - 121
The Layout of CMFB (3/4)
• 電晶體跟電容分別繞線繞好

使用Guard Ring使switch
的noise不要跑出來影響別

把輸入訊號和需與電容相
接的線繞在此一區域,減
少繞線距離

有關clock的線都繞在此處
方便未來global clock
routing

編撰者:張順志
7 - 122
The Layout of CMFB (4/4)
• Complete CMFB layout

編撰者:張順志
7 - 123
The Complete Layout of OPAMP
• 將補償電容、CMFB 和 opamp連接在一起
利用補償電容將opamp
和noisy CMFB隔絕開
,減少noise coupling
OPAMP
transistors 電容都盡量放置在N-well上
,以減少noise coupling,
頻率補償電容 並且電容的bottom plate要
接在insensitive point,top
Plate則接在sensitive point
CMFB1 ,以減少noise對電路的影

繞線時絕對要避免類比訊號
和 數位訊號跨接,若需跨接
CMFB2
,則應做shielding

編撰者:張順志
7 - 124
Layout of Clock
Bootstrapped Circuit (1/3)
• The clock bootstrapped circuit is listed below
M3 clk1b

M8
M7 M10

c1
M4
clk1

M13
M5
D
M9
clk1b S
M12
Bootstrapped Switch

編撰者:張順志
7 - 125
Layout of Clock
Bootstrapped Circuit (2/3)
• 將clock bootstrapped circuit中電晶體的部分獨立出來layout,而其電
容(C1)則和電路中其他電容整合在一起,方便未來layout matching。

電晶體擺放的原則就是
儘量使繞線的長度縮短
S3 ,以減少寄生效應。
VDD
8 3 4

13 7 5
G S5
9 12
10
S

clkb clk
gnd 編撰者:張順志
7 - 126
Layout of Clock
Bootstrapped Circuit (3/3)
• 把 Bootstrapped Switch和clock bootstrap circuit (不包含電
容)接在一起

G和S的繞線要盡量縮短,
避免過多的寄生電容,使
Clock Boost 的效果變差
(電容分壓效應)

G
S

Bootstrapped switch Clock bootstrapped circuit 編撰者:張順志


7 - 127
S/H Capacitor Array
• 將sample and hold 的電容和 clock boostrapped 的電容
整合在一起,彼此獨立做common-centroid matching

¾ common-centroid matching
¾ add dummy layer
Sh_c1 Sh_c2 cb1_c Cb2_c ¾ symmetry routing

Sh_c2 Sh_c1 cb2_c cb1_c

S/H capacitors clock bootstrap capacitors


編撰者:張順志
7 - 128
S/H Layout (1/2)
• 整合之前所完成的 sub-layout,如此便完成完整sample
and hold的layout

Analog 混合訊號layout最重要的準則:
1. 類比和數位電路離的越遠
OPAMP
越好

2. 類比和數位信號線最好不要
跨線,尤其在 ADC的layout
中。
Capacitor

digital Switches

編撰者:張順志
7 - 129
S/H Layout (2/2)
• 將 S/H layout 放大之後的capacitor 和switches的部分

Clock path

Clock bootstrapped circuit and input switch Other switches


編撰者:張順志
7 - 130
Layout of
Dynamic Comparator (1/6)
• The dynamic comparator circuit is listed below

M9 M10
M11 M12

latch
latch
O+
M7
M8 Out+
O-

M5 M6
Out-

Vref- M1 M2 M3 M4
In+ In- Vref+ This critical transistor
need perfect matching
so that the offset can be
reduced

編撰者:張順志
7 - 131
Layout of
Dynamic Comparator (2/6)
• 決定各電晶體的擺放位置

尺寸過大的電晶體,基於
10 9 11 12 7 8 layout形狀的考量,應以
並聯的型式layout

3 2 5 1 4 6 2 3
M1~M6 必須common-centroid
Layout,以減少mismatch
2 3 6 4 1 5 3 2

編撰者:張順志
7 - 132
Layout of
Dynamic Comparator (3/6)
• 進行各電晶體的繞線,完成partial comparator layout

latch 繞線時,應盡量以棋盤式
走線,如此較有規律,方
便繞線和未來的debug

繞線時,水平和垂直的線,
最好固定用特定材質,避免
Output 未來繞線時跨線的困難

Input &
Ref signal

編撰者:張順志
7 - 133
Layout of
Dynamic Comparator (4/6)
• NAND gate layout

編撰者:張順志
7 - 134
Layout of
Dynamic Comparator (5/6)
• 兩個不同尺寸的inverter layout

編撰者:張順志
7 - 135
Layout of
Dynamic Comparator (6/6)
• Partial comparator layout加入SR-Latch 和buffer的
layout,即完成整個comparator layout
SR-latch

Output

Input &
Ref signal

Buffer
編撰者:張順志
7 - 136
The Layout of Sub-ADC
in 1.5-bit Stage (1/5)
• The sub-ADC with its decoder is listed below

Dummy phi2

MSB
In+ +
+ + x
_ _
Ref-
_ LSB xb
In- LSB

+ zb
+ +
_ y
_
_
yb

Digital Decoder

編撰者:張順志
7 - 137
The Layout of Sub-ADC
in 1.5-bit Stage (2/5)
• Transmission Gate which is always on is usually used for
delay matching.

gnd

in out

VDD

TG Delay Circuit

編撰者:張順志
7 - 138
The Layout of Sub-ADC
in 1.5-bit Stage (3/5)
• Two cascaded inverter form the buffer circuit

inv1 Inv2

in out

Buffer Circuit

inv1 Inv2
編撰者:張順志
7 - 139
The Layout of Sub-ADC
in 1.5-bit Stage (4/5)
• 按照前頁的電路圖排列,呼叫出之前完成的comparator,並
且搭配NAND、INV、Buffer layout,經由straight forward的
繞線即可完成sub-ADC的layout

可利用熱鍵”i”呼叫出先前
已完成layout cell

7 - 140 Two comparators Digital Decoder 編撰者:張順志


The Layout of Sub-ADC
in 1.5-bit Stage (5/5)
• The signal flow of sub-ADC

zb

z
yb 這些信號未來將接到
MDAC的switch,當
y 控制訊號
xb

MSB LSB
編撰者:張順志
7 - 141
MDAC Layout Array
• MDAC的電容做common-centroid matching

¾ Guard Ring
¾ Capacitor located on
cs1 cf1 cs1 cf1 N-well
¾ Dummy capacitor layer
cf1 cs1 cf1 cs1 ¾ 2D common-centroid
layout technique
¾ minimum distance
among all capacitors
cs2 cf2 cs2 cf2

cf2 cs2 cf2 cs2

編撰者:張順志
7 - 142
MDAC Switch

clk

in out

clkb

TG Switch Circuit in

out

clkb clk

編撰者:張順志
7 - 143
MDAC Layout (1/4)
• MDAC Circuit Vinp

clk2
clk1 clk1a
clk1

x y z cs1 cf1

Out+
_ +
Ref- cm Ref+
+ _
Ref+ cm Ref-
Out-
x y z
cs2 cf2

clk1
clk1 clk1a
Switch array1
clk2

Vinn Switch array2


編撰者:張順志
7 - 144
MDAC Layout (2/4)
• 整合之前所完成的所有Cell,仔細考量繞線即可完成
complete MDAC layout

OPAMP 可利用熱鍵”i”呼叫
出先前已完layout
cell

Switch array2 Capacitor array

Sub-ADC with Switch array 1


decoder
編撰者:張順志
7 - 145
MDAC Layout (3/4)
• MDAC 繞線考量:
– 類比和數位訊號線要盡量分開,最好走線走不同區域
– 繞線時,線段盡量不要有額外的轉折,這些轉折在製程
製作上,都會產生額外的非理想效應
– cell 擺置的位置應考量整體 layout的形狀,理想為方形
或矩形。
– 規律性繞線對於未來做LVS check時,有助於Debug。

編撰者:張順志
7 - 146
MDAC Layout (4/4)
• 將 MDAC Layout 下半部放大

Analog path Digital path

編撰者:張順志
7 - 147
Layout of Last Stage (1/2)
• Last stage circuit diagram

In+ +
Ref+ + +
_ _
Ref-
In- _ LSB

+
+ +
_ _
cm
_

+
+ +
_ _
_

MSB

編撰者:張順志
7 - 148
Layout of Last Stage (2/2)
• 使用和sub-ADC in 1.5bit stage相同的comparator,並且
利用先前已完成的INV、NAND、OR gate layout

Clock path
region decoder

comparators
編撰者:張順志
7 - 149
Synchronization Cell Array (1/8)
• Flip-flop circuit

clk2
clk1
TG1
In Out
inv1

clk1 clk2
clk2

TG2 Inv2

First Part Second Part

編撰者:張順志
7 - 150
Synchronization Cell Array (2/8)
• Inverter layout

編撰者:張順志
7 - 151
Synchronization Cell Array (3/8)
• Transmission gate switch layout

clk

in out

clkb

TG Switch Circuit

編撰者:張順志
7 - 152
Synchronization Cell Array (4/8)
• 呼叫出先前完成的 TG、inv layout,按照電路的電路擺置
位置擺放,即完成flip-flop layout

First Part Second Part ¾ First part 和Second part


電路一樣,可完成其中一個
之後,利用熱鍵”c”複製完成
layout部分,以減少layout
TG1 時間且較對稱。
inv1 inv2
¾ Clock path 聚集在同一
TG2 區域方便拉線和Debug

Clock Path Region


編撰者:張順志
7 - 153
Synchronization Cell Array (5/8)
• 這只是示意圖,基本上每級Delay cell應該有兩條path(因
為每級輸出2bit codes),如下頁的示意圖一般

Synchronization cell array


編撰者:張順志
7 - 154
Synchronization Cell Array (6/8)
D Q
FF
CK

D Q
FF
CK

D Q D Q
FF FF
CK CK

D Q D Q
FF FF
CK CK

18

D Q D Q D Q D Q D Q D Q D Q D Q
FF FF FF FF FF FF FF FF
CK CK CK CK CK CK CK CK

D Q D Q D Q D Q D Q D Q D Q D Q
FF FF FF FF FF FF FF FF
CK CK CK CK CK CK CK CK

D Q D Q D Q D Q D Q D Q D Q D Q D Q
FF FF FF FF FF FF FF FF FF
CK CK CK CK CK CK CK CK CK

D Q D Q D Q D Q D Q D Q D Q D Q D Q
FF FF FF FF FF FF FF FF FF
CK CK CK CK CK CK CK CK CK

9
編撰者:張順志
7 - 155
Synchronization Cell Array (7/8)
• 呼叫先前完成的flip-flop layout cell,完成前頁所示之
synchronization delay cell

Stage1 Stage2 Stage3 為了使layout更為緊密,在layout


時,並不採用直接照著電路圖layout
圖,而是盡量堆疊flip-flop,使delay
cell 儘可能為一完整的矩形

Stage4 Stage5 Stage6 Stage7 Stage8 Stage9

編撰者:張順志
7 - 156
Synchronization Cell Array (8/8)

Clock path region

可利用熱鍵”shift+f” or “ctrl+f”切換呼叫出來的
Instant view

編撰者:張順志
7 - 157
Digital Error
Correction Circuit (1/4)
• 這是實現error correction function 的binary adder電路圖

OR
i1 d1

AND
i2
ci

d2

NOR1 NOR2

編撰者:張順志
7 - 158
Digital Error
Correction Circuit (2/4)
• NOR gate layout

編撰者:張順志
7 - 159
Digital Error
Correction Circuit (3/4)
• NAND gate layout

編撰者:張順志
7 - 160
Digital Error
Correction Circuit (4/4)
• Complete adder layout

AND NOR1 NOR2 OR

打 body contact 以避免latch-up,並且得接到乾淨的電源


7 - 161 以達到吸納noise的目的 編撰者:張順志
Combine the Layout of
Digital Circuits (1/2)
• 呼叫出adder和delay cell layout出來,將其繞線連接,即
完成數位電路部份的layout

Delay Cell

Digital error correction circuit


(included nine adders)

編撰者:張順志
7 - 162
Combine the Layout of
Digital Circuits (2/2)

Digital error correction


(adder)

編撰者:張順志
7 - 163
Layout of Clock Generator (1/10)
• Clock generator circuit
M1
– Main clock generator clk1a

inv2 Inv3 Inv4 Inv5


inv1 nand1
clk1

Inv10
Clock_in

clk2a

TG1 nand2 inv6 Inv7 Inv8 Inv9


clk2a
M2
– Comparator clock generator
INVdelay
clk1 invcom
Com_clk1

7 - 164 nandcom 編撰者:張順志


Layout of Clock Generator (2/10)
• Inverter layout (L=0.18um)

編撰者:張順志
7 - 165
Layout of Clock Generator (3/10)
• NAND gate layout (L=0.35um)

編撰者:張順志
7 - 166
Layout of Clock Generator (4/10)
• 呼叫先前完成的nand、inv gate layout,先按照電路圖的
位置擺置好

inv1 nand1 inv2 Inv3 Inv4 Inv5 M1

Inv10

TG1 nand2 inv6 Inv7 Inv8 Inv9 M2

編撰者:張順志
7 - 167
Layout of Clock Generator (5/10)
• 連接各cell即完成 main clock generator layout

clk1a clk1

這四個clock phases在接到
電路之前都將先經過inv、
TG Delay產生額外四個反向
Phase,之後再經由clock
buffer tree,然後才會接到
電路中

clk2a clk2

編撰者:張順志
7 - 168
Layout of Clock Generator (6/10)
• INVdelay Layout (L=0.6um)

編撰者:張順志
7 - 169
Layout of Clock Generator (7/10)
• INVcom Layout

編撰者:張順志
7 - 170
Layout of Clock Generator (8/10)
• NANDcom Layout

編撰者:張順志
7 - 171
Layout of Clock Generator(9/10)
• 將先前完成的INVdelay、NANDcom、INVcom等layout cell依
電路位置排置好,並將其繞線,即完成comparator clock
generator layout

Inv delay chain NAND

INV

編撰者:張順志
7 - 172
Layout of Clock Generator (10/10)
• Complete clock generator layout

clk1a clk1

comparator clock generator 1

Com_clk1

Com_clk2

main clock generator comparator clock generator 2

clk2a
clk2

編撰者:張順志
7 - 173
Clock Buffer Tree
• We use clock tree to reduce clock skew and buffer size

Buffer Clk1_1

Buffer Clk1_1
clk1
Buffer Buffer Clk1_1
Clk_tot Buffer Clk1_2
Clk Gen.

Buffer Clk1_2

Buffer Clk1_2

Buffer Buffer Clk1_2


clkn
Buffer Clk1_2

編撰者:張順志
7 - 174
Floor Plan

Stage Stage Stage Stage


S/H

Digital Error Correction


1 2 3 4

Delay Cell
Digital Region
Analog
Digital Output
Input
Clk_gen Stage Stage Stage Stage
8 7 6 5
Stage
9

Analog Region

編撰者:張順志
7 - 175
Complete ADC Layout (1/3)
• Die Area: 1mm*1mm

Stage StageStage Stage


SH 1 2 3 4

Digital Circuit
Clock Gen.
& Clock Buffer
Tree

Stage StageStage Stage


8 7 6 5
編撰者:張順志
7 - 176
Complete ADC Layout (2/3)
• Calibre DRC Check

編撰者:張順志
7 - 177
Complete ADC Layout (3/3)
• Calibre LVS Check

編撰者:張順志
7 - 178
Outline
• 1. Introduction
• 2. Specifications of A/D converter
• 3. Circuit design and simulations
• 4. The implement of pipelined ADC layout
• 5. Measurement setup and consideration
• 6. Conclusion
• 7. Reference

編撰者:張順志
7 - 179
Measurement Setup and
Consideration (1/2)
• Instrument and circuit
for ADC measurement :
1. Voltage reference generator
(LM317)
2. Pulse generator
3. Function generator (HP33120)
4. Power supply (HP E3631A)
5. Logic analyzer (HP 16500B)
6. PC
7. Filter tank
8. Isolator
9. Single to differential circuit
10. Voltage regulator
11. Low pass filter
12. Bypass filter

編撰者:張順志
7 - 180
Measurement Setup and
Consideration (2/2)
Isolator: reduce digital supply coupling
Single to differential circuit: Bead inductor reduce high frequency noise

Voltage regulator: generate


VDDA and VDDD voltage Reference voltage
generator circuit: Bypass filter:

Vo = 1.25(1+R1/R2)+IadjR2
編撰者:張順志
7 - 181
Outline
• 1. Introduction
• 2. Specifications of A/D converter
• 3. Circuit design and simulations
• 4. The implement of pipelined ADC layout
• 5. Measurement setup and consideration
• 6. Conclusion
• 7. Reference

編撰者:張順志
7 - 182
Conclusion
• The analog and digital signal path must be
separated clearly in the layout mixed signal
circuit such as ADC.
• The performance of layout will play a important
role on the performance of ADC.
• We must consider the issues of layout at the
circuit design level so that iteration can be
reduced.
• The more we consider, the more we get.

編撰者:張順志
7 - 183
Outline
• 1. Introduction
• 2. Specifications of A/D converter
• 3. Circuit design and simulations
• 4. The implement of pipelined ADC layout
• 5. Measurement setup and consideration
• 6. Conclusion
• 7. Reference

編撰者:張順志
7 - 184
Reference (1/2)
• M. Amourah and R.L. Geige, “All digital transistor high gain operational
amplifier using positive feedback technique,” IEEE International
Symposium on Circuits and Systems, vol.1 , pp.26-29, May 2002
• Jong-Bum Park, Sang-Min, YooSe-Won Kim, Young-Jae Cho, and Seung-
Hoon Lee, “A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter
with 400-MHz input bandwidth,” IEEE Journal of Solid-State Circuits,
vol.39, issue.8, Aug. 2004
• Jipeng Li and Un-Ku Moon, “A 1.8-V 67-mW 10-bit 100-MS/s pipelined
ADC using time-shifted CDS technique,” IEEE Journal of Solid-State
Circuits, vol.39, issue.9, Sept. 2004
• O. Stroeble, V. Dias, and C. Schwoerer, “An 80 MHz 10 b pipeline ADC
with dynamic range doubling and dynamic reference selection,” IEEE
International Solid-State Circuits Conference, pp.15-19, Feb. 2004
• Byung-Moo Min, P. Kim, D. Boisvert, and A. Aude, “A 69 mW 10 b 80
MS/s pipelined CMOS ADC,” IEEE International Solid-State Circuits
Conference, 2003
編撰者:張順志
7 - 185
Reference (2/2)
• Mikko E. Waltari and Kari A. I. Halonen, “Circuit techniques for low-
voltage and high-speed A/D converters,” Kluwer Academic Publishers
• “Nyguist-Rate A/D Converter Design” 謝晉昇
• T. B. Cho and P. R. Gray, “A 10b, 20MSample/s, 35mW Pipeline A/D
Converter,” IEEE Journal of Solid-State Circuits, vol.SC-30, no.5, pp.166-
172, Mar. 1995.
• Yong-In Park, S .Karthikeyan, F. Tsay, and E. Bartolome, “A 10-b 100-
MSample/s CMOS pipelined ADC with 1.8 V power supply,” IEEE
International Solid-State Circuits Conference, Feb. 2001

編撰者:張順志
7 - 186