You are on page 1of 68

PLL Verification Workshop Version 1.

12

PLL Verification
Workshop

Product Version: IC 6.1.6, MMSIM 13.1, INCISIV 13.2


Workshop Version: 1.12
Date: Jun 2014

© 2014 Cadence Design Systems, Inc. All rights reserved Page 1 of 68


PLL Verification Workshop Version 1.12

© 2002-2014 Cadence Design Systems, Inc. All rights reserved.

Printed in the United States of America.

Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA

Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence)
contained in this document are attributed to Cadence with the appropriate symbol. For queries
regarding Cadence’s trademarks, contact the corporate legal department at the address shown
above or call 800.862.4522.

All other trademarks are the property of their respective holders.

Restricted Print Permission: This publication is protected by copyright and any unauthorized use
of this publication may violate copyright, trademark, and other laws. Except as specified in this
permission statement, this publication may not be copied, reproduced, modified, published,
uploaded, posted, transmitted, or distributed in any way, without prior written permission from
Cadence. This statement grants you permission to print one (1) hard copy of this publication
subject to the following conditions:

The publication may be used solely for personal, informational, and noncommercial purposes;

The publication may not be modified in any way;

Any copy of the publication or portion thereof must include all original copyright, trademark,
and other proprietary notices and this permission statement; and

Cadence reserves the right to revoke this authorization at any time, and any such use shall be
discontinued immediately upon written notice from Cadence.

Disclaimer: Information in this publication is subject to change without notice and does not
represent a commitment on the part of Cadence. The information contained herein is the
proprietary and confidential information of Cadence or its licensors, and is supplied subject to,
and may be used only by Cadence’s customer in accordance with, a written agreement between
Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does
not make, and expressly disclaims, any representations or warranties as to the completeness,
accuracy or usefulness of the information contained in this document. Cadence does not warrant
that use of such information will not infringe any third party rights, nor does Cadence assume
any liability for damages or costs of any kind that may result from use of such information.

Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as


set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 2 of 68


PLL Verification Workshop Version 1.12

Contents
1 OVERVIEW ............................................................................................................................ 4
1.1 DESIGN EXAMPLE ............................................................................................................................................4

1.2 WORKSHOP FLOW ............................................................................................................................................5

1.3 TOOLS USED ....................................................................................................................................................6

1.4 BEFORE YOU BEGIN .........................................................................................................................................6

1.5 DEFINITIONS ....................................................................................................................................................6

1.6 ACRONYMS USED IN THIS DOCUMENT..............................................................................................................6

2 CLOSED LOOP DYNAMICS EVALUATION USING PHASE DOMAIN MODELS .. 7


3 VCO TUNING (KVCO) AND PHASE NOISE CHARACTERIZATION ..................... 17
3.1 THE VCO TEST BENCH .................................................................................................................................. 17

3.2 VCO KVCO CHARACTERIZATION................................................................................................................... 20

3.3 VCO PHASE NOISE CHARACTERIZATION ....................................................................................................... 30

3.4 VCO CHARACTERIZATION OVER CORNERS ................................................................................................... 36

4 PHASE FREQUENCY DETECTOR (PFD)/ CHARGE PUMP (CP) NOISE


CHARACTERIZATION ........................................................................................................... 44
5 PHASE NOISE EVALUATION OF THE CLOSED-LOOP PLL ................................... 53
5.1 (OPTIONAL) USING ADE XL TO ANALYZE NOISE CONTRIBUTIONS............................................................... 58

6 FRACTIONAL-N PLL FUNCTIONAL VERIFICATION .............................................. 63

© 2014 Cadence Design Systems, Inc. All rights reserved Page 3 of 68


PLL Verification Workshop Version 1.12

1 Overview
The workshop demonstrates various methods of characterizing Phase-Lock Loops (PLLs) and
their principle components. It is meant to compliment the presentation portion of the PLL Design
Verification seminar.

1.1 Design Example


The PLL design example selected for this workshop is intended for a use in a Wireless Local
Area Network (WLAN) application (IEEE 802.11b). The PLL-based frequency synthesizer is
required to provide the clocks signals necessary to drive the RF mixers of a direct conversion
architecture transceiver operating in the 2.4GHz band.

The code name for this design is Zambezi45. It has been implemented in a fictional but
representative 45nm CMOS process.

The performance requirements for this PLL are detailed in the table below.

Parameter Conditions/Notes Min Typ Max Unit


VCO Output Frequency
4800 4970 MHz
(fvco)

Synthesizer Output At divide by 2 outputs


Frequency 2400 2485 MHz
(fout)
Frequency step @ fout Tuning resolution 9.765 kHz

Settling time @ fout To within +50 kHz of final frequency

For full band step Time includes VCO calibration. Actual time
depends on approximate prediction of
(tplllock) calibration result within 3 band settings of
100 us
final result value and presetting
calibration start via vcobndset<4:0>. See
VCO Calibration section

From Sleep to Power ON 200 us

Spurious @ fout
+ 10 kHz < Foffset < +10 dBc
-45
MHz

Foffset > + 10 MHz -56 dBc

Integrated from + 30 kHz to degRMS


2
+ 8 MHz

At > +10 MHz offset -124 dBc/Hz

I to Q, at Tx or Rx divider outputs. This is


1 Quadrature Phase Error intended to be cleaned up with a poly-
deg
phase filter, external to the Synthesizer
10
@ fout
macro.

The design architecture for the Zambezi PLL is given below:

© 2014 Cadence Design Systems, Inc. All rights reserved Page 4 of 68


PLL Verification Workshop Version 1.12

dvdd/dgnd dvdd/dgnd

fsynth<13:0> Modulator  atb_p


dither<2:0>
Modulator ATB atb_m
bypass Control

(1.0v) dvdd 1.2V (LF)


dgnd
Multi-
Modulus
Divider
1.2V (LF) 1.2V (HF) 1.2V (HF) 1.2V (HF) 1.2V (HF)

PFD & Loop LPF VCO rxiclk


I&Q rxqclk
(20MHz) refclk CP Filter
(20MHz) refclk_n Divide
by 2 txiclk
txqclk
(2.5v) avdd_h RC VCO
agnd_h 1.2V Regulator (HF)
Calibration Calibration
1.2V Regulator (LF) Control Control
dvdd/dgnd dvdd/dgnd

This PLL is a Fractional-N type using a Delta-Sigma Modulator (DSM) in the feedback divider
loop. This VCO uses a LC tank architecture. Both the VCO and the Low Pass Filter (LPF)
blocks contain calibration circuitry to enable the PLL to meet its specifications over all process
and temperature conditions. Finally, separate voltage regulators are used for the high and low
frequency portions of the design in order to provide the required isolation for low noise
operation.

1.2 Workshop Flow


We will begin by investigating the application of linear phase domain modeling techniques to
study the closed-loop PLL performance. This approach allows one to quickly optimize the
overall design and to identify the key sub-block specifications. Next, we will examine and
characterize the performance for the realized transistor level implementations for the following
sub-blocks: VCO, Phase-Frequency Detector (PFD), and Charge Pump (CP) sub-blocks. We will
then enter the key metrics obtained from these simulations back into our linear phase domain
model in order to confirm meeting the top-level closed loop performance requirements. Finally,
we will investigate functional verification techniques for the complete final transistor-level PLL
realization.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 5 of 68


PLL Verification Workshop Version 1.12

1.3 Tools Used


This workshop uses the following Cadence products:

Product Name Release Release Name Products Used

 Virtuoso IC Design Framework


Virtuoso 6.1.6 IC6.1.6.500.6
 Analog Design Environment (ADE)
 Spectre APS, Spectre RF Circuit
MMSIM 13.1 MMSIM13.1.ISR5
Simulator

INCISIV 13.2 INCISIV13.02.002  AMSDesigner Simulator

1.4 Before You Begin


The following instructions assume the Zambezi45 PLL example design database and above
mentioned Cadence tools have been properly installed on your computer and they are accessible
from your environment. As necessary, please follow the installation and configuration
instructions given in the database root installation directory README.txt file.

1.5 Definitions
CIW – Virtuoso Command Interpreter Window – Main window that first appears when the
Virtuoso design framework is first started.

$PROJECT – Root directory of the seminar workshop workspace

1.6 Acronyms used in this Document

Abbreviation Description
LMB Left Mouse Button. Indicates that you are to press the left mouse button

MMB Middle Mouse Button Indicates that you are to press the middle mouse
button

RMB Right Mouse Button Indicates that you are to press the right mouse button

© 2014 Cadence Design Systems, Inc. All rights reserved Page 6 of 68


PLL Verification Workshop Version 1.12

2 Closed Loop Dynamics Evaluation using Phase Domain


Models
In this section, we will evaluate the PLL loop dynamic characteristics such as settling time, loop
bandwidth, and stability by running the Transient, AC, and Stability analyses, respectively on
the PLL phase domain model.

The linear phase domain modeling approach enables very fast closed loop PLL simulations (<
1s). This technique will be applied to characterize PLL closed loop behavior including following:

 Step response: for start-up/frequency-hopping settling times and phase/frequency settling


curve damping behavior.
 Closed loop frequency response: for input/output and VCO/output transfer functions, 3dB
bandwidth, gain peaking magnitude/frequency, and high frequency suppression.
 Stability analysis: provides the loop phase margin
 Total and individual noise contributions from different noise sources: for jitter and phase
noise determinations. (to be exercised in a later workshop section)

Via the characterized parameters, designers can pick proper design parameters such as charge
pump (CP) current, LF/LPF configuration and RC values, and VCO gain. Note that the nonlinear
behavior such as cycle slipping won’t be obtained here because of the linear approximation.
Non-linear behavior can be observed from simulations using voltage domain models (such as
those used in later workshop sections).

We will now study closed loop PLL behavior using Linear Phase Domain Models.

ACTION 1: Start virtuoso. In the command line, type the following commands:

% cd $PROJECT/WORK/pll_zambezi45
% source project.cshrc
% virtuoso –log CDS.log &

The project.cshrc file should specify the locations of all of the required tool executables (location
of the IC product installation) and other environment setup such as the location of the cadence
license file. If the virtuoso fails to start, make any corrections to this file.

After Virtuoso starts you should see the main Virtuoso window (often referred to as the CIW) as
shown below:

© 2014 Cadence Design Systems, Inc. All rights reserved Page 7 of 68


PLL Verification Workshop Version 1.12

The Cadence Library Manager window should also appear as follows:

We will use the Library Manager to locate and open the schematic containing the PLL linear
phase domain model

ACTION 2: In the Library Manager window, open the following schematic view for read.

Library: zambezi45_sim
Cell: pll_phase_domain_sim
View: schematic

After selecting the view in the Library Manager, do RMB->Open (Read-Only)…

© 2014 Cadence Design Systems, Inc. All rights reserved Page 8 of 68


PLL Verification Workshop Version 1.12

The following Virtuoso Schematic Editor window will appear containing the schematic for the
linear phase domain PLL model as shown below.

Please review the contents of this schematic model. Each major functional PLL component is
represented in this model with various noise contribution sources placed at the appropriate
locations within the loop.

We will first disable all noise sources and study the closed loop dynamics.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 9 of 68


PLL Verification Workshop Version 1.12

ACTION 3: Launch the Cadence Analog Design Environment (ADE) application. From the
schematic Editor window select Launch->ADE L/ The following window will appear.

We will use ADE to setup and perform the Spectre simulations. We will load an existing saved
simulation setup.

ACTION 4: In the ADE window, select Session->Load State… The following form will
appear. Select the spectre_loop_dynamics state as shown below and select the OK button located
at the bottom of the form.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 10 of 68


PLL Verification Workshop Version 1.12

The ADE window will be populated with the analysis and output setup information from the
saved state.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 11 of 68


PLL Verification Workshop Version 1.12

This simulation setup performs a series of basic transient, Transient, small-signal AC, and
Stability analyses designed to characterize the phase domain PLL closed-loop behavior. The
transient analysis is used to determine the loop step response. It is used to measure the
/frequency-hopping settling times and the phase frequency settling times. The AC analysis
provides the closed-loop frequency response. Including the input-output and VCO-output
transfer functions, -3dB bandwidth, gain peaking, and noise shaping. Finally, the stability
analysis provides the loop phase margin.

Each of the injected noise sources shown on the schematic have been disabled by setting the
corresponding ON_* ADE Design Variables highlighted above to 0. The following picture
shows which noise sources have been disabled

© 2014 Cadence Design Systems, Inc. All rights reserved Page 12 of 68


PLL Verification Workshop Version 1.12

ACTION 5: In ADE window, select Simulation->Netlist and Run. It will take about a second
to complete. The plots as shown below should appear.

The upper-left sub-window is the step response from transient analysis for the settling time
evaluation. The upper-right sub-window is the closed-loop frequency response from the small-
signal AC analysis for the PLL transfer function and 3dB bandwidth measurement. The lower-
left sub-window is the stability plot from stability analysis for phase and gain margin evaluation.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 13 of 68


PLL Verification Workshop Version 1.12

We will first measure the frequency setting lime. This will be done by measuring the time for the
output of the feedback ph_div divider to settle after a pulse (step) signal is applied to the ph_in
input

ACTION 6: In the waveform window, select the step response sub-window. RMB click to
copy a new window (Copy toNew windowRectangular). Adjust the y-axis to -100uV to
100uV by LMB double clicking on the y-axis, selecting the Scale tab on the Axis Properties
form, selecting the Manual mode, and setting the Axis Limits.

ACTION 7: Place markers and delta-marker as shown below. Use the M bind key to place
markers on the ph_in and ph_div traces. Position the marker so the Y-axis value is
approximately 25uV ( for example assuming a 25ppm settling time requirement). Once both
markers have been created, use the Ctrl+LMB key to select both markers. Then select Marker-
>Create Delta Marker from the waveform window menus.

It is interpreted as the frequency hops at 10us, and the new frequency settles within 25ppm in
62us. Please refer to PLL design literature for additional details.

We will now look at the closed-loop frequency response characteristics. For this study the small-
signal AC source as the ph_in has been swept and we have plotted the frequency response of the
ph_div output signal.

ACTION 8: In the waveform window, return to the first tab and select the frequency response
sub-window. RMB click to copy a new window (Copy toNew windowRectangular). Place
markers and delta-marker as shown below.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 14 of 68


PLL Verification Workshop Version 1.12

This measurement indicates the PLL input-output closed-loop transfer function has ~1dB gain
peaking at 42 kHz and 3dB bandwidth of 224 kHz.

On to the results of the stability analysis…

ACTION 9: In the waveform window, select the stability sub-window. RMB click to copy a
new window (Copy toNew windowRectangle).

© 2014 Cadence Design Systems, Inc. All rights reserved Page 15 of 68


PLL Verification Workshop Version 1.12

Phase

Gain

We directed the stability analysis to measure the loop gain and phase on the ph_div signal. Both
the loop gain phase (LOOPGAIN (deg)) and loop gain magnitude (LOOPGAIN ((dB)) are
plotted above. To measure the phase margin, one needs to locate the point on the gain magnitude
plot having gain of 0dB and then measure the corresponding phase.

ACTION 10: Add a vertical marker to the above plot. In the waveform window, select Marker-
>Create Marker. In the form that appears, insure the Vertical tab is selected and OK the form. A
vertical marker will appear on the graph. Use the LMB to drag the marker to the point at which
the gain curve is 0dB. The phase margin can be read directly from the marker label on the phase
plot.

Note: 0 deg of LOOPGAIN (deg) plot corresponds to -180deg if one breaks the loop and
measures the AC phase. So the phase value 63deg (at the frequency where LOOPGAIN (dB) is
0) is the phase margin.

ACTION 11: Close the waveform and ADE windows.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 16 of 68


PLL Verification Workshop Version 1.12

3 VCO Tuning (Kvco) and Phase Noise Characterization


In this section, we will characterize the VCO tuning curves (output frequency versus control
voltage) and the output phase noise by performing swept Harmonic-Balance and Pnoise
analyses.

3.1 The VCO Test Bench


ACTION 12: Use the Library Manager to open the following test bench schematic in read-only
mode.

Library: zambezi45_sim
Cell: pll_vco_core_sim
View: config

Note: We are opening the Hierarchy EDitor (HED) configuration or config view instead of
directly opening the schematic view. Use of the config view enables more control over view
selection during the hierarchical design elaboration process. For example, one may wish to
replace some non-critical circuit function blocks with behavioral models during simulation in the
interest of reducing simulation run times.

ACTION 13: When the following Open Configuration or Top CellView form appears, choose to
open the schematic top cell view as shown. You may also choose to open the configuration view
if you wish but we will not be further discussing the contents of the this view. OK the form when
done.

The schematic below will appear. This is the test bench we will be using to characterize the
VCO.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 17 of 68


PLL Verification Workshop Version 1.12

We will be evaluating a 5GHz VCO. The VCO provides a differential output signal to drive
divide-by-2 dividers providing quadrature 2.5GHz signals to the direct down conversion and
direct up conversion mixers in the receiver and transmitter respectively. The VCO output is also
connected to the PLL feedback dividers. The VCO controls include a 5-bit band selection bus to
select from 32 overlapping bands. The overlapping tuning bands provide sufficient VCO
bandwidth so as to allow for process variations and frequency drift due to varying supply and
operating temperatures. Provisions are included to calibrate the VCO so the required band can
be determined given the current operating conditions. Finally, there is the VCO vtune fine
frequency control meant to be connected to the output of the PLL loop filter.
The vcobnd<4:0> bus is driven by a stimulus source generating the 5-bit stimulus It’s outval
parameter is set a design variable bandNum in order to facilitate sweeping of the band number
across all 32 VCO sub-bands.
We will now descend into the VCO in order to study its design in more detail.

ACTION 14: LMB Select the pll_vco_core instance and then do RMB->Descend Read... The
following form will appear. Make sure the schematic view is selected and OK the form.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 18 of 68


PLL Verification Workshop Version 1.12

The following VCO schematic will appear.

You can see this is a LC tank type of VCO. Course tuning is provided by switching binary
weighted groups of capacitors located on the bottom. Fine tuning adjustment (vtune) is realized
using varactors located in the center block. The VCO output is later buffered before being
connected to the quadrature divide-by-2 and PLL feedback dividers.

ACTION 15: When done reviewing the design please return to the top-level test bench by
selecting RMB->Return.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 19 of 68


PLL Verification Workshop Version 1.12

3.2 VCO Kvco Characterization


Kvco measurement requires sweeping the tuning voltage (vtune), measuring the corresponding
VCO output frequency, and using this information to calculate the Kvco slope. Kvco varies over
the vtune voltage range. Full VCO characterization requires sweeping vtune over its entire range
and over each of the 32 VCO sub-bands. However, for the moment will we focus on a single
mid-band (bandNum=15).

ACTION 16: Launch the Cadence Analog Design Environment (ADE) application. From the
schematic Editor window select Launch->ADE L. The following window will appear.

We will use ADE to setup and perform the Spectre APS simulations. But we first must define the
simulation analysis and measurement setup.

ACTION 17: In the ADE window, select Analyses->Choose… The following form will appear.
Select the hb (Harmonic Balance) analysis.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 20 of 68


PLL Verification Workshop Version 1.12

© 2014 Cadence Design Systems, Inc. All rights reserved Page 21 of 68


PLL Verification Workshop Version 1.12

The Spectre APS Smart Harmonic Balance (HB) engine is the primary analysis used to
characterize the VCO. Harmonic balance works well for high dynamic range and weakly
nonlinear systems such as this sinusoidal LC tank VCO. We will use this analysis to obtain the
accurate periodic steady-state operation in the frequency domain which then can be used to make
the required measurements. The Spectre RF harmonic balance analysis engine utilizes a
Transient-Aided approach for HB. Using this approach, an initial transient analysis is performed
in order to place the design near its steady-state condition and improve overall convergence.

The HB analysis setup for an autonomous circuit such as a VCO requires an initial guess for the
oscillation frequency.

ACTION 18: In the above from locate the Fundamental Frequency field and enter 5G. This is
the expected center frequency for this design.

We will leave the Number of Harmonics field set to auto. In this mode, the number of
harmonics will be determined automatically in order to satisfy the accuracy criteria.

ACTION 19: Change the Accuracy Defaults (errpreset) option to Conservative.

The errpreset option adjusts a number of simulator options (reltol, relref, method, etc.)
influencing the accuracy of results. The conservative setting is recommended for most RF
applications.

The HB analysis oscillation setup also requires specification of the oscillation nodes.

ACTION 20: In the form, first select the Oscillator checkbox. Use the Select button to select the
/a and /b oscillator output signals for the Oscillator node+ and Oscillator node- fields
respectively. Also disable the Calculate initial conditions (ic) automatically option

© 2014 Cadence Design Systems, Inc. All rights reserved Page 22 of 68


PLL Verification Workshop Version 1.12

Finally to complete the hb analysis setup and in order to characterize Kvco over the entire tuning
range we will be repeating the analysis while sweeping the vtune (tuning voltage) design
variable.

ACTION 21: Select the Sweep checkbox. In the Variable Name field enter vtune or use the
Select Design Variable button to select from a list of available design variables. Specify a sweep
range Start value of 0 and a Stop value of 1.2 (Volts). The Step Size should be set to 0.1.

ACTION 22: Make sure the hb analysis is enabled and OK the analysis setup form.

You should now see the hb analysis entered into the Analyses Panel in ADE.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 23 of 68


PLL Verification Workshop Version 1.12

We are now ready to begin the simulation.

ACTION 23: To start the simulation, select the (Netlist and Simulate) button.

The simulation will start by performing an initial transient analysis followed by the invocation of
the Smart HB analysis engine – iterating for each swept vtune value.

The simulation should complete in 2-3 minutes.

Once the simulation finished we can start examining the results.

ACTION 24: In the ADE window, select Results->Direct Plot->Main Form. The Waveform
plotting window will appears along with the Direct Plot Form as shown below.

ACTION 25: On the Direct Plot Form, select the Harmonic Frequency function. Ensure the
fundamental Harmonic Frequency is selected. Also, check the Add to Outputs option. Select the
Plot button.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 24 of 68


PLL Verification Workshop Version 1.12

The oscillator output frequency as a function of the tuning voltage vtune should now be plotted
as follows:

© 2014 Cadence Design Systems, Inc. All rights reserved Page 25 of 68


PLL Verification Workshop Version 1.12

The slope of this curve is the Kvco value which we require for our top-level PLL phase domain
model.

The effect of selecting the Add to Outputs option on the Direct Plot Form is to have the
calculator expression necessary to replot this graph added to the ADE window Outputs panel.

ACTION 26: Close the Direct Plot Form and the waveform plotting window.

ACTION 27: Return to the main ADE window and double LMB click on the output added to
the Outputs panel. The following Setting Outputs form will appear:

© 2014 Cadence Design Systems, Inc. All rights reserved Page 26 of 68


PLL Verification Workshop Version 1.12

The Setting Outputs form is one way in ADE that a simulation output measurement expression
can be created or modified.

ACTION 28: Change the Name of the output to Freq Plot. Then select the Change button
located near the bottom of the form.

We will now modify this expression in order to create a new expression which will plot the slope
of the frequency tuning curve so we can measure Kvco.

ACTION 29: Change the Name of the Output to Kvco Plot. Select the Calculator Open button.
The calculator window appears.

In the Calculator window the existing output expression can be seen. We will use the derivative
function (deriv) in order to calculate Kvco.

ACTION 30: In the calculator, select the deriv function located in the Function Panel when the
Special Functions are selected. The derive() function will be added the expression. Repeat this
step to enclose the expression in the abs() function. Note: this abs() function is available under
the Math Functions.

The final function should look as follows:

ACTION 31: We can now plot this function. Select the button.

The following waveform will appear.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 27 of 68


PLL Verification Workshop Version 1.12

ACTION 32: Close the waveform window and return to the Setting Outputs form and select the
Get Expression button. The expression from the calculator will be pasted into the Expression
field on this form.

The Setting Outputs form should now appear as follows:

ACTION 33: On the Setting Outputs form. Select the Add button. The Kvco Plot expression
should now appear in the ADE Outputs panel.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 28 of 68


PLL Verification Workshop Version 1.12

ACTION 34: Repeat the previous steps and 2 additional expressions for capturing 2 additional
output measurement expressions:

Max. Kvco – This scalar value shows the maximum Kvco turning curve slope.

ymax(abs(deriv(harmonic(xval(getData("I1.R0.R0.n1" ?result "hb_fd")) '1))))

Min. Kvco - This scalar value shows the maximum Kvco turning curve slope.

ymin(abs(deriv(harmonic(xval(getData("I1.R0.R0.n1" ?result "hb_fd")) '1))))

ACTION 35: Close the Calculator window and Cancel the Setting Outputs form when done.

The Outputs Panel should now contain the following measurements:

ACTION 36: We can now evaluate all of the functions by selecting the button located in the
menu on the right side of the ADE window.

Both the Freq Plot and Kvco Plot should appear in the waveform window. Meanwhile Max.
Kvco and Min. Kvco should be evaluated to produce scalar results captured in the Output panel.

In the future, when the simulation is rerun these waveforms and scalar measurements will be
evaluated automatically when the simulation completes.

ACTION 37: Close the waveform plotting window.

ADE setup may be saved for later use.

ACTION 38: In the ADE window select Session->Save State… The following form will
appear:

© 2014 Cadence Design Systems, Inc. All rights reserved Page 29 of 68


PLL Verification Workshop Version 1.12

ACTION 39: Select a name for the State and OK the form. The state will be stores as view
located under the same cell name as the test bench schematic.

ACTION 40: Close the ADE window. Select Session->Quit.

3.3 VCO Phase Noise Characterization


VCO phase noise characterization uses extensions on the basic Spectre APS HB analysis to study
the output phase noise characteristics of the VCO. The additional analysis is called hbnoise or
simply Harmonic Balance Noise analysis.

We will be using a modified test bench schematic that also containing the VCO output buffers so
we can study the VCO and buffer noise at the same time.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 30 of 68


PLL Verification Workshop Version 1.12

We will load a saved ADE state for this analysis.

ACTION 41: Return to the ADE window and select Session->Load State and select the
spectre_PhaseNoise state as shown and OK the form.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 31 of 68


PLL Verification Workshop Version 1.12

The ADE window will be populated with the analysis and output setup information from the
saved state.

This ADE setup is similar to Kvco measurement except the HB analysis is performed for a single
vtune value and after the HB steady-state response is calculated; an HBnoise analysis is
performed to calculate the phase noise. The measurement setup located on the Outputs panel
records the phase noise at various offsets from the calculated VCO fundamental output tone.

ACTION 42: In the ADE Analyses panel, double-click hbnoise analysis in order to view the
setup.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 32 of 68


PLL Verification Workshop Version 1.12

The harmonic balance noise (HBnoise) analysis is similar to conventional noise analysis, except
that HBnoise analysis includes frequency conversion effects. As a consequence, it is useful for
predicting the noise behavior of mixers, switched-capacitor filters, and other periodically driven

© 2014 Cadence Design Systems, Inc. All rights reserved Page 33 of 68


PLL Verification Workshop Version 1.12

circuits. It is particularly useful for predicting the phase noise of autonomous circuits, such as
oscillators.

HBnoise analysis linearizes the circuit about the periodic operating point computed by the HB
analysis. It is the periodically time-varying nature of the linearized circuit that accounts for the
frequency conversion. In addition, the effect of a periodically time-varying bias point on the
noise generated by the various components in the circuit is also included.

The time-average of the noise at the output of the circuit is computed in the form of a
spectral density versus frequency. For this design the output of the circuit is specified with a pair
of nodes – vcoclk and vcoclk_n.

The noise analysis always computes the total noise at the output, including contributions
from the input source and the output load. The amount of the output noise that is attributable to
each noise source in the circuit is also computed and output individually.

The noise analysis in this example is calculated for several absolute swept frequency points (100-
>1GHz)

The maximum sideband field defines the maximum number of harmonics used for the noise
calculation. In practice, noise can mix with each of the harmonics of the periodic drive signal
applied in the HB analysis and end up at the output frequency.

If Ki represents sideband i, then for periodic noise,

f(noise_source) = f(out) + Ki * fund(hb)

For quasi-periodic noise with multiple tones in HB analysis, assuming there are one large tone
and one moderate tone, Ki is represented as [Ki_1 Ki_2]. The corresponding frequency shift is

Ki_1 * fund(large tone of HB) + Ki_2 * fund(moderate tone of HB)

Assuming that there are L large and moderate tones in HB analysis and a set of n integer vectors
representing the sidebands

K1 = { K1_1,...K1_j..., K1_L}, K2, ..., Kn.

Then

f(noise_source) = f(out) + SUM_j=1_to_L{ Ki_j * fund_j(hb) }

ACTION 43: OK the Choosing Analyses from when finished examining the HB Noise analysis
setup.

ACTION 44: In the ADE window, go to the Outputs pane and enable plotting of the Phase
Noise as shown below.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 34 of 68


PLL Verification Workshop Version 1.12

ACTION 45: When ready to perform the simulation, select the (Netlist and Simulate)
button.

Following the standard HB analysis to determine the steady-state, an hbnoise analysis will be
performed across the specified swept frequency range. The simulation should complete in
approximately 1 minute.

After the simulation completes you should see the Phase Noise plot as shown below

You should also observe the scalar measurements recorded in the ADE Outputs Panel.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 35 of 68


PLL Verification Workshop Version 1.12

ACTION 46: Close the ADE window, select Session->Quit. Say No if asked to save any
changes.

3.4 VCO Characterization over Corners


In the previous sections we characterized the VCO – measuring Kvco and Phase Noise under
nominal conditions. Where the nominal conditions refers to the combination of typical process
corner, supply voltage (VDD=1.2V), and default simulation temperature (27C). More complete
block-level characterization usually requires simulation across all possible operating conditions –
most commonly Process, Voltage, and Temperature (PVT) corners. This can be tedious to do if
there are many corners and/or many characteristics which need to be measured. We will
therefore introduce the Virtuoso ADE XL environment.

ADE XL is an extension built on top of ADE L simulation environment used in the previous
sections. The focus in this section will be to use the multiple test and corner analysis capabilities
of ADE XL to demonstrate characterization and design performance verification across corners.
However, ADE XL is the entry point for many other advanced design and analysis features of
interest to the circuit designer including:

 Circuit Optimization
 Parasitic-Aware Design (Pre-Layout Parasitic Estimation), post-layout parasitic
debugging, Layout Dependent Effects (LDE) analysis
 Yield Analysis – Monte Carlo, Advanced high yield estimation, Yield optimization,
Sensitivity analysis, Feasibility analysis
 Simulation dataset creation for the Electrically-Aware Design (EAD) layout
implementation flows
 Multi-Technology Simulation (MTS)

ADE XL multiple test and corner capabilities are particular useful when it is necessary to
perform design regression testing following circuit or other changes.

ACTION 47: Use the Library Manager to open the following test bench schematic in read-only
mode.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 36 of 68


PLL Verification Workshop Version 1.12

Library: zambezi45_sim
Cell: pll_vco_core_sim
View: adexl

ADE XL will start by loading all of the tests and display the ADE XL window will appear as a
new tab in the current schematic editor window as shown below.

Run Toolbar

Data View
assistant

ADE XL Main Canvas

Run Summary

The Virtuoso Schematic Editor supports tabs. Multiple cell views can be opened in the same
window. In the above window, the pll_vco_core_sim schematic is available in one tab and the
adexl view is available in a second tab.

The Data View assistant pane provides a single user interface to quickly view and specify
commonly used setup data. The Data tab on the Data View assistant pane allows one to quickly
view and set up tests, modify global variables, edit parameters, select corners, manage
documents, and setup states. The History tab on the Data View assistant pane allows one to
work with history items (previously run simulations).

The Run Summary assistant pane displays a summary of the simulation setup and the status of
simulation runs. The Run Summary assistant can be used to enable or disable sweeps, corners,
and the nominal corner.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 37 of 68


PLL Verification Workshop Version 1.12

The Run Toolbar is used to choose the run mode, start simulations using the Run button,
and stop simulations using the Stop button. Many different run modes are available using
the drop down combo box. However, during this tutorial, the focus will be only on the first run
mode - Single Run, Sweeps and Corners.

ACTION 48: In the ADE XL window, go to the Data View assistant and expand the Tests icon.
A list of 5 tests will be seen.

Each test corresponds to a single ADE state setup - like the ones we examined earlier for
measuring Kvco and phase noise. The first 2 tests measure the VCO center frequency for the
highest frequency band (bandNum=0) and the lowest frequency band (bandNum=31) respective
(Recall this VCO has 32 overlapping tuning bands in order to be span a sufficiently broad
adaptable to process, temperature and voltage variations). The remaining tests measure Kto
(temperature sensitivity), phase noise, and tuning sensitivity (Kvco) respectively.

ACTION 49: Double LMB select the Frequency_Max test (OR RMB select the test and select
the Open Test Editor… menu item). The ADE XL Test Editor window will now appear.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 38 of 68


PLL Verification Workshop Version 1.12

The ADE XL Test Editor is used to define the required analysis and output measurement setup
for the test. Its functionality is virtually identical to the ADE L setup window explored earlier.
From here one can load existing saved ADE L states, define analyses, create output
measurements, and perform simulations in debug mode. The measurement outputs defined here
will be automatically transferred to the Output Setup canvas located on the parent ADE XL
window.

ACTION 50: When done viewing the Test setup, close the Test Editor by selecting Session-
>Quit.

ACTION 51: Return to the ADE XL window. Expand the Outputs Setup tab to the right such
that all columns are visible up to an including the Units column.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 39 of 68


PLL Verification Workshop Version 1.12

In this panel, one can view all of the output measurements for all tests. This panel also allows
one to supply specifications for the measurements and units for documentation purposes. The
specification information is used to determine if the design is passing or failing to meet its
specifications. It can be a quick visual reference to determine the overall design state.

ACTION 52: Return to the ADE XL Data View assistant panel. Expand the Corners item.

As already mentioned, one of the principle advantages of ADE XL is the ability to conveniently
handle multiple design corners (PVT). Here one can see 4 different corner definitions (Nominal
corner plus 3 additional corners). We will now examine the setup in greater detail.

ACTION 53: Double LMB select any corner in the Data View assistant to display the Corner
Setup tool form.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 40 of 68


PLL Verification Workshop Version 1.12

The Corner Setup form contains all corner definitions. In addition to the Nominal corner there
are 3 additional named corners – each corresponding to a different process corner: Typical
process (named C1_Model_MC_VCO_Temp for this process model deck),
C2_Model_FF_VCO_Temp (Fast Process), and C3_Model_SS_VCO_Temp (Slow Process). Each
process corner contains 3 values (min, typ, max) for both temperature [-40, 27, 127] and supply
voltage [1.14, 1.2, 1.26]. This means that in reality there are 3x3 or 9 corners per column for a
total of 3x9 or 27 corners. Also notice that each corner has been enabled for all 5 tests. This
results in a total of 5x27 or 135 simulations.

Note: This is a relatively simple process corner setup. Most designs require more corners to
handle the independent variations for all of the different component types.

ACTION 54: OK the Corner Setup form when finished inspecting the corners/

ACTION 55: Return to corner list on the Data View assistant. In order to save time and reduce
the number corners to be simulation, disable the C2_Model_FF_VDD_Temp and
C3_Model_SS_VDD_Temp corners.

ACTION 56: While still on the Data View assistant panel, disable all tests except for
Phase_Noise and the Tune_Sense.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 41 of 68


PLL Verification Workshop Version 1.12

We should have now reduced the number of simulations to 2 Tests x 9 Corners = 18. This can be
verified by going to the Run Summary panel located in the lower left corner of the ADE XL
window.

Note: ADE XL support running multiple simulations in parallel. From the ADE XL- window-
>Option->Job Setup… one can specify both job distribution and the maximum number of
parallel jobs. This capability becomes especially important when large numbers of simulations
must be performed such as during corner analysis, Monte Carlo analysis, and circuit
optimization. For this workshop, we have assumed a practical limit of only one job at a time may
be executed on the local machine.

ACTION 57: In the Run Summary Panel, disable running the Nominal Corner. This corner is
already covered in the corner setup.

ACTION 58: When ready to begin the simulation, select the Run Simulation button located
near the top of the ADE XL window.

Hint: If the Run Simulation button is not visible, it may be necessary to widen the ADE XL
window sufficiently in order to make all of the menu buttons appear.

The corner simulations will begin running. You can monitor progress by checking the Run
Summary panel. Results on the main ADE XL canvas will also be updated as the individual
simulation tests complete. Results of tests which met their specification limits will be colored
green while tests which have failed will be colored red. If a test result is failing but nearly
passing will be colored yellow.

You will probably need to scroll the Results panel to the right in order to view the results for
most corners.

All 18 simulations should complete in ~10 minutes. Afterwards the ADE XL window Results
area should look similar to the following:

© 2014 Cadence Design Systems, Inc. All rights reserved Page 42 of 68


PLL Verification Workshop Version 1.12

ACTION 59: ***OPTIONAL *** If would like to view a set of saved results for all tests go to
the Data View assistant. Select the History tab, go to the PreLayout_Nominal and do RMB-
>Load Setup to Active. The archived results should now be visible in the ADE XL Results area.

ACTION 60: Close the ADE window when finished. Select File->Close. Also close the
schematic editor window.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 43 of 68


PLL Verification Workshop Version 1.12

4 Phase Frequency Detector (PFD)/Charge Pump (CP) Noise


Characterization
In this section, we will characterize the PLL Phase Frequency Detector (PFD) and Charge Pump
(CP) noise by performing a Periodic Steady State (PSS) analysis followed by a Full Spectrum
Periodic Noise (PNOISE) analysis.

ACTION 61: Use the Library Manager to open the following test bench schematic in read-only
mode.

Library: zambezi45_sim
Cell: pll_pfd_cp_sim
View: schematic
The schematic below will appear. This is the test bench we will be using to characterize the
PFD/CP contributed noise.

ACTION 62: View the properties of the VFref voltage source circled above (the 1st on the left),
by LMB selecting the voltage source, followed by pressing q key. The Edit Object Properties
form will appear, as shown below.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 44 of 68


PLL Verification Workshop Version 1.12

ACTION 63: View the properties of the VFcomp voltage source circled in the schematic (the
2nd on the left). The Edit Object Properties form will appear, as shown below.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 45 of 68


PLL Verification Workshop Version 1.12

Note that the two periodic noise sources are offset by dt - a design variable which we will set to
10ps later in the ADE simulation setup window. You can experiment with this variable to see
how the resulting noise changes (larger dt, higher noise). Ideally, you would put a value closer to
the situation when the PLL locks.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 46 of 68


PLL Verification Workshop Version 1.12

ACTION 64: Launch the Cadence Analog Design Environment (ADE) application. From the
schematic Editor window select Launch->ADE L. The following window will appear.

We will use ADE to setup and perform the Spectre APS simulation. We will load an existing
saved simulation setup.

ACTION 65: In the ADE window, select Session->Load State… The following form will
appear. Select the spectre_pnoise state as shown below and select the OK button located at the
bottom of the form.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 47 of 68


PLL Verification Workshop Version 1.12

The ADE window will be populated with the analysis and output setup information from the
saved state.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 48 of 68


PLL Verification Workshop Version 1.12

We will now review the contents of this setup beginning with the contents of the Design Variable
panel on the left.

Design Variables – This panel contains a list of the design variables used in the test bench
schematic. The design variables here set the supply voltage (vdd), the voltage source skew (dt),
and the voltage source frequencies (Fref, Fcomp).

Analyses – This panel contains the list of analysis to be performed. We will be running a PSS
analysis followed by pnoise.

Outputs – This is a list of outputs to be measured or plotted after all of analyses listed above
have been completed.

ACTION 66: In the Analysis panel in the ADE L window, double LMB click on the pss
analysis line. The following Choosing Analysis form will appear. When done viewing, press OK
to close the form.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 49 of 68


PLL Verification Workshop Version 1.12

Note the Shooting method is used, as the periodic waveforms VFref and VFcomp are of square
wave shape.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 50 of 68


PLL Verification Workshop Version 1.12

ACTION 67: In the Analyses panel in the ADE L window, double LMB click on the pnoise
analysis line, The following Choosing Analyses form will appear. When done viewing, press OK
to close the form.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 51 of 68


PLL Verification Workshop Version 1.12

Note that fullspectrum is selected for the simulator to automatically determine the Maximum
sideband.

ACTION 68: In the ADE L window, select the Netlist-and-Run icon to begin the simulation.
When it finishes (takes around 5 minutes), the following plot will appear on the waveform
viewing window.

-10 dB/dec

0 dB/dec

Place markers every decade as shown above. The dashed blue lines have been added as a visual
reference to slow ~-30dB/decade slope for the flicker noise and the thermal noise contributions.
From the graph above, you can see how to model the PFD/CP contributed noise into flicker noise
(-10 dB/dec) and thermal noise (0 dB/dec).

ACTION 69: Close the waveform plotting, ADE, and schematic editor windows.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 52 of 68


PLL Verification Workshop Version 1.12

5 Phase Noise Evaluation of the Closed-Loop PLL


In this section, we will revisit the same phase-domain model schematic used in the first part of
this workshop in order to evaluate the PLL closed-loop total output phase noise and the noise
components contributed by individual blocks noise sources injected into the loop, by running
multiple noise analyses (turn on all noise contributors followed by turning on individuals, one-
by-one) on the PLL phase domain model.

ACTION 70: Return to the schematic that was first opened in ACTION 2:

Library: zambezi45_sim
Cell: pll_phase_domain_sim
View: schematic

As indicated in the note next to the VCO noise source (top-right circle), this testbench models
both flicker and white noise contributions. Previously, we have discussed the VCO noise
characterization. Here we model the noise source by curve-fitting to the characterized noise.
The VCO2G5 instance represents the cascaded chain of the 5GHz VCO, Buffer, DIV2 divider
blocks.
The reference input phase noise (top-left circle) is estimated from commercially available crystal
oscillators. The phase-frequency detector and charge pump (PFD_CP) noise (middle-left circle)
is a curve-fit from a transistor-level Spectre pnoise simulation of the driven circuit PFD_CP
chain. The loop filter and low pass filter (LF_LPF) noise (middle-right circle) is the curve-fit
from noise analysis of the LF_LPF chain (the other approach is to use a real RC network to
replace the two svcvs components for the LF and LPF, set the resistor parameter “isnoisy =yes”,
and drop this noise injection). In our example, LF represents parallel branches of R2C2 and C1
shunt to ground. LPF represents a simple RC filter to suppress additional high frequency noise
from the Delta-Sigma Modulator (DSM).

© 2014 Cadence Design Systems, Inc. All rights reserved Page 53 of 68


PLL Verification Workshop Version 1.12

The DSM noise modeling methodology is described in the note below which is also located next
to the DSM noise source (bottom circle). The values are read from a pre-saved noise table file.

ACTION 71: Launch the ADE application. From the schematic Editor window select Launch-
>ADE L The following window will appear.

We will use ADE to setup and perform the Spectre APS simulations. We will load an existing
saved simulation setup.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 54 of 68


PLL Verification Workshop Version 1.12

ACTION 72: In the ADE window, select Session->Load State… The following form will
appear. Select the spectre_noise_total_components state as shown below and select the OK
button located at the bottom of the form.

ACTION 73: In ADE window, set the Plotting mode setting (window lower right corner) to
Append. Then select Simulation->Netlist and Run . It will take a few seconds to complete.
The plot as shown below should appear.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 55 of 68


PLL Verification Workshop Version 1.12

This is a plot of the total output noise.

ACTION 74: View the noise contributions from individual noise sources by individually
enabling the source. The noise source can be enabling the setting the design variables
ON_pfd_cp, ON_dsm, ON_vco, ON_lf_lpf, ON_in to 1 one at a time. Each of these variables
controls the 5 sources of noise in the schematic. For example, to turn on only VCO noise
contribution, perform the ACTION below.

ACTION 75: In the ADE window, select Variables->Edit. Set ON_vco value to 1, ON_pfd_cp
to 0, ON_dsm to 0, ON_lf_lpf to 0, and ON_in value to 0, as shown below.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 56 of 68


PLL Verification Workshop Version 1.12

ACTION 76: In Editing Design Variables window, click Apply & Run Simulation.

The plots will be appended as shown below.

TOTAL

VCO

As expected, the injected VCO phase noise is low pass filtered by the closed-loop PLL transfer
function to the output phase noise.

If you repeat the similar procedure for the other noise sources contributions, you will obtain the
following set of overlaid noise contribution plots.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 57 of 68


PLL Verification Workshop Version 1.12

TOTAL

VCO

LF_LPF

PFD_CP

DSM

REF_OSC

As expected, the injected Delta-Sigma Modular (DSM) noise is high pass filtered by the closed-
loop PLL transfer function to the output phase noise.

ACTION 77: Close the Waveform and ADE L windows. In the ADE window select Session-
>Quit. Select No if asked to save the ADE state.

5.1 (Optional) Using ADE XL to Analyze Noise Contributions


ADE XL can be used to quickly and conveniently generate the above collection of plots showing
the impact of each individual sub-block noise contribution to the total output noise.

ACTION 78: From the schematic editor window containing the phase domain schematic model,
select Launch ADE XL… The following form will appear. Select, Open Existing View and OK
the form.

ACTION 79: In the Open ADE (G)XL View form. Select the adexl_noise_contributions view
and OK the from.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 58 of 68


PLL Verification Workshop Version 1.12

The following ADE XL Window will appear.

In this example, we will define a corner for the same combination of noise source switch settings
used in the previous section. We can then run the closed-loop phase-domain analysis across these
corners to quickly generate the same plot as before.

ACTION 80: In the ADE XL window, expand the Corners setup located under the Data View
panel.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 59 of 68


PLL Verification Workshop Version 1.12

One corner has been specified for providing the total and individual noise source closed-loop
contribution plots

ACTION 81: In order to confirm the Corner setup, return to the Data View panel, select the
Corners item, and do RMB->Open Corners Setup…. The following form will appear

ACTION 82: Observe the ON_* variable setting for each corner. OK the form when finished.

We are now ready to start the ADE XL simulation.

ACTION 83: Run the simulations by selecting the button. The simulations should complete
within a few seconds. When finished, the ADE XL Results panel should look similar to the
following:

© 2014 Cadence Design Systems, Inc. All rights reserved Page 60 of 68


PLL Verification Workshop Version 1.12

ACTION 84: Go to ADE XL results panel and move the cursor to the single line containing the
zambez45_sim:pll_phase_domain_sim:1 test, select the output noise V/sqrt(Hz), and then do
RMB->Plot Across Corners.

The noise contributions should now be plotted.

ACTION 85: In the waveform plot window, expand the output noise V/sqrt(Hz) plots by LMB
selecting the + to the left of the output name.

The waveform plot window should now look as follows with each noise contribution plotted and
appropriately labeled.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 61 of 68


PLL Verification Workshop Version 1.12

ACTION 86: Close the waveform, ADE XL, and schematic editor windows.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 62 of 68


PLL Verification Workshop Version 1.12

6 Fractional-N PLL Functional Verification


In this section, we will verify the fractional-N PLL loop functionality by performing mixed-
signal simulations using the AMS Designer simulator. The primary digital block containing the
delta-sigma modulators and calibration circuits will be represented by verilog HDL (RTL or
gate verilog), while the other analog/mixed-signal blocks will be represented by VerilogAMS
analog behavioral models.
This functional simulation performs various tests. It begins by a power-up sequence in order to
reset the PLL to its initial default state. It then performs the RC loop filter and VCO calibration
sequences. Calibration will require locking of the PLL and bypassing the DSM circuitry. Finally,
the calibration circuitry is powered down and PLL is ready for normal operation.

ACTION 87: Use the Library Manager window to open the following ADE state view:

Library: zambezi45_sim
Cell: LP_pll_chip_sim
View: ams_function_pmc0_noCPF

The following ADE window will appear

ACTION 88: In the ADE window, click SessionDesign Window to display the schematic
window, as shown below.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 63 of 68


PLL Verification Workshop Version 1.12

The left block provides the stimulus for the Device Under Test (DUT) – the PLL - on the right.

If you descend down 2 levels into the DUT (PLL), you will see the core PLL loop with its
building blocks as shown below.

DIGITAL:
DSM & CAL

ACTION 89: In the ADE window, select SimulationNetlist and Run . The SimVision
Console and Design Browser windows will appear.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 64 of 68


PLL Verification Workshop Version 1.12

ACTION 90: In the SimVision Design Browser window, select FileSource Command Script.
Browse to open the simvision_LP_pll_chip_sim.svcf file located in the
$PROJECT/WORK/zambezi45_pll directory. Note: This is the same directory where you first
started Virtuoso. This file contains a saved configuration setup for the waveform display.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 65 of 68


PLL Verification Workshop Version 1.12

The SimVision Waveform window will appear:

ACTION 91: Select SimulationRun in the Waveform window to start the simulation. It will
take 70 minutes to finish. So you will likely choose to stop the simulation before it completes.
However, a copy of the saved simulation results has been provided. You will be asked to load
these results shortly. While the simulation is running you can update what is displayed in the
waveform window using the menu buttons located on the right side of the
Waveform window.

ACTION 92: Pause the simulation anytime by pressing the interrupt the simulator menu
button.

ACTION 93: In the Waveform window, select FileExit SimVision to exit SimVision. In
ADE Window, click SessionQuit to exit ADE. Close also the schematic window.

We will now view the saved completed simulation results in another SimVision session.

ACTION 94: Start the stand-alone SimVision. In the same UNIX terminal where you launched
Virtuoso, enter the following command:

% simvision &

ACTION 95: In the SimVision Design Browser, select FileOpen Database. Browse to open
the psf.trn file located in the following directory:

$PROJECT/WORK/pll_zambezi45/sim_saved/LP_pll_chip_sim/ams/config_pmc0_saved/psf

Select the Open & Dismiss button to complete the opening of the results database.

© 2014 Cadence Design Systems, Inc. All rights reserved Page 66 of 68


PLL Verification Workshop Version 1.12

ACTION 96: In the SimVision Waveform window, select FileSource Command Script.
Browse to Open the simvision_LP_pll_chip_sim_saved.svcf file located in the
verification_seminar/WORK/zambezi45_pll directory.

Here is the resulting plot:

© 2014 Cadence Design Systems, Inc. All rights reserved Page 67 of 68


PLL Verification Workshop Version 1.12

You can see the RC loop filter calibration results in the R trim value of ‘h7 (saved in rcal[3:0]
following startrccal long pulse of 1 and rccaldone short pulse of 1).

Also visible are the first VCO calibration results in the VCO band selection of ‘h0E and the
second VCO calibration results in the VCO band selection of ‘h14. The third one results in ‘h14
and the forth one results in ‘h13 (saved in vcocal[3:0] following each startvcocal long pulse of 1
and vcocaldone short pulse of 1).

You can also see VCO analog control signal vtune settling each time the target frequency is set
to a new frequency. PLL lock indicator plllock asserts 1 after the locking condition is satisfied.

ACTION 97: In the Waveform window, select FileExit SimVision to exit SimVision. In
ADE Window, click SessionQuit to exit ADE. Close also the schematic window.

ACTION 98: Exit virtuoso. In CIW, select FileExit.

END OF WORKSHOP

© 2014 Cadence Design Systems, Inc. All rights reserved Page 68 of 68