Final Project

Argana, Erwin M., Avelino, Anne Loraine L.,Corbillon, Rio Glowee M., De Leon, Roeden
V., Mercado, Cristopher John M., Nañoz, Allona Jane M., Valencia, Ellen Mhae M.

College of Engineering
School of Technology
First Asia Institute of Technology and Humanities

ABSTRACT- The circuit consists of three NOT gates and

an AND gate. The circuit requires four inputs. Three of
these four will be inverted. The modified inputs will be
relayed into an AND gate. The end result of the
configured circuit is a single output coming out from the
logic gate.

I. INTRODUCTION

The project consists of an AND gate which has four inputs.

Three of these inputs were inverter (NOT gate). The Figure I
digital Logic NOT Gate is the most basic of all the logical
gates and is sometimes referred to as an Inverting Buffer or The whole diagram consists of three NOT gates
simply a Digital Inverter. A Logic AND Gate is a type of and an AND gate. Inputs A, B, and C will pass through a
digital logic gate that has an output which is normally at logic NOT gate, also called inverter, while the input D will not.
They will then go through the 4-input AND gate and
level “0” and only goes “HIGH” to a logic level “1”
would produce a single output.
when ALL of its inputs are at logic level “1”. There are mainly
two applications of AND gate as Enable gate and Inhibit gate.
Enable gate means allowance of data through a channel while
inhibit gate is just the reverse of that process, i.e. disallowance
of data through a channel. NOT gates are also known as
inverter because they invert the output given to them and show
the reverse result. The objective of this project is to learn and
to understand the principle of the transistor.

II. CIRCUIT DESIGN AND DISCUSSION

The schematic diagram for the 4-input AND gate is

shown in Figure I. Figure II

Shown in Figure II is the input A connected to one of

the NOT gates. The gate sends 1 as output, if it receives 0
as input. Alternatively, if it receives 1 as input, it sends 0
as output. The same is true with inputs B and C. The
inverter consists of one of each the NMOS and PMOS
transistors. The PMOS transistor is connected to the
supply Vdd, while the NMOS transistor is connected to the
ground. The input goes in the junction of the gates of both
transistor.
Figure III
The schematic diagram is then translated to a
schematic for simulation, which is shown in Figure IV.
Each gate was manually created using transistors. By the
use of a LED as an indicator, we tested sets of inputs and
noted the corresponding output.

III. RESULTS AND ANALYSIS

The circuit is an AND gate that contains four(4)

inputs: three(3) NOT/inverters and one(1) AND gate. The
first three (3) inputs are inverters wherein they are also
considered as NAND gates because the result outputs are
the inversed of the outputs of the AND gate. The AND
gate truth table will also be considered but since the circuit
has NOT gates the output will be inversed.

AND gate Truth Table:

A B C D OUT
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
Figure III shows the 4-input AND gate. It will only 0 1 1 0 0
output 1 when all inputs are also 1. This means that if 0 1 1 1 0
either or all of its inputs are 0, the output will be 0. The
1 0 0 0 0
four NMOS transistors are all connected in series to the
1 0 0 1 0
supply Vdd. The other end of the series is then connected
1 0 1 0 0
to the parallel connection of four PMOS transistors, which
other ends are connected consequently to the ground. The 1 0 1 1 0
single output of the whole circuit then comes from the 1 1 0 0 0
junction between the series of NMOS and the parallel of 1 1 0 1 0
PMOS. 1 1 1 0 0
1 1 1 1 0

As we can see, the only output that has resulted to

short circuit(1) is the inputs having (0, 0, 0, 1). According to
the AND gate that has 2 inputs the circuit will be short if and
only if the inputs are all open(1) but since the first 3 inputs are
all 0, using the 3-input AND gate, the result is short(1) but
they are all inverter that’s why the result is inverted. Therefore,
the inputs are all short(1) that resulted to a short(1) circuit also.

IV. CONCLUSION

The circuit is compose of two basic schematic

techniques. The first is an inverter, it is done by
connecting an NMOS transistor to the ground and the
PMOS transistor to the source. This will result invert the
Figure IV
initial input. Secondly, the AND logic gate is composed
off four NMOS transistors in series connected to the
source. On the other side, four PMOS transistors to the
ground. Using this connections, a positive output will
occur if and only if the four input switches will be
shorted.
Argana, Erwin
AND gate requires an all 1 input to produce an
output of 1; neglecting this condition will lead to a 0
output. In simulation, 1 represents an open circuit. In this
project, learning’s from previous subjects can be applied,
like in determining how many possible inputs are there.
The formula 2n can be applied. Once the numbers of
possible inputs are determined, the truth table can be
done and by knowing the truth table, a proper schematic
using transistor can be analyzed and done. This is what
I’ve learned and can be concluded in making this project.
Understanding the uses and characteristics of a particular
transistor can greatly help in analyzing the proper output
of the circuit.
Avelino, Anne Loraine
The circuit gives two combination of schematic.
AND gate combines with the NOT gate schematic. It has
a four input that will produce only one input. The inputs
in the circuit are dependent to each of one. If input 1,2
and 3 is equal to zero and input 4 is equal to one the result
will function which it indicates as one output as we
consider our truth table.
Mercado, Cristopher John
Therefore, I conclude that it is important to know the
principle of the transistors and the logic gates (including
its inputs and outputs). The AND gate output is at logic
1 when, and only when all its inputs are at logic 1,
otherwise the output is at logic 0. While the NOT gate
output is at logic 0 when its only input is at logic 1, and
at logic 1 when its only input is at logic. That’s why it’s
called an inverter. The project consists of an AND gate
which has four inputs. Three of these inputs were
inverter (NOT gate). We need to understand fully the
principle because it’s very essential for us, ECE students.
Nañoz, Allona Jane
The four- input gate increases the number of state of
possibilities of the output because it has more input
terminals. The input can be short (1) or open (0).
According to the truth table of an AND gate, the output
of an AND gate will get a result of 1 if and only if all of
the input are short (1). Since the first three input of the
given circuit are all NOT, meaning the only output that
will make the circuit short is the (0, 0, 0, 1).
Valencia, Ellen Mhae

Corbillon, Rio Glowee

VI. REFERENCES
As the Information, age goes on, there seem to be an [1] http://www.electronics-tutorials.ws/logic/logic_2.html
unending call for new digital devices. A fundamental in [2] http://www.electronics-tutorials.ws/logic/logic_3.html
building digital circuits include the knowledge in logic [3] http://www.learnabout-electronics.org/Digital/dig21.php.
gates. Numerous applications of such concepts range [4] http://www.electronics-tutorials.ws/logic/logic_4.html.
from burglar alarms to disc drive read-write IC's.
Therefore, being adept in such concepts can be
considered vital to both old and aspiring electronics
practitioners.

De Leon, Roeden

In this project I conclude that AND gate need’s an

all input 1 or short to get an output of 1, since the circuit
have three inverters you need three input 0 or open
therefore if the input pass through in the inverters it
became 1 or short.