VDD

VDD
VDD

VDD

VDD

VDD
CLR
VDD VDD VDD VDD
PRE

CLR
D
VDD

VDD VD
VDD1 VDD2

VDD
0 0
VDD

clock_b
clock

VDD
PULSE 0 1 300p 10p 10p 700p 1.9n
VDD

Q
VDD

VDD
clock_b

VDD

VDD

VDD

VDD
D

clock
VDD VDD VDD VDD
clock_b

clock

.tran 10n uic

VDD

VDD
.include cmosedu_models.txt Q
VDD

VDD

clock

clock_b
clock_b

VDD
clock

VDD VDD

VDD

Vclock
PRE

PULSE(0 1 0.5n 10p 10p 0.2n 1n)

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