You are on page 1of 2

Gate Oxide Breakdown Failures Highlight Industry Need for New Electric...

Gate Oxide Breakdown Failures Highlight Industry Need for New Electrical
Rule Checking Tools
Posted Feb 10, 2011, by Battle of Fins and BOXes
Matthew Hogan
TSMC 28nm yield (SemiWiki)
Print this Post
DAC 2011 is upon us!
Mentor Graphics User to User (U2U)
TAGS: Low Power,
PERC, ERC, thin oxide, Gate Oxide Breakdown Failures Highlight Industry Need
for New Electrical Rule Checking Tools
Dawn at the OASIS
Designers are discovering a new class of design errors that is difficult to check using more traditional methods, and can
Layout Density and the Analog Cell
potentially affect a wide range of IC designs, especially where high reliability is a must. There errors require electrical
rule checking to complement the tradition layout checks. Effects of Inception

Electrical rules are relatively complex, non-standard, and growing in number and type, creating a need for a highly On-line session covering the DAC presentation for Calibre
flexible, user-configurable tool. ERCs are important, but particularly challenging in designs with multiple voltage domains xACT 3D
and mixed analog/digital circuits, such as low-power devices targeting mobile and other battery-powered applications.
You can't give stuff away fast enough
Designs that incorporate multiple power domain checks are particularly susceptible to subtle design errors that are
difficult to identify in the simulation space or with traditional PV techniques. Often these subtle errors don’t result in ARCHIVES
immediate part failure, but performance degradation over time. For example, Negative Bias Temperature Instability
December, 2012
(NBTI) leads to the threshold voltage of PMOS transistors increasing over time, resulting in reduced switching speeds
for logic gates. Another effect is Hot Carrier Injection (HCI), which alters the threshold voltage of NMOS devices over March, 2012
time. Soft breakdown (SBD) also contributes as a time-dependent failure mechanism, contributing to the degradation
effects of gate oxide breakdown. May, 2011

April, 2011
Some electrical rule checks are based on the netlist and include looking for floating devices, nets, or pins, detecting thin
gates connected to excessive voltages, checking for violations of the maximum allowed number of series pass gates, February, 2011
and finding issues related to level shifter designs. Other checks are performed using geometric layout information, such
as net area ratios for antenna rules, floating wells, and minimum “hot” NWELL width. January, 2011

November, 2010
An important application of ERC is verifying that electrostatic discharge (ESD) protection circuits are in place wherever
the device is vulnerable, whether those circuits are included in the schematic and netlist or not. To ensure a robust August, 2010
design, the ERC tool must go beyond simple schematic or netlist-to-layout verification and recognize where ESD
protection elements are needed, based on combined information from the netlist and the layout topology. June, 2010

May, 2010
In multiple power domains, other precautions have to be considered. For example, IP reuse may require more robust
rules to avoid device burnout at the system integration stage. This is particularly the case where an IP block is being April, 2010
re-targeted to a different process node or power domain. The introduction of lower voltage power domains is also an
area where IP reuse and the contribution to the overall reliability of the chip must be considered. Often, to attain lower March, 2010
voltage thresholds for lower power circuits, the oxide layer of a transistor is made thinner. While this has significant February, 2010
voltage and power benefits, there are potential problems when thin-oxide gates have paths to specific voltage rails. To
avoid long term damage to the gate over a period of time, which results in performance degradation, the voltage rail January, 2010
must be carefully chosen. A previous implementation may have the gate tied at a voltage that is too high for the current
December, 2009
November, 2009
Successful integration of physical IP blocks requires knowledge of the design hierarchy as well as the structure of
voltage domains and cell voltage constraints. Design hierarchy also comes into play when one set of rules is applied to October, 2009
upper layer interconnects and pad frames, while different rules are applied between blocks crossing multiple power
September, 2009
August, 2009
As ERC becomes more critical to producing a reliable product, designers and engineers are constantly discovering new
checks that they would like to make during verification. These checks are based on their accumulated knowledge and July, 2009
best practices of design groups; thus, there is no “standard” set of checks. Consequently, it is crucial that an ERC tool
June, 2009
be easily programmable, allowing users to adapt it quickly to new checks as they become needed.
May, 2009
Finding and Fixing Double Patterning Errors in 20nm Design
Physical Verification (20)
Double patterning brings a new set of design constraints to the 20nm node and it has caused designers to get very
DRC (18)
concerned about how they find and deal with DP related violations. In this presentation,...... View On-demand Web
Seminar → Calibre (17)

There is more information available on this topic as well as Calibre PERC, an ERC tool specifically developed to IC Design (14)
address advanced circuit verification issues, at
Design for Manufacturing (10)
/addressing-reliability-and-circuit-verification-challenges-with-calibre-perc-42217 and
/ic_nanometer_design/multimedia/circuit-verification-design-reliability. Design Quality (9)

1 of 2 2/3/2013 8:35 PM
Gate Oxide Breakdown Failures Highlight Industry Need for New Electric...

IC Verification (8)
Mentor will also be presenting on this topic at the free Tech Design Forum on March 10 in Santa Clara
( Look for the session “Successful Analog Mixed Signal Yield (7)
Design at Advanced Nodes.”
DAC (7)
Design Rules (6)
Matthew Hogan is a Calibre Marketing Engineer for Mentor Graphics. With over 15 years of design and field
experience, he is well-versed in the issues that are imposed on today's aggressive designs. Matthew holds a B.Eng
and an MBA. Visit Matthew Hogan's Blog →


ESD Design Rule Checking

How do you debug LVS?

More Blog Posts


Calibre Advanced Layout Analysis DSPF Back-Annotation Flow in IC

Station Schematic
ON-DEMAND WEB SEMINAR: If you have a Calibre
nmDRC-H license, you already have full access to a ON-DEMAND WEB SEMINAR: This 15 minute, multimedia
feature-rich toolbox that allows you to quickly design and demo and tutorial shows how IC designers can utilize IC
implement a broad range of layout analysis applications. Station Schematic to easily model parasitic capacitance
Attend this...... View On-demand Web Seminar → at each phase of the design cycle.... View On-demand
Web Seminar →
CAA Using Calibre YieldAnalyzer: It's
Not Just a Fab Problem Anymore Using Calibre PERC: Illustrated
ON-DEMAND WEB SEMINAR: During this web seminar ON-DEMAND WEB SEMINAR: This online demo shows
you will learn how Calibre YieldAnalyzer supports several how Calibre PERC can address reliability challenges that
flows and capabilities that allow designers to get the arise during the circuit and electrical verification process.
details they need to create DFM-aware designs and Calibre PERC is specifically designed to perform
enforce best practices...... View On-demand Web electrostatic...... View On-demand Web Seminar →
Seminar →

No one has commented yet on this post. Be the first to comment below.

Add Your Comment

Please complete the following information to comment or sign in.



(Your email will not be published)


I agree to the Terms of Use

2 of 2 2/3/2013 8:35 PM