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AMC13 Module

CMS MicroTCA Overview


E. Hazen – Boston University
Representing the work of J. Rohlf, S.X. Wu, A. Heister, C. Hill, D. Zou, C. Woodall
at Boston University
and the CMS Collaboration worldwide

See http://www.amc13.info for detailed documentation

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Outline
● CMS is going MicroTCA (.0 but not .4)
– Brief review of crate configuration
– Brief tour of cards in production
● AMC13XG Module status report
– Design Update
– 10G link testing
– TTC path temperature coefficient

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“MTCA.CMS” Crate
(note MTCA.0 but not necessarily MCTA.4)
Legacy TTC

TTS / Local Trigger
GOL / GBT from detector DAQ optical fibers

12 AMC Slots
Power

AMC13 AMC13
AMC

AMC

AMC

  Clocks
  Fast controls
Power

  DAQ
MCH1

Commercial MCH
  Management
  Ethernet

Fiber links to trigger
Ethernet
One specific geometry shown, others possible...
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“MTCA.CMS” Crate Requirements
● Dual-star backplane with redundant clocks
– Fabrics A, B routed star-wise to both MCH sites
– MCH2 CLK1 routed star-wise to AMC FCLKA
● Full-height, double width slots (pref. 12)
● Vertical cooling

Vadatech VT894 New Elma design (due late 2013)


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MicroTCA installation in CMS
● Subsystems installing uTCA now or soon:
– HCAL back-end
– TCDS system
– Global trigger
– Calorimeter trigger
– Muon trigger
● Incomplete list!

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TCDS: TTC/TTS replacement system
Several MicroTCA crates; various modules

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Calorimeter Trigger: Layer 1

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Calorimeter Trigger: Layer 2

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CMS Muon Track Finder
3 uTCA crates with various modules
(Virtex-7 Version soon)

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FC7 motherboard for TCDS modules

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The CERN GLIB
● Conceived as a test
board, but may well
end up installed at
P5 in various
systems
● 100+ produced!

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The AMC13XG

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What is AMC13?
● It is not an MCH! It is a 13th AMC in MCH-2 slot
● It distributes LHC clock / timing / controls to AMCs
● It collects DAQ data from AMCs
● It provides standard interface to CMS subdetectors:
– CMS DAQ via 1-3 optical fibers (currently at 5.0 Gb/s)
– TTC via 1300nm fiber @ 160Mb/sec biphase mark code
● Future TTC upgrade may be supported
– TTS via 1300nm fiber with protocol t.b.d.
● Latest version is 10Gb/s capable on backplane and optical
links

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History / Versions
● DTC (2010, 3 built)
– Based on NAT-MCH
XC3S200A / XC6V130T
– Prototype all functions
● AMC13 (2011, 17 built)
– Based on new T1
– New port assignments XC6SLX25T / XC6VLX130T (or 240T)
● AMC13XG (2013, 15 built)
– Redesigned T1 (only)
– 10Gb/s links
XC6SLX25T / XC7K325T

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AMC13XG (XG = Ten Gigabit)
Quad SFP+
Optical cage
AVR32 uC
T3 connector
MMC
(JTAG, I2C)

Spartan-6
FPGA

Kintex-7 FPGA
With heatsink

DDR3 SDRAM
Tongue 2 PCB
Clocks T3 connector board removed
Tongue 1 PCB to show internal detail
GbE, Fabric A

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AMC13XG Front Panel
LED2
LED1 (MMC Green LED)
(MMC Red LED)

Serial # SFP0
(DAQ Loop-back test)

USB 3x SFP+
(MMC console) 10Gb/s capable
SFP1
(DAQ Output)
Functions listed
for initial HCAL
JTAG firmware
(MMC AVR-32) SFP2
(Spare)

SFP3
JTAG (TTC/TTS)
(AMC13 FPGAs)

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Out of time!
● Summary:
– CMS adopting MTCA.0 widely
– “final” AMC13XG design complete
● built in qty 15
● Larger scale production starting late 2013
– Keeping an eye on MTCA.4, trying not to be
explicitly incompatible

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Reserve Slides

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Why Not .4? Mainly history...
● CMS converged on uTCA in 2009. Requirements:
– Vendor standard crate
– Backplane clock and TTC distribution
– DAQ with ~ 400MB/s * 2 per crate
– 12 slots preferred due to detector modularity
– “DTC” prototype completed (NAT-MCH mezzanines)
● Further details settled in 2010:
– MCH2 site used for AMC13 timing/DAQ module
– Only fabrics A, B used for infrastructure
– MCH2 tongues 3, 4 (fabrics D and up) available for user
applications
● This is not incompatible with MTCA.4
(though we “prefer” full-height AMC slots)
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AMC13XG Block Diagram
FP Input

CLK 40.xx CLK


CDS F/O To AMCs
TTC in IO
SFP
TTS out IO

DAQ
SFP+ GTX GTX
10 Gb/s Fabric A
GTX
Kintex 7 12 ports
DAQ  Gb/s
SFP+ GTX
10 Gb/s GTX (10 Gb possible)
GTX
Spare
SFP+ 512 Mbyte
10 G b/s
GTX DDR3
1600MT/s (6.4 GB/s)
GTP
IO
Fabric B
GbE GTP Spartan 6 80 Mb/s (TTC)
MCH1
IPMI MMC May upgrade to
uC ~ 320 Mb/s
Front JTAG
Panel
LEDs Flash
via T3
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AMC13 Clock Paths
Tongue 1 LVDS
Tongue 2
160MHz x 4 SY89872 SY89832
Divide by 40MHz Future Fanout
2/4 Option
For ext clock T2 U23
Div DS91M125
Recovered
Reset 1:4
Clock SY89832 40MHz
Fanout
SFP 160MHz Fanout Clock
To uTCA
T1 U3 backplane
1300nm receiver
IO_L10
(ATM type)
Compatible with M-LVDS
TTC fiber data MGT CLK
ADN2814
Clock/data MGT CLK
Recovery IO_L9
IC

T1 U2 Virtex 6
GCLK
Recovered Data
80 Mb/s LVDS

80Mb/sec
TTC data
Spartan 6 To uTCA
LX130T
● Low-jitter clock path Backplane
(Fabric B)
Measured jitter << 10ps (measurement limit)

● TTC through FPGAs, but re-timed to clock


at backplane

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AMC13 DAQ Path
MicroTCA
Backplane Fiber Out
5.0 Gb.s 5.0 Gb/s
Link (to 10 Gb/s)
Tx
FIFO DAQ
(in DAQ Tx
AMC) Fiber
FIFO
DAQ Tx
Possible 2nd
DAQ fiber
Event
Builder Note: Data could flow
through SDRAM

8k event
SDRAM
L1A
TTC
FIFO

IPbus control / monitor / local DAQ GbE

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AMC to AMC13 backplane link
AMC (e.g. HCAL uHTR)
12 point-to-point AMC13
links
BU provided firmware
80 Mb/s
LHC clock TTC Protocol
L1A TTC Fabric B
Receiver IO IO
BC0 etc

TP[0:7] Level 1
Trigger 5 Gb/s
BC0
8b/10b
Fabric A
MUX MGT MGT
CLK
16
Data
Level 2
Framing
DAQ
Buffer
Status

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Link to CDAQ
● 5.0 Gb/s optical link with “S-Link like” protocol
● Firmware developed by CDAQ (both ends)
– Error check coding, retransmission on error
– Error monitoring
– Full diagnostic and test capability from receive end

AMC13 FEROL
Data from 4 blocks (4Kbytes each)
-Receive block
FED -Ack. block
-DATA (64 bit) SFP itf
-Order blocks
Main

-WEN Logic

-UCTRL
-CLOCK
-Backpressure Block is sent until it is
-link down acknowledged
Send commands
Internal
Receive CMD
+ ACk (one at the time)

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T1 PCB Stackup
Nelco 4000SI-13 Material
1 GTL Impedance control (10G, SDRAM)
Prepreg 2.7
2 GP1 GND
Core 5.0
3 GP2 Split power
Prepreg 5.4
4 G1 Impedance control (SDRAM)
Core 5.0
Overall: 1.6mm 5 GP3 Split power
Prepreg 2.7
Signal: 18μm 6 GP4 GND
Core 5.0
Power: 36μm 7 GP5 Split power
Prepreg 5.4
8 G2 Impedance control (SDRAM)
Core 5.0
9 GP6 GND
Prepreg 5.4
10 G3 Impedance control (10G, SDRAM)
Core 5.0
11 GP7 GND
Prepreg 2.7
12 GBL Impedance control (10G, SDRAM)

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Top Layer 1 (signal)

HS to T2 1.8V 2.0V UTCA connector

DDR3 power

DDR3

Kintex-7

LS to T2

1.0V 1.2V 1.0V aux 3.3V Payload

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T2 PCB Stackup
Standard FR-4 Material

1 GTL Impedance control (TTC)


5 mil dielectric
2 GP1 GND
3 mil dielectric
3 GP2 Split power
9 mil dielectric

Overall: 1.6mm 4 G1 Inner signal


9 mil dielectric
Signal: 18μm 5 GP3 Split power
9 mil dielectric
Power: 36μm
6 G2 Inner Signal
9 mil dielectric

7 GP4 GND
5 mil dielectric
8 GBL Impedance control (TTC)

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T2 PCB Layout UTCA connector
Spartan 6 FPGA

Fabric B (TTC)

AVR 32 (MMC)

Clock fanout ICs

Connector to T3

Connector from T1

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Eye Patterns
on
Serial Links

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Backplane Test in VT892 Crate
Double-length (loop-back) test
MCH2 connector AMC1 connector

Jumper
GTX Board
~5 cm 20 cm (est)
AMC13XG PCB (Nelco) backplane PCB
(Kintex-7 FPGA)
Total length: 50 cm (3.3ns) NOTE: Preliminary!
still tweaking parameters

5.0 Gb/s 10.0 Gb/s

-0.5 Time (UI) +0.5 -0.5 Time (UI) +0.5


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10GB Fiber Loop-Back Test
MCH2 connector

GTX SFP Transceiver 30M Fiber


Avago AFBR-703SDZ
~3 cm
AMC13XG PCB (Nelco)
(Kintex-7 FPGA)

NOTE: Preliminary!
still tweaking parameters
10.0 Gb/s

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Temperature Sensitivity
of
AMC13 Clock network

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TTC Clock Delay Testing
904 (E. Laird) and at BU

Backplane
Coax Fiber AMC
Clock TTC
AMC13XG Test
Source Encoder
Rx
TTCex (904)
TTT (BU)

1
Oscilloscope
Coax
2

Goal: Measure phase shift between TTC input and clock on uTCA backplane

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Repeated Power Cycles
B. 904 (E. Laird et al)
Note: vertical scale inverted BU (D. Zou et al)

300 ps

700 s

● Measure TTC to custom AMC rx card ● Measure TTT to 3.5GHz diff probe
● 6 power cycles of whole uTCA crate on AMC card clock inputs w/ 100Ω
● Converges in O(200s) ● 6 power cycles of whole uTCA crate
● Slow drift seen but very low level, ● Vary from 10 min to 8h off time
● nearly unmeasurable with this setup

Hypothesis: temperature effect

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Delay vs position in AMC clock chain
2814 has no
Tongue 1 Tongue 2
delay/phase spec! 160MHz x 4 SY89872
LVDS
SY89832
Divide by 40MHz Future Fanout
2/4 Option
For ext clock T2 U23
Div DS91M125
Recovered
Reset 1:4
Clock SY89832 40MHz
Fanout
SFP 160MHz Fanout Clock
To uTCA
T1 U3 backplane
1300nm receiver
IO_L10
(ATM type)
Compatible with M-LVDS
TTC fiber data MGT CLK
ADN2814
Clock/data MGT CLK
Recovery IO_L9
IC

T1 U2 Virtex 6
GCLK
Recovered Data
80 Mb/s LVDS

0ps 150ps 150ps 300ps


80Mb/sec
TTC data
Spartan 6 To uTCA
LX130T
Low-jitter clock path
● Backplane
(Fabric B)
Measured
Measuredphase shift(measurement
jitter << 10ps vs warm-up limit)
All +/-
TTCatthrough
● leastFPGAs,
20ps but re-timed to clock These MLVDS drivers have spec'd
at backplane Tempco of 10 ps/°C

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Delay vs Temp @ BU
Change crate temp by blocking cooling.
Temp measured in air near AMC13XG

Δ delay at input to MLVDS drivers

Total plot range corresponds ~ to normal warm-up


160

140

120

100
Delay 80
Delay (ps)
(ps) Fitted
60

40
Slope: 25.8 ps/°C
20

0
24 25 26 27 28 29 30 31
-20
Temperature (°C)

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Phase shift: Conclusions
● Phase shift with temperature is not unexpected, and is
much less than the old TTCrx
● The phase is stable after 200s or so warmup
● It is fine for foreseen applications
● ~ half of the shift is in the clock/data separator IC which is
the heart of the design
● Improving it would require starting over on the clock path
design
● A modest improvement could be gained by switching from
uTCA-standard MLVDS to LVDS
– And, Mr Wu told us so from the start!

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AMC13 Board Stack
● Base configuration has only tongues 1, 2
● Base board - With optics and HS links (Fabric A)
● Clocks board - distributes LHC clock and controls
● Mezzanine connector for T3 with I2C
– T3 has JTAG and LEDs

T3 board
Provides JTAG / LEDs on front panel
T1 base board
Can be removed after initial programming MMC functions (Wisconsin firmware)
TTC optical rx
Crosspoint switch or other custom board 3x SFP+ cage
can be installed here (but see notes!) Cross-over GbE from MCH1
for controls and local DAQ

T2 Clocks board Connector to T3 provides:


Clock / controls fanout
Power
T4 JTAG (MMC and Xilinx)
T3 Utility SPI
Quad SFP+ T2 MMC serial console
Cage T1

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