Comandos Tcl

Crear Proyecto en Vivado

create_project -force {partial_reconfiguration} {/folder} -part xc7a15tcpg236-1

set_property simulator_language verilog [current_project]

update_compile_order -fileset sources_1

update_compile_order -fileset sim_1

Agregar archivos Fuente

add_files -norecurse /folder/Source/test.v

update_compile_order -fileset sources_1

update_compile_order -fileset sim_1

Activar reconfiguración Parcial

set_property PR_FLOW 1 [current_project]

Crear Partición reconfigurable

create_partition_def -name Partition_1 -module User1
 create_reconfig_module -name User1 -partition_def
[get_partition_defs Partition_1] -define_from User1

update_compile_order -fileset User2

Crear particiones Físicas

Startgroup
create_pblock pblock_Partition1
resize_pblock pblock_Partition1 -add SLICE_X14Y127:SLICE_X35Y147
add_cells_to_pblock pblock_Partition1 [get_cells [list Partition1]] -clear_locs
endgroup

Crear configuración de reglas de Síntesis e Implementación

create_pr_configuration -name PRconfig_1 -partitions [list Partition1: User1 Partition2:
User2 Partition3: User3]
create_run impl_2 -parent_run synth_1 -flow {Vivado Implementation 2017} -pr_config
PRconfig_1
Clear modulo para Partición reconfigurable
 create_reconfig_module -name Test -partition_def [get_partition_defs PR_1 ] -top
Module_11
 import_files -norecurse D:/MEGA/Hardware/HDL/hdl/Led.v D:/MEGA/Hardware/HDL/hdl/User1.v -
of_objects [get_reconfig_modules Test]
 set_property PARTITION_CELL_RMS [list Partition1:Test Partition2:Module_2
Partition3:Module_3 ] [get_pr_configurations PRconfig_1]
 set_property greybox_cells [list ] [get_pr_configurations PRconfig_1]