library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity main is
Port (
clk : in STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
r : out STD_LOGIC_VECTOR (2 downto 0) := "000";
g : out STD_LOGIC_VECTOR (2 downto 0) := "000";
b : out STD_LOGIC_VECTOR (1 downto 0) := "000"
);
end main;

architecture Behavioral of main is

signal hcounter : integer := 0;
signal vcounter : integer := 0;
signal tick : STD_LOGIC := '0';
begin

clk_process : process(clk)
begin
if(rising_edge(clk)) then
tick <= not tick;
if(tick = '1') then -- Happens at 25MHz (50MHz / 2)

-- Reset the counter if column/line finished or increment it

if(hcounter = 799) then
hcounter <= 0;
if vcounter = 524 then
vcounter <= 0;
else
vcounter <= vcounter + 1;
end if;
else
hcounter <= hcounter + 1;
end if;

-- Send a pulse of vsync to start a new column

if vcounter >= 490 and vcounter < 492 then
vsync <= '0';
else
vsync <= '1';
end if;

-- Send a pulse of hsync to start a new line

if hcounter >= 656 and hcounter < 752 then
hsync <= '0';
else
hsync <= '1';
end if;

-- If pixel time, draw something

if hcounter < 640 and vcounter < 480 then
--display a colour on the RGB signals once I have opamps to get
them through
--if hcounter < 213 then
 -- Blue line
--b <= "111";
--r <= "000";
--g <= "000";
--elsif hcounter < 426 then
-- White line
--r <= "111";
--g <= "111";
--b <= "111";
--else
-- Red line
-- r <= "111";
-- g <= "000";
-- b <= "000";
--end if;
else
--display black colour on the RGB signals
-- b <= "000";
-- r <= "000";
-- g <= "000";
end if;
end if;
end if;
end process;

end Behavioral;